2-Channel High Speed AD Module AN9238 User Manual

Part 1: 2-Channel High Speed AD Module AN9238

The ALINX high-speed AD module AN9238 is a 2-channel, 65MSPS, 12-bit analog-to-digital signal module. It utilizes the AD9238 chip from ADI Company, which supports 2-channel AD input conversion. The module features single-ended analog signal input with a voltage range of -5V to +5V and an SMA socket interface. It is equipped with a standard 0.1-inch pitch 40-pin female header for connection to FPGA development boards.

Figure 1-1: AN9238 Module Product Image: This image displays the ALINX AN9238 module, showing its circuit board populated with various electronic components, SMA connectors for signal input, a 40-pin header for FPGA interfacing, and the ALINX branding.

Part 1.1: AN9238 Module Parameter Description

The detailed parameters for the AN9238 high-speed AD module are as follows:

• AD conversion chip: 1 piece of AD9238
• AD conversion channel: 2 channels
• AD sampling rate: 65MSPS
• AD sampling data bits: 12 bits
• Digital interface level standard: +3.3V CMOS level
• AD analog signal input range: -5V to +5V
• Analog signal input interface: SMA interface
• Measurement accuracy: approximately 10mV
• Working temperature: -40°C to 85°C

Part 1.2: AN9238 Module Size Dimension

Figure 1-2: AN9238 Module Size Dimension: This diagram illustrates the physical dimensions of the AN9238 module, indicating a width of 81mm, a height of 51mm, and a component height of 21mm.

Part 2: AN9238 Module Function Description

Part 2.1: AN9238 Module Hardware Block Diagram

Figure 2-1: AN9238 Module Hardware Block Diagram: This block diagram outlines the module's internal structure. It shows two channels of 12-bit AD data and 65M clock inputs connecting to the dual-channel AD9238 chip. The AD9238's output is processed through an AD8138 chip for single-ended to differential conversion and an AD8065 operational amplifier. SMA connectors are used for AD1 and AD2 inputs, and a 40-pin connector interfaces with the FPGA.

For detailed circuit design of the AD9238, refer to the AD9238 chip manual.

Part 2.1: Single-ended Input and Operational Amplifier Circuit

The single-ended inputs AD1 and AD2 are received via two SMA headers (J5 or J6) and operate within a voltage range of -5V to +5V. On the FPGA development board, the AD8065 chip and voltage divider resistors scale this input voltage down to a range of -1V to +1V. Users can adjust the front-end voltage divider resistor values to accommodate a wider input voltage range. The conversion formula is given as: VOUT = (1.0/5.02)*VIN.

Voltage Comparison Table (AD Analog Input vs. AD8065 Output):

Part 2.2: Single-ended to Differential and AD Conversion

The input voltage range of -1V to +1V is converted into a differential signal (VIN+ - VIN-) by the AD8138 chip. The common mode level of this differential signal is determined by the CML pin of the AD chip.

Voltage Comparison Table (AD Analog Input vs. AD8065 Output vs. AD8138 Differential Output):

Part 2.4: AD9238 Conversion

The AD9238 is configured by default in offset binary mode. The table below shows the output data format for AD conversion.

Table 16: Output Data Format

With a VREF of 1V for the AD9238, the final analog signal input and AD conversion data are as follows:

The digital value converted by AD9238 is smallest at -5V input and largest at +5V input.

Part 2.6: AN9238 Digital Output Timing

The AD9238 dual-channel AD module features a +3.3V CMOS output mode with independent data and clock for channels A and B. The AD data conversion occurs on the rising and falling edges of the clock, allowing the FPGA to sample the AD data using the AD clock.

Digital Output Timing Diagram Description: This diagram illustrates the timing relationships between the analog input signals (ADC A, ADC B) and the digital output signals, including clock signals (CLK A, CLK B), multiplexer select, and data bits (e.g., A0 to A8, B0 to B8). It shows how data is captured relative to clock edges.

Part 2.7: The Pin Assignment of AN9238 Module

The following table lists the signals for the 40-pin extension interface. For specific user requirements, please refer to the schematic diagram.

Part 3: AD Sampling DEMO Program Description

The demonstration program dynamically displays waveforms generated by a signal generator using the Signaltap (chipscope) software. It also transmits collected AD data to the serial port regularly, allowing a serial debugging tool on the computer to display the actual collected AD data values.

The program comprises a top-level module named ad9238_test.v and three sub-modules: ad.v for AD data collection, volt_cal.v for voltage and hexadecimal-to-decimal format conversion, and uart.v for serial port transmission of the collected data's ASIC code.

FPGA Program Module Functions:

1. volt_cal.v: This data conversion module converts the 12-bit data collected by the AD module into 20-bit decimal voltage data. The most significant bit of the 12-bit data represents the sign (positive or negative). To calculate the voltage, the sign bit is removed first, and the remaining 11 bits are converted into a voltage value. The bcd.v program is used to convert 16-digit hexadecimal data into 20-digit decimal data.
2. uart.v: This serial port transmitting program sends 26 characters to the serial port to display the voltage values of channel 1 and channel 2. When transmitting the decimal voltage value, it needs to be converted into ASIC code. The program utilizes serial port transmitting and serial port clock generation routines, transmitting the voltage value to the PC's upper computer at a baud rate of 9600.

FPGA Program Block Diagram Description: The diagram shows the FPGA connected to the AN9238 module via input signals (ad1_in, ad2_in) and clock signals (ad1_clk, ad2_clk). Within the FPGA, modules like uart, volt_cal, sigaltap/chipscope, and a PLL are depicted, illustrating the data flow and processing.

Part 4: Hardware Connection and Testing

Connecting the AN9238 module to an FPGA development board is straightforward. Simply plug the 40-pin interface of the module into the expansion port of the development board (AX301B/AX4010 connect to J1 port, AX309 connects to J3). The following illustrates the hardware connection diagram of an ALINX AX301B FPGA development board and the AN9238.

Hardware Connection Diagram Description: The image shows an ALINX AX301B FPGA development board connected to the AN9238 module. A signal generator is also visible, set up to produce a -5V to +5V sine wave at a frequency of 200KHz. The FPGA development board is powered on.

Part 4.1: Take the AX301B Development Board as an Example

To perform testing with the AX301B development board:

1. Open "signaltap" within the Quartus software.
2. Download the "ad9238_test.sof" file.

Quartus Software Screenshot Description: This screenshot displays the Quartus software interface, specifically the Signal Tap Logic Analyzer setup, showing the project file and configuration options.

After downloading the file, run Signaltap. The waveform interface will then display a positive wave signal.

By changing the signal transmitter to generate a square wave of -5V to +5V, the AD channel will display a corresponding square wave. The signal can be observed in hexadecimal format by setting the display mode accordingly.

Signal Tap Logic Analyzer Screenshots Description: These images show the Signal Tap Logic Analyzer displaying captured waveforms, including sine and square waves, and their hexadecimal representations, demonstrating the module's response to different input signals.

Part 4.2: Take the AX309 Development Board as an Example

The following illustrates the hardware connection diagram of an ALINX AX309 FPGA development board and the AN9238.

AX309 Connection Diagram Description: This section would typically show a diagram of the AX309 board connected to the AN9238 module, similar to the AX301B example.

To proceed with testing on the AX309:

1. Download the "ad9238_test.bit" file using the Impact software.
2. Open the "chipscope" software.
3. Open the "ad9238_test.cpj" project within Chipscope.

Impact Software and Chipscope Project Description: Screenshots show the Impact software for downloading the bit file and the Chipscope Pro Analyzer interface with the project open dialog, indicating the necessary steps.

Click the "Open Cable/Search JTAG Chain" button to establish a connection to the FPGA development board.

JTAG Connection Description: An image shows the Chipscope Pro Analyzer interface with the option to open the JTAG chain, facilitating the connection between the software and the hardware.

Upon opening the "Bus Plot" interface, the waveform interface will display a sine wave signal.

Chipscope Waveform and Bus Plot Description: Screenshots from the Chipscope Pro Analyzer display captured waveforms and bus plots, showing the sampled data from the AD module, both as time-series data and in a bus plot format.

The specific data (in hexadecimal format) sampled by the AD module is displayed in the waveform window.

Part 4.3: Serial Display Voltage

The converted voltage values can also be observed through the serial port. The serial port's baud rate is configured to 9600. For instance, when the AD module receives a DC input voltage of +3.3V, the serial debugging assistant displays the corresponding voltage readings. Note that different modules may exhibit slight variations in these readings.

Serial Debugging Assistant Screenshots Description: Two screenshots of a serial debugging assistant tool are provided. The first shows voltage readings when the AD input is +3.3V, displaying values like AD1:+3.264V, AD2:+0.002V. The second screenshot shows readings when the DC voltage is changed to -3.3V, displaying values such as AD1:-3.310V, AD2:+0.000V.