ALINX AN706 8-Channel AD Acquisition Module User Manual

Part 1: 8-Channel AD Acquisition Module Parameters

• Module VPN: AN706
• AD Chip: AD7606
• Channel: 8-channel
• AD bits: 16-bit
• Max Sample Rate: 200KSPS
• Input Voltage Rate: -5V~+5V
• PCB layers of Module: 4-Layer, independent power layer and GND layer
• Module Interface: 40-pin 0.1 inch spacing female header, download direction
• Ambient Temperature (with power applied): -40°~85°, all the chips on module to meet the industrial requirements
• Input interface: 8 SMA interfaces and 16-pin headers with 2.54 pitch (Each channel has positive and negative two Pin)
• Measurement accuracy: Within 0.5mV

Part 2: Module structure

The 8-channel AD module structure is depicted in Figure 2-1. It shows the signal flow from the analog input SMA interfaces (V1-V8) through the AD7606 chip, which handles analog-to-digital conversion. The module utilizes an LT1117 for voltage regulation and a 2.5V reference voltage. Data is output via a 40-pin AD data output expansion port and a 16-pin AD signal input interface.

Part 3: AD7606 Chip Introduction

The AD7606 is a 16-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) available with eight, six, and four channels. Each part includes analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, and a 2.5 V reference.

The input clamp protection circuitry can tolerate voltages up to ±16.5 V. The AD7606/AD7606-6/AD7606-4 operate from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels.

The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin-driven, yielding improvements in SNR and reducing the 3 dB bandwidth.

Part 4: AD7606 Chip Functional Block Diagram

Figure 4-1 illustrates the functional block diagram of the AD7606 chip. It details the internal components including input channels (V1-V8) with clamp protection and track-and-hold (T/H) amplifiers, a second-order low-pass filter (LPF), an 8:1 multiplexer (MUX), a 16-bit successive approximation register (SAR) ADC, and a digital filter. Control signals like CONVST A, CONVST B, RESET, and RANGE are managed. The chip features a parallel/serial interface for data output (DB[15:0], DOUTA, DOUTB) and control inputs (CS, RD, PAR/SER/BYTE SEL, REF SELECT). It also includes an internal 2.5V reference voltage (REFIN/REFOUT) selectable via the REF SELECT pin.

Part 5: AD7606 Chip Timing Specification

Figure 5-1 shows the AD7606 timing diagrams, illustrating the sequence of operations for synchronous sampling using the parallel mode. The diagrams depict the CONVST A and CONVST B signals, which initiate conversion when tied together. The BUSY signal indicates the conversion status, going high during conversion and low upon completion. The CS/RD signal controls read operations, and FRSTDATA signals the availability of the first data byte. The data bus DB[15:0] carries the converted 16-bit values. The Chinese text "AD7606 通道进行同步采样, 使用并行模式" translates to "AD7606 channels perform synchronous sampling, using parallel mode".

Part 6: AD7606 Chip Pin Configuration

The AN706 8-channel AD module configures the AD7606's operating mode using pull-up or pull-down resistors on three configuration pins.

Reference Selection

The AD7606 supports external or internal voltage references. The REFIN/REFOUT pin can be used with an external 2.5V reference. The REF SELECT pin determines whether to use the internal or external reference. The AN706 module utilizes the internal 2.5V reference due to its high accuracy (2.49V~2.505V).

Data Acquisition Mode

The AD7606's AD conversion data acquisition can be in parallel or serial mode. The PAR/SER/BYTE SEL pin controls this setting. For the AN706 module, parallel mode is selected to read AD data.

Input Range Selection

The RANGE pin selects the input voltage range, either ±10 V or ±5 V. For the ±5 V range, 1 LSB = 152.58 µV. For the ±10 V range, 1 LSB = 305.175 µV. The AN706 module is designed to use the ±5V analog voltage input range.

Digital Filter and Oversampling

The AD7606 includes an optional digital first-order sinc filter, beneficial for applications requiring slower throughput rates or higher signal-to-noise ratio (SNR) and dynamic range. The oversampling ratio is controlled by the OS[2:0] pins, where OS2 is the MSB and OS0 is the LSB. These pins are latched on the falling edge of BUSY. The table below details the oversampling bit decoding for various oversample rates, affecting SNR, bandwidth, and maximum throughput frequency.

In the AN706 module's hardware design, the OS[2:0] pins are connected to the external interface, allowing an FPGA or CPU to control the filter and achieve higher measurement accuracy.

Part 7: AD7606 Chip ADC TRANSFER FUNCTION

The AD7606 outputs data in two's complement format. Code transitions occur at the midpoint between successive integer LSB values (e.g., 1/2 LSB, 3/2 LSB). The LSB size is calculated as FSR/65,536. Figure 7-1 illustrates the ideal transfer characteristic.

The transfer characteristics show the relationship between analog input voltage and ADC code. For a ±10V range, the formula is:±10V CODE = VIN × 32,768 × (REF / 10V / 2.5V)For a ±5V range, the formula is:±5V CODE = VIN × 32,768 × (REF / 5V / 2.5V)The LSB is calculated as:LSB = (+FS - (-FS)) / 2^16

The table provides specific LSB values for ±10V and ±5V ranges:

Part 8: Interface definition (The labeled pin on the PCB is pin 1)

The following table defines the pinout of the AN706 module's interface connector.

Part 9: AN706 Module Experimental procedure

1. First, connect the AN706 module to the 34-pin standard expansion port of the ALINX FPGA Development Board (ensure the development board is powered off).
2. Connect your signal source to the AN706 Module input connector (Note: AD port input range: -5V~+5V).
3. Download the program to the FPGA using the Quartus II or ISE software. For testing programs, send an email to rachel.zhou@alinx.com.cn.
4. Open the serial debugging assistant tool and configure the serial port's communication baud rate as follows.

   Figure 9-1 shows the "Serial Debugging Assistant Tool" interface, which allows configuration of COM port, baud rate (e.g., 9600), data bits, stop bits, etc.

5. The voltage values of the 8-channel signal input of the AN706 module will appear in the serial communication. Since the 8-way data is displayed in one line in the serial debugging assistant, it may be necessary to enlarge the interface for better readability.

   Figure 9-2 displays "Serial Communication" data, showing multiple lines of AD channel readings (e.g., AD1:+1.7518V).

   The initial data shown represents 8 channels without an external signal input, indicating a floating state, with AD conversion output data around 1.75V.

   Example: Connecting the input of channel 1 to the 3.3V test pin on the AN706 module using a DuPont line to test a 3.3V voltage.

   Figure 9-3 shows the physical connection of Channel 1 to a 3.3V test pin.

   After this connection, the measurement data for AD1 displayed on the serial interface is approximately +3.3074V. Figure 9-4 illustrates this "Test pin voltage display on the serial interface," showing the updated AD1 value.

Part 10: AN706 Module Measurement Accuracy

By measuring the applied voltage with a high-precision voltmeter, the actual measurement accuracy of the AD706 module is confirmed to be within 0.5mV across the -5V to +5V voltage input range.

Table 10-1 presents the results of testing eight channels with four different analog voltages. The first column shows data measured by a high-precision digital multimeter, while the subsequent eight columns display the AD module's corresponding measurements.

In this test routine, the oversampling override enable filter is not utilized to enhance the accuracy of the AN706 module. Users aiming for further improvements in sampling accuracy, where sampling speed is not critical, can configure this setting within the program. By adjusting the oversampling ratio, sampling magnification can be achieved.

Part 11: AN706 Module test program description

This section provides a brief description of the Verilog test programs and their underlying logic. Users can also refer to the code's comments for more details.

1. Top level program: ad706_test.vThis program defines the FPGA and AN706 modules, handles serial port communication for receiving and sending signals, and instantiates three subroutines: `ad7606.v`, `volt_cal.v`, and `uart.v`.
2. AD data acquisition program: ad7606.vAccording to the AD7606 timing, this program samples 16 analog signals, converting them into 16-bit data. It first sends the CONVSTAB signal to initiate AD data conversion and waits for the Busy signal to go low before reading data for channels 1 through 16 sequentially.

   The AD Voltage Conversion is calculated as: 1 LSB = 5V / 32758 = 0.15 mV.

3. Voltage conversion program for AD data: volt_cal.vThis program processes the 16-bit data collected by `ad7606.v`. It converts Bit[15] into positive and negative signs and Bit[14:0] into a voltage value using a specific formula, then converts this hexadecimal voltage value into a 20-digit BCD code.
4. Serial port sending program: uart.vThis program sends 8 channels of voltage data to the PC via UART. The serial port's transmit clock is derived by dividing the 50MHz frequency, and the baud rate is set to 9600bps.