ALINX ZYNQ7000 FPGA Development Board AC7Z020 System on Module

Version Record

Part 1: AC7Z020 Core Board Introduction

The AC7Z020 is an FPGA core board utilizing the XILINX ZYNQ7000 series chip, specifically the XC7Z020-2CLG400I. The ZYNQ chip's Processing System (PS) integrates dual ARM Cortex™-A9 processors, AMBA® interconnects, internal memory, external memory interfaces, and peripherals. The FPGA Programmable Logic (PL) section offers programmable logic cells, DSPs, and internal RAM.

This core board features two Micron MT41K256M16TW-107 DDR3 chips, each with a 512MB capacity, providing a 32-bit data bus width. The clock frequency for data read/write between the ZYNQ and DDR3 can reach up to 533MHz, supporting high-bandwidth data processing.

Connectivity is provided via two board-to-board connectors, extending USB ports, Gigabit Ethernet interfaces, SD card interfaces, and 48 MIO ports. Additionally, 122 PL side IO ports from BANK13, BANK34, and BANK35 are available. The IO levels for BANK34 and BANK35 can be adjusted by replacing the LDO chip. The board's compact size of 35 x 42 mm makes it suitable for secondary development.

Part 2: ZYNQ Chip

The AC7Z020 core board uses the Xilinx XC7Z020-2CLG400I chip from the Zynq7000 series. The PS system includes dual ARM Cortex™-A9 processors, AMBA® interconnects, internal memory, external memory interfaces, and peripherals such as USB, Ethernet, SD/SDIO, I2C, CAN, and UART interfaces. The PS can operate independently upon power-on or reset.

PS System Parameters:

• Dual-core ARM Cortex-A9 processor, ARM-v7 architecture, up to 1GHz.
• 32KB Level 1 instruction and data cache per CPU, 512KB Level 2 cache shared by 2 CPUs.
• On-chip boot ROM and 256KB on-chip RAM.
• External storage interface supporting 16/32-bit DDR2 and DDR3.
• Dual Gigabit NIC support with DMA, GMII, RGMII, SGMII interfaces.
• Dual USB2.0 OTG interfaces, each supporting up to 12 nodes.
• Dual CAN2.0B bus interfaces.
• Dual SD card, SDIO, MMC compatible controllers.
• 2 SPIs, 2 UARTs, 2 I2C interfaces.
• 4 pairs of 32-bit GPIO, with 54 (32+22) as PS system IO and 64 connected to PL.
• High bandwidth connection between PS and PL.

PL Logic Parameters:

• Logic Cells: 85K
• Look-up-tables (LUTs): 53,200
• Flip-flops: 106,400
• 18x25 MACCs: 220
• Block RAM: 4.9Mb
• Two AD converters for on-chip voltage, temperature sensing, and up to 17 external differential input channels (1MBPS).

The XC7Z020-2CLG400I chip has a speed grade of -2 (industrial grade) and a BGA400 package with a 0.8mm pin pitch.

Part 3: DDR3 DRAM

The AC7Z020 core board is equipped with two Micron 512MB DDR3 SDRAM chips (model MT41K257M16TW-107, compatible with Hynix H5TQ4G63AFR-PBI). The total bus width for DDR3 SDRAM is 32-bit, operating at a maximum speed of 533MHz (1066Mbps data rate).

The DDR3 memory system is directly connected to the memory interface of BANK 502 in the ZYNQ Processing System (PS).

The hardware design of DDR3 requires strict consideration of signal integrity, including matching resistor/terminal resistance, trace impedance control, and trace length control for high-speed and stable operation.

DDR3 DRAM Pin Assignment:

Part 4: QSPI Flash

The AC7Z020 core board is equipped with a 256MBit Quad-SPI FLASH chip, model W25Q256FVEI, operating at a 3.3V CMOS voltage standard. This non-volatile flash memory can serve as a boot device for storing boot images, FPGA bit files, ARM application code, and other user data.

The QSPI FLASH is connected to the GPIO port of BANK500 in the ZYNQ chip's PS section. The GPIO port functions need to be configured as the QSPI FLASH interface.

Configure chip pin assignments:

Part 5: Clock Configuration

The AC7Z020 core board provides an active clock for the PS system, enabling independent operation. The ZYNQ chip receives a 33.333333MHz clock input via the X1 crystal on the core board, connected to the PS_CLK_500 pin of the ZYNQ chip BANK500.

Clock pin assignment:

Part 6: Power Supply

The AC7Z020 core board is powered by DC5V, supplied by the carrier board. Power for BANK34 and BANK35 is also provided via the carrier board. The board utilizes four DC/DC power chips to convert the +5V input into +1.0V, +1.8V, +1.5V, and +3.3V supplies. The +1.0V output can reach 6A, +1.8V and +1.5V supplies provide 3A, and the +3.3V supply offers 500mA. J29 provides power to FPGA BANK34 and BANK35, defaulting to 3.3V. Users can change the VCCIO34 and VCCIO35 settings on the backplane to modify the power for these banks. The TPS51206 chip generates the VTT and VREF voltages required by DDR3.

The power-on sequence for the ZYNQ FPGA is designed as +1.0V -> +1.8V -> (+1.5V, +3.3V, VCCIO) to ensure normal operation. The IO levels of BANK34 and BANK35 are determined by the carrier board's VCCIO34 and VCCIO35 supply, with a maximum of 3.3V. If the carrier board provides a slower power-on sequence for VCCIO34 and VCCIO35, it may affect the core board's power-on sequence.

Part 7: AC7Z010 Core Board Size Dimension

Part 8: Board to Board Connectors Pin Assignment

The core board features two high-speed expansion ports using 120-pin inter-board connectors (J29/J30) for carrier board connection. The pin spacing is 0.5mm. J29 connects to 5V power, VCCIO input, some IO signals, and JTAG signals. J30 connects to the remaining IO signals and MIO. The IO level of BANK34 and BANK35 can be adjusted via the VCCIO input on the connector. The highest level does not exceed 3.3V. The AX7Z010 carrier board defaults to 3.3V. Note that BANK13 IO is not available for the AC7Z020 core board.

Pin assignment of board to board connector J29

Pin assignment of board to board connector J30