ARTIX-7 FPGA Core Board AC7200 User Manual

Version Record

Part 1: AC7200 Core Board Introduction

The AC7200 FPGA core board is based on XILINX's ARTIX-7 series 200T AC7200-2FGG484I. It is a high-performance core board offering high speed, high bandwidth, and high capacity, suitable for applications such as high-speed data communication, video image processing, and high-speed data acquisition.

This core board features two MICRON MT41J256M16HA-125 DDR3 chips, each with a capacity of 4Gbit. These two chips combine to form a 32-bit data bus, providing a read/write data bandwidth of up to 25Gb between the FPGA and DDR3, meeting high bandwidth data processing needs.

The AC7200 core board provides 180 standard IO ports of 3.3V level, 15 standard IO ports of 1.5V level, and 4 pairs of GTP high-speed RX/TX differential signals. Its compact size of 45*55 mm makes it ideal for secondary development.

Figure 1-1: AC7200 Core Board (Front View) Description: A view of the front of the AC7200 core board, showing the main FPGA chip, various connectors (including JTAG and power interfaces), LEDs (PWR, DONE, User LED), and a reset button.

Figure 1-2: AC7200 Core Board (Rear View) Description: A view of the rear of the AC7200 core board, primarily showing board-to-board connectors and other components.

Part 2: FPGA Chip

The FPGA used is the AC7200-2FGG484I from Xilinx's Artix-7 series, featuring speed grade -2 and industrial temperature grade, housed in an FGG484 package with 484 pins.

Xilinx ARTIX-7 FPGA Chip Naming Rules: The naming convention follows a structure: ARTIX | 7 | XC | 7 | A | ### | -1/-L1/-L2/-2/-3 | FB/FF/FG/FT/SB/CP/CS | V | 484 | C. Each segment denotes Generation, Family, Part Number, Speed Grade, Package Type, RoHS Compliance, Pin Count, and Temperature Grade.

Figure 2-1: The Specific Chip Model Definition of ARTIX-7 Series Description: A diagram illustrating the breakdown of the Xilinx FPGA part number.

Figure 2-2: FPGA chip on board Description: A close-up view of the Xilinx Artix-7 FPGA chip mounted on the core board.

Main Parameters of the FPGA Chip AC7200:

FPGA Power Supply System

Artix-7 FPGA power supplies include VCCINT, VCCBRAM, VCCAUX, VCCO, VMGTAVCC, and VMGTAVTT. VCCINT (1.0V) is for the FPGA core. VCCBRAM (1.0V) is for block RAM. VCCAUX (1.8V) is the auxiliary supply. VCCO provides voltage for FPGA BANKS (BANK0, BANK13-16, BANK34-35). For the AC7200, BANK34 and BANK35 are for DDR3 and use 1.5V, while other BANKS use 3.3V. BANK15 and BANK16 VCCO are LDO-powered. VMGTAVCC (1.0V) is for GTP transceivers, and VMGTAVTT (1.2V) is its termination voltage.

The power-up sequence requires VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If VCCINT and VCCBRAM share the same voltage, they can be powered simultaneously. Power-off is reversed. For GTP transceivers, the sequence is VCCINT, then VMGTAVCC, then VMGTAVTT. If VCCINT and VMGTAVCC share voltage, they can be powered simultaneously. Power-off is the reverse.

Part 3: Active Differential Crystal

The AC7200 core board is equipped with two Sitime active differential crystals: a 200MHz crystal (SiT9102-200.00MHz) for the system main clock and DDR3 control, and a 125MHz crystal (SiT9102-125MHz) as a reference clock for GTP transceivers.

Part 3.1: 200Mhz Active Differential Clock

Crystal G1 provides the 200MHz system clock. Its output connects to the FPGA's BANK34 global clock pin MRCC (R4 and T4). This clock can drive user logic, and users can configure internal PLLs and DCMs for different frequencies.

Figure 3-1: 200Mhz Active Differential Crystal Schematic Description: A circuit diagram showing the 200MHz crystal (G1), associated components (resistor R54, capacitors C128, C129, C130, C135, C137), a PLL, and output signals SYS_CLK_N and SYS_CLK_P.

Figure 3-2: 200Mhz Active Differential Crystal on the Core Board Description: A close-up view of the 200MHz crystal component on the core board.

200Mhz Differential Clock Pin Assignment:

Part 3.2: 148.5Mhz Active Differential Crystal

Crystal G2 is the 148.5MHz active differential crystal, serving as the reference input clock for the FPGA's GTP module. Its output connects to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6).

Figure 3-3: 148.5Mhz Active Differential Crystal Schematic Description: A circuit diagram showing the 125MHz crystal (G2), associated components (resistor R55, capacitors C131, C132, C133, C134, C136), a PLL, and output signals MGT_CLKO_P and MGT_CLKO_N.

Figure 3-4: 1148.5Mhz Active Differential Crystal on the Core Board Description: A close-up view of the 125MHz crystal component on the core board.

125Mhz Differential Clock Pin Assignment:

Part 4: DDR3 DRAM

The AC7200 core board is equipped with two Micron 4Gbit (512MB) DDR3 chips, model MT41J256M16HA-125. These chips support a maximum operating speed of 800MHz (1600Mbps data rate). The DDR3 memory system is directly connected to the BANK 34 and BANK 35 interfaces of the FPGA.

DDR3 SDRAM Configuration:

The DDR3 hardware design requires strict signal integrity considerations, including resistor matching, terminal resistance, trace impedance control, and trace length control for high-speed and stable operation.

Figure 4-1: The DDR3 DRAM Schematic Description: A schematic illustrating the connection between the FPGA (BANK 34 and 35) and the two DDR3 chips (U5, U6), showing data, address, control, and clock signals.

Figure 4-2: The DDR3 on the Core Board Description: A close-up view of the two DDR3 memory chips mounted on the core board.

DDR3 DRAM Pin Assignment:

Part 5: QSPI Flash

The AC7200 core board includes one 128MBit QSPI FLASH (W25Q256FVEI) operating at 3.3V CMOS. Its non-volatile nature makes it suitable as a boot device for storing system boot images, FPGA bit files, and application code.

QSPI FLASH Specification:

The QSPI FLASH connects to BANK0 (CCLK0) and BANK14 (D00-D03, FCS pins) of the FPGA.

Figure 5-1: QSPI Flash Schematic Description: A diagram showing the hardware connection between the FPGA (U1) and the QSPI Flash (U4), illustrating clock, chip select, and data lines.

Figure 5-2: QSPI on the Core Board Description: A close-up view of the QSPI Flash chip on the core board.

QSPI Flash Pin Assignments:

Part 6: LED Light on Core Board

The AC7200 FPGA core board features three red LEDs: PWR (power indicator), DONE (configuration status), and a User LED. The PWR LED illuminates when the board is powered, and the DONE LED lights up when the FPGA is configured. The User LED is connected to a BANK34 IO and can be controlled programmatically. It is lit when the connected IO voltage is low and off when high.

Figure 6-1: LED lights on core board Schematic Description: A schematic showing the connections of the PWR, DONE, and User LED (LED1) to the FPGA's BANK0 and BANK34.

Figure 6-2: LED lights on the Core Board Description: A view highlighting the physical location of the LEDs on the core board.

User LEDs Pin Assignment:

Part 7: Reset Button

A reset button is present on the AC7200 FPGA core board, connected to a normal IO of BANK34. It is used to initialize the FPGA program. When pressed, the signal input to the FPGA IO is low, validating the reset. When not pressed, the input is high.

Figure 7-1: Reset Button Schematic Description: A schematic showing the reset button's connection to the FPGA's BANK34.

Figure 7-2: Reset button on the Core Board Description: A close-up view of the reset button on the core board.

Reset button pin assignment:

Part 8: JTAG Interface

The AC7200 core board features a JTAG test socket (J1) for JTAG download and debugging. It supports TMS, TDI, TDO, TCK, GND, and +3.3V signals.

Figure 8-1: JTAG Interface Schematic Description: A schematic illustrating the JTAG interface signals and their connection to a 6-pin connector.

Figure 8-2 JTAG Interface on Core Board Description: A view of the JTAG interface connector (J1) on the AC7200 FPGA core board. It is a 6-pin, 2.54mm pitch test hole requiring a pin header for use.

Part 9: Power Interface on the Core Board

For standalone operation, the AC7200 FPGA core board includes a 2-pin power interface (J3). It is crucial not to supply power through both the J3 interface and the carrier board simultaneously to prevent damage.

Figure 9-1: Power Interface on the Core Board Description: A view of the 2-pin power interface connector (J3) on the core board.

Part 10: Board to Board Connectors

The core board is equipped with four 80-pin high-speed board-to-board connectors for interfacing with a carrier board. IO ports are routed differentially, with a 0.5mm pin spacing.

Board to Board Connectors CON1:

CON1 connectors (80-pin) interface with VCCIN (+5V) and ground on the carrier board, extending FPGA IOs. Notably, 15 pins of CON1 connect to BANK34, which is used for DDR3, operating at a 1.5V standard.

Pin Assignment of Board to Board Connectors CON1:

Board to Board Connectors CON2:

CON2 (80-pin female header) extends IO from BANK13 and BANK14 of the FPGA, both operating at 3.3V.

Pin Assignment of Board to Board Connectors CON2:

Board to Board Connectors CON3:

CON3 (80-pin) extends IO from BANK15 and BANK16 of the FPGA. It also carries JTAG signals. The default LDO voltage is 3.3V, but can be adjusted by replacing the LDO chip.

Pin Assignment of Board to Board Connectors CON3:

Board to Board Connectors CON4:

CON4 (80-pin) extends IO and GTP high-speed data and clock signals from BANK16. The IO voltage standard is adjustable via an LDO (default 3.3V). High-speed signals are differentially routed with equal length for signal integrity.

Pin Assignment of Board to Board Connectors CON4:

Part 11: Power Supply

The AC7200 FPGA core board is powered by DC5V via a carrier board or by the J3 interface when used alone. Avoid powering from both sources simultaneously to prevent damage. The power supply design is detailed in Figure 11-1.

Figure 11-1: Power Supply on core board schematic Description: A block diagram illustrating the power supply architecture, showing the input (+5V) and its distribution through various DC/DC converters and regulators (TPS54620, TLV62130RGT, TPS74801, TPS51200, SPX3819M5) to different voltage rails (+1.0V, +1.8V, +1.5V, +3.3V, VTT, VREF, VCCIO, MGTAVCC, MGTAVTT).

The board utilizes four DC/DC converters (TLV62130RGT) to provide +3.3V, +1.5V, +1.8V, and +1.0V, each capable of up to 3A. VCCIO, supplied by LDOSPX3819M5-3-3, powers BANK15 and BANK16, with adjustable IO voltage by changing the LDO. The 1.5V rail generates VTT and VREF for DDR3 using TI's TPS51200. MGTAVTT and MGTAVCC for GTP transceivers are generated by TI's TPS74801.

Power Supply Functions:

The Artix-7 FPGA requires a specific power-on sequence: 1.0V -> 1.8V -> (1.5V, 3.3V, VCCIO) and 1.0V -> MGTAVCC -> MGTAVTT. The circuit design ensures this sequence for proper operation.

Part 12: Structure Diagram

Figure 12-1: AC7200 FPGA Core board (Top view) Description: A diagram showing the top layout of the AC7200 FPGA Core board, indicating its dimensions of 55.0mm by 45.0mm, and the placement of key components and connectors.