ALINX AC7Z100C ZYNQ7000 FPGA Core Board

Version Record

Part 1: AC7Z100C Core Board Introduction

The AC7Z100C is an FPGA core board utilizing the Xilinx ZYNQ7000 series chip, specifically the XC7Z100-2FFG900. The ZYNQ chip's Processing System (PS) integrates two ARM Cortex-A9 processors, AMBA interconnects, internal memory, external memory interfaces, and peripherals. The FPGA fabric offers programmable logic cells, DSP slices, and internal RAM.

The core board is equipped with four Micron 512MB DDR3 chips (MT41J256M16HA-125), totaling 4GB. Two DDR3s are mounted on the PS and PL sides, forming a 32-bit bus width. The PS-side DDR3 SDRAM operates up to 533MHz (1066Mbps data rate), while the PL-side DDR3 SDRAM operates up to 800MHz (1600Mbps data rate). Additionally, two 256Mbit QSPI FLASH and 8GB eMMC FLASH chips are integrated for booting storage configuration and system files.

The board features four board-to-board connectors that expand the USB interface, Gigabit Ethernet interface, SD card interface, and other PS IO ports. It also extends the ZYNQ's 8-pair high-speed transceiver GTX interface and nearly all PL IO ports (144). The IO level of BANK12 and BANK13 can be adjusted by replacing the LDO chip. With a compact size of 80*60 mm, it is suitable for secondary development.

Figure 1-1: AC7Z100C Core Board (Front View)

Figure 1-2: AC7Z100C Core Board (Rear View)

Part 2: ZYNQ Chip

The AC7Z100C FPGA core board uses the Xilinx Zynq7000 series chip, module XC7Z100-2FFG900. The chip's PS system integrates two ARM Cortex-A9 processors, AMBA interconnects, internal memory, external memory interfaces, and peripherals, including USB, Ethernet, SD/SDIO, I2C, CAN, and UART interfaces. The PS can operate independently.

Figure 2-1: Overall Block Diagram of the ZYNQ7000 Chip

Main Parameters of the PS System:

• ARM dual-core Cortex-A9 processor, ARM-v7 architecture, up to 800MHz.
• 32KB L1 instruction and data cache per CPU, 512KB L2 cache, 2 CPU shares.
• On-chip boot ROM and 256KB on-chip RAM.
• External storage interface supporting 16/32-bit DDR2, DDR3.
• Two Gigabit Ethernet ports with support for DMA, GMII, RGMII, SGMII.
• Two USB 2.0 OTG interfaces, each supporting up to 12 nodes.
• Two CAN 2.0B bus interfaces.
• Two SD card, SDIO, MMC compatible controllers.
• 2 SPI, 2 UART, 2 I2C interfaces.
• 54 multi-function IOs configurable as normal IO or peripheral control.
• High bandwidth connection within PS and PS to PL.

Main Parameters of the PL Logic Part:

• Logic Cells: 444K
• Look-up-tables (LUTs): 277,440
• Flip-flops: 554,800
• 18x25MACCS: 2020
• Block RAM: 26.5Mb
• 16-channel high-speed GTX transceiver, supporting PCIe Gen2x8.
• Two AD converters for on-chip voltage, temperature sensing, and up to 17 external differential input channels (1MBPS).

The XC7Z100-2FFG9001 chip has speed grade -2, industrial grade, FGG900 package, and 1.0mm pin pitch.

Figure 2-2: The Specific Chip Model Definition of ZYNQ7000 Series

Figure 2-3: The XC7Z100 chip used on the Core Board

Part 3: DDR3 DRAM

The AC7Z100C core board is equipped with four Micron 512MB DDR3 chips (MT41J256M16HA-125). Two DDR3s are mounted on the PS and PL sides, forming a 32-bit bus width. The PS-side DDR3 SDRAM operates up to 533MHz (1066Mbps) and connects to BANK 502 of the ZYNQ PS. The PL-side DDR3 SDRAM operates up to 800MHz (1600Mbps) and connects to BANK33 and BANK34 of the FPGA.

Table 3-1: DDR3 SDRAM Configuration

The hardware design of DDR3 requires careful consideration of signal integrity, including matching resistor/terminal resistance, trace impedance control, and trace length control for high-speed and stable operation.

Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side

Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side

PS side DDR3 DRAM pin assignment:

PL side DDR3 DRAM pin assignment:

Part 4: QSPI Flash

The AC7Z100C core board features two 256Mbit Quad-SPI FLASH chips (W25Q256FVEI) providing an 8-bit data bus. These chips use a 3.3V CMOS voltage standard and serve as a non-volatile boot device for storing FPGA bit files, ARM application code, and user data.

Table 4-1: QSPI FLASH Specification

QSPI FLASH is connected to the GPIO port of BANK500 in the PS section of the ZYNQ chip. These PS ports need to be configured as the QSPI FLASH interface.

Figure 4-1: QSPI Flash in the schematic

Configure chip pin assignments:

Part 5: eMMC Flash

The AC7Z100C core board includes an 8GB eMMC Flash chip (THGBMFG6C1LBAIL) supporting the JEDEC e-MMC V5.0 standard HS-MMC interface with 1.8V or 3.3V level support. The eMMC Flash and ZYNQ connection has a 4-bit data width. Its large capacity and non-volatile nature make it suitable for storing ARM applications, system files, and user data.

Table 5-1: eMMC FLASH Specification

eMMC Flash is connected to the GPIO port of BANK501 in the PS section of the ZYNQ chip. These PS ports need to be configured as the SD interface.

Figure 5-1: eMMC Flash in the Schematic

Pin Assignment of eMMC Flash

Part 6: Clock Configuration

The core system provides reference clocks for the PS system, PL logic, and GTX transceiver, enabling independent operation. The clock circuit design is illustrated in Figure 6-1.

Figure 6-1: Clock source in the Core Board

PS system clock source:

The ZYNQ chip provides a 33.333MHz clock input to the PS section via the X4 crystal on the core board, connected to the PS_CLK_500 pin of BANK500.

Figure 6-2: Active crystal oscillator to the PS section

PS Clock Pin Assignment

PL system clock source:

A differential 200MHz PL system clock source is provided for the DDR3 controller and FPGA logic. The crystal output connects to the global clock (MRCC) of FPGA BANK34.

Figure 6-3: PL system clock source

PL Clock pin assignment:

GTX reference clock:

The core board provides a 125MHz reference clock for the GTX transceiver, connected to the reference clock input REFCLK1P/REFCLK1N of BANK111.

Figure 6-4: GTX Clock Source

Figure 6-5: Programmable Clock Source on the AC7Z100C FPGA Core Board

GTX clock source ZYNQ pin assignment:

Part 7: LED Light

The AC7Z100C FPGA core board has two red LEDs: a power indicator (PWR) and a configuration indicator (DONE). The PWR LED illuminates when the board is powered, and the DONE LED illuminates when the FPGA is configured.

Figure 7-1: AC7Z100C FPGA Core board LED light Hardware Connection

Part 8: Reset circuit

A reset circuit is present on the AC7Z100C core board. The reset input connects to a reset button on the carrier board, and the reset output connects to the ZYNQ chip's PS reset pin. Users can reset the ZYNQ system using the carrier board's buttons.

Figure 8-1: Reset circuit connection diagram

Reset button ZYNQ pin assignment

Part 9: Power Supply

The AC7Z100C FPGA core board is powered by DC 5V via a connection carrier board. The power supply design is shown in Figure 9-1.

Figure 9-1: Power interface section in the schematic

The 5V input generates a +1.0V ZYNQ core power using the MYMGK1R820FRSR DCDC power chip, capable of up to 20A. The 5V supply also powers the ETA1471 DCDC chip to generate four supplies: MGTAVTT, +1.5V, +3.3V, and another +1.5V. The MGTAVTT supply is generated by ETA8156. The VTT and VREF voltages for DDR3 (PS and PL) are generated by U7 and U10. IO power for BANK10 and BANK11 is supplied by a two-channel SPX3819M5-3-3. The LDO chip can be replaced to change IO voltage standards.

Power Distribution Table:

The ZYNQ FPGA requires a specific power-on sequence: +1.0V -> +1.8V -> (+1.5V, +3.3V, VCCIO12, VCCIO13) to ensure normal operation.

Part 10: AC7Z100C Core Board Size Dimension

Figure 10-1: AC7Z100C Core Board Size Dimension

Part 11: Board to Board Connectors Pin Assignment

The core board has four high-speed expansion ports using 120-pin inter-board connectors (J29-J32) for carrier board connection. The connectors are Panasonic AXK5A2147YG (core board) and AXK6A2337YG (carrier board). J29 connects BANK10 IO and BANK11 IO; J30 connects GTX transceiver signals; J31 connects JTAG and BANK35 IO (1.8V); J32 connects PS MIO, IO, and +5V power supplies for BANK11 and BANK12.

Pin assignment of J29 connector

Pin assignment of J30 connector

Pin assignment of J31 connector

Pin assignment of J32 connector