User Guide: EVAL-AD4080ARDZ
Product: Evaluating the AD4080 Fast Precision 20-Bit, 40MSPS, Differential SAR ADC
Document Number: UG-2305
Features
- Full-featured evaluation board for the AD4080 with power solution.
- Single differential channel and common-mode input available through board SMA connectors.
- Analysis | Control | Evaluation (ACE) Software plugin available for device configuration, data capture, and performance evaluation.
- Flexible analog front end (two stages).
- Out-of-box evaluation experience with the SDP-K1 demonstration platform (EVAL-SDP-CK1Z).
- On-board low noise power solution and 3.0V precision reference.
- On-board clock generation circuitry with sampling frequency selection via ACE software.
- Compatible with Arduino Uno form factor (Rev3 form factor).
Evaluation Board Kit Contents
- EVAL-AD4080ARDZ evaluation board.
- 12V AC/DC external wall mount adapter.
Equipment Needed
- PC running Windows 10 operating system or higher.
- EVAL-SDP-CK1Z digital host controller board and supporting USB cable (referred to as the SDP-K1).
- Differential precision signal source (ADMX1001B precision signal source preferred).
- 7V to 12V DC source (12V AC/DC external wall mount adapter supplied with evaluation kit).
- Two Subminiature Version A (SMA) to SMA cables to connect a differential signal source to the evaluation board.
General Description
The EVAL-AD4080ARDZ evaluation board enables quick and easy evaluation of the performance and features of the AD4080. It is designed to demonstrate the AD4080's performance within the ACE software environment and supports the following AD4080 features:
- Serial peripheral interface (SPI) complementary metal-oxide semiconductor (CMOS) data output interface (read from first-in, first-out (FIFO)).
- Analog-to-digital converter (ADC) configuration via SPI.
- Internal or external generation of 1.1V regulated supply rails (external by default).
- Sampling rate capability 40/20/10MSPS (software selectable in ACE).
The EVAL-AD4080ARDZ is designed for use with the System Demonstration Platform (SDP-K1) board to facilitate communication with the AD4080, enabling ADC configuration and data capture. The SDP-K1 controller board also provides the communication link to the host PC and the ACE software plugin. The EVAL-AD4080ARDZ evaluation board conforms to the Arduino Uno Shield mechanical and electrical standards for interfacing with the SDP-K1.
The EVAL-AD4080ARDZ evaluation solution includes AD4080 industrial input and output (IIO) firmware application drivers for device configuration and ADC data capture, as well as the AD4080 ACE plugin graphical interface (GUI) for performance evaluations.
For full details, consult the AD4080 data sheet in conjunction with this user guide.
Evaluation Board Hardware Guide
Hardware Overview
A simplified block diagram of the EVAL-AD4080ARDZ hardware is shown in Figure 3. This evaluation board showcases the performance and features of the AD4080, highlighting recommended companion components. The EVAL-AD4080ARDZ includes all circuitry necessary to operate the AD4080.
Figure 3: Simplified Block Diagram of the Evaluation Board: Depicts the main functional blocks including Stage 1 amplifiers, AD4080 ADC, voltage reference, power generation, clock generation, and digital interface, showing their interconnections.
Refer to the Analog Input Circuit, Voltage Reference, Power Supplies Generation, Conversion and Data Clock Generation Circuit, and Digital Interface sections for detailed specifics on each circuit block. For modifiable blocks, see the Supported Configurations section.
Figure 4: EVAL-AD4080ARDZ Evaluation Board Circuitry Locations—Top Side: Illustrates the physical layout of key components on the top side of the evaluation board, including amplifiers, the AD4080 chip, voltage regulators, and connectors.
Figure 5: EVAL-AD4080ARDZ Evaluation Board Circuitry Locations—Bottom Side: Shows the physical layout of components on the bottom side of the evaluation board.
Analog Input Circuit
The EVAL-AD4080ARDZ features a two-stage, precision signal conditioning circuit designed for flexibility in optimizing signal chain performance. In its default configuration, a differential 6V peak-to-peak (p-p) input signal with a common-mode voltage of 1.5V results in a full-scale measurement from the ADC. The typical supported input frequency range is DC to 1MHz.
Recommendations for signal chain configuration for specific bandwidths are in the Analog Front End (AFE) Considerations section.
Input Stage (Stage 1)
Stage 1 uses a pair of LT6236 operational amplifiers (op amps) for their wideband (90MHz), low noise, favorable distortion, and low power characteristics. The stage is configured for differential input, differential output, noninverting, unity-gain operation, presenting a high impedance to the signal source. With ±5V and -4V supply rails, the LT6236 inputs have a valid range of approximately -2V to +4V. A common-mode voltage of 1.5V is close to ideal for maximizing voltage range and minimizing distortion.
Figure 6: Stage 1 Simplified Schematic: Illustrates the input stage configuration with LT6236 op amps, feedback resistors (RFB), and input resistors (RG).
Configurable options for Stage 1 include:
- Stage bandwidth: No explicit bandwidth limiting (default) or band limiting via RC input filter and/or capacitors across amplifier feedback.
- Stage gain: Unity gain (default) or noninverting gain setting.
- Stage bypass: No bypass (default), Bypass Stage 1, or Bypass Stage 1 along with Stage 2 for using an amplifier mezzanine card (AMC).
- Input signal type: Differential (default) or Single-ended.
Fully Differential Amplifier Stage (Stage 2)
Stage 2 uses an ADA4945-1 fully differential amplifier configured for unity gain. The clamp pins (-VCLAMP and +VCLAMP) are connected to GND and VREF, limiting the output range to approximately ±500mV beyond these nodes to protect the ADC from overdrive.
The common-mode input of the ADA4945-1 is floating by default, internally biased to the midpoint between the output voltage clamps (1.5V). In its default configuration, this stage has a 3dB cutoff frequency of 1.1MHz.
Figure 7: Stage 2 Simplified Schematic: Shows the ADA4945-1 differential amplifier configuration.
Configurable options for Stage 2 include:
- Stage bypass: No bypass (default) or Bypass Stage 2.
- ADA4945-1 power mode: Full power mode (default) for maximum bandwidth and best distortion, or Low-power mode for reduced power consumption at the cost of performance.
- Alternative amplifier installation: Options include ADA4940-1 or ADA4932-1 (footprint compatible but require pin connection changes; not included on the board).
- Stage bypass: No bypass (default) or Bypass along with Stage 1 for using the AMC.
Voltage Reference
The AD4080 requires an external 3V voltage reference for specified performance. The AD4080 includes internal reference buffers, simplifying reference selection. The evaluation hardware primarily uses the LTC6655-3 (U6) for its exceptional noise performance (0.25ppm p-p at 0.1Hz to 10Hz), 0.025% initial accuracy, and 2ppm/°C low temperature drift.
An alternative reference, the LT6657-3 (U7), is also mounted. To use it, R133 must be moved to R66, and the R127 0Ω link must be placed. A third option, the ADR4530B, has a footprint on the board and can be mounted with configuration changes (R131 and R132 populated, R133, R127, R66 removed).
Table 1: 3V Reference Comparison: Compares LT6657, LTC6655, and ADR4530B based on accuracy, temperature coefficient, noise, load, regulation, supply, shutdown, protection, current limit, thermal protection, shunt mode, supply current, and operating temperature.
Common-Mode Circuit
The AD4080 features a common-mode voltage generation feature, providing a voltage equal to VREF/2 via the CMO pin. This is useful for biasing front-end stages. Alternatively, the ADA4945-1 can set the output common mode to the midpoint of its output clamping pins (1.5V).
Configurable options include:
- FDA common-mode setting: Internal (default, ADA4945-1 sets midpoint) or External (using CMO voltage from ADC).
- Common-mode signal buffering: No buffering (default) or buffering through an ADA4807-2 amplifier (necessary for additional load on CMO output; note output impedance of 700Ω).
Power Supplies Generation
The EVAL-AD4080ARDZ operates from a 7V to 12V supply via an AC/DC wall adapter. This input is regulated down using switching and linear dropout (LDO) regulators to generate necessary power rails.
Figure 8: Power Circuitry Simplified Schematic: Illustrates the power supply generation path, showing regulators like LT8606, ADP150, MAX38912, LT3093, and their outputs for various supplies (ADC supply, AFE supply, reference supply, oscillator supply).
AD4080 Power Supply
The AD4080 requires three main power supplies: VDD33 (3.3V analog), VDD11 (1.1V ADC core), and IOVDD (1.1V digital interface). The board includes integrated power supply decoupling.
Configurable options for the 1.1V rails (VDD11 and IOVDD) include:
- On-board generated rails (default, from MAX38912 regulators U18 and U19).
- Internal AD4080 LDO regulator (enabled by applying a voltage to the VDDLDO pin).
- Off-board external supply.
The 3.3V rail source is:
- On-board generated rail (default, from ADP150 LDO regulator U16).
- Off-board external supply.
Amplifier Power Supply
The signal conditioning circuitry operates from +5V and -4V rails. The U1 and U2 amplifiers use the +5V VDD_AFE and -4V VSS_AFE rails. The U3 amplifier uses +5V VDD_AFR and -4V VSS_AFE rails. The common-mode buffer A5 amplifier uses a unipolar +5V 5V_SUPP rail, with its negative rail connected to ground.
Conversion and Data Clock Generation Circuit
The EVAL-AD4080ARDZ generates low jitter conversion (CNV+) clocks for the AD4080's full operating range, enabling fidelity processing of full-scale input signals up to 1MHz. The circuit uses 40MHz (Y1), 20MHz (Y2), and 10MHz (Y3) CMOS reference oscillators. The selected oscillator signal is fed to the CNV+ pin. Software in the ACE application selects the conversion frequency by enabling the appropriate oscillator.
Figure 9: Simplified Diagram of the Clock Circuitry: Illustrates the clock generation using multiple oscillators and their connection to the AD4080's CNV+ pin, along with digital interface signals.
Digital Interface
The EVAL-AD4080ARDZ uses the V3 Arduino connector (P4, P6, P7) from the SDP-K1 controller board for ADC device configuration via 4-wire SPI, reading conversion results, and controlling conversion. The SDP-K1 board acts as the communication medium between the ACE Software plugin and the evaluation hardware.
The AD4080 operates with a 1.1V digital interface supply. SN74AUP1T34QDCKRQ1 unidirectional and SN74AVC1T45DCKR bidirectional level translators are used to interface between the AD4080's 1.1V logic and the SDP-K1's 3.3V logic.
Evaluation Hardware Setup Procedure
Follow these steps to prepare the hardware for evaluation:
- Ensure jumper P14 on the SDP-K1 board is set for VIO_ADJUST of 3.3V.
- Connect the EVAL-AD4080ARDZ board to the SDP-K1 board as shown in Figure 10.
- Connect the 12V DC power supply (from the wall adapter) to the SDP-K1 board barrel jack (P15). The green (DS1), blue (DS2), and blue (DS3) LEDs should illuminate.
- Connect the USB cable from the PC to the SDP-K1 board's P2 USB-C connector. The orange DS1 LED on the SDP-K1 board should light up.
- Set the EVAL-AD4080ARDZ configuration jumpers (JP1 to JP6) as shown in Figure 10: JP1, JP3, JP6 ON; JP2, JP4, JP5 OFF.
- Ensure switch (S1) Positions 1 to 4 are all OFF.
- The hardware is now ready for use with the ACE Software.
Figure 10: EVAL-AD4080ARDZ Jumpers JP1 to JP6 Setup: Diagram illustrating the jumper configuration for the evaluation board.
Evaluation Software Installation
The ACE Software is a desktop application for evaluating and controlling Analog Devices products. The EVAL-AD4080ARDZ hardware is controlled and configured via the ACE Software with its corresponding plugin.
To install the ACE Software:
- Download the ACE Software package from the Analog Devices website.
- Click 'Download ACE Installer' to get the installer file.
- Run the installer and follow the on-screen instructions.
To install the EVAL-AD4080ARDZ plugin:
- Run the ACE Software and navigate to the Plug-in Manager in the ACE sidebar. Select 'Available Packages'.
- From the list, select 'Board.AD4080' (use the Search field if needed) and click 'Install selected'.
Evaluating the AD4080 with the ACE Software
Once hardware setup and software installation are complete, launch the ACE software for evaluation.
Upon launching ACE, the EVAL-AD4080ARDZ is automatically detected and displayed in the 'Attached Hardware' panel (highlighted in yellow in Figure 11).
Figure 11: Auto-Detection of the Evaluation Board in the ACE Start Tab: Screenshot of the ACE software's start tab, showing the auto-detection of the EVAL-AD4080ARDZ evaluation board.
If prompted with an 'ACE - Tinyiiod Firmware Required' message (as shown in Figure 12), click OK to program the SDP-K1 board with the necessary firmware.
Figure 12: ACE - Tinyiiod Firmware Required Message: Screenshot of the ACE software's firmware requirement prompt.
Double-clicking the EVAL-AD4080ARDZ icon opens a new tab displaying a block diagram of the evaluation board (Figure 13).
Figure 13: EVAL-AD4080ARDZ Tab Open in the ACE Software: Screenshot presenting a board-level view of the EVAL-AD4080ARDZ within the ACE software.
Double-clicking the AD4080 in the block diagram opens an AD4080 tab with an 'INITIAL CONFIGURATION' panel, the AD4080 chip's block diagram, and 'Proceed to Memory Map' and 'Proceed to Analysis' buttons (Figure 14).
Figure 14: AD4080 Tab in the ACE Software: Screenshot of the AD4080 specific tab within the ACE software, showing initial configuration options and navigation buttons.
These buttons lead to tabs for evaluating the AD4080 chip. The sampling frequency can be configured here, affecting clocking components and data synchronization. The default sampling frequency is 40MHz. Maximum sample size can be set to 16384, and minimum to 1.
AD4080 Memory Map
Clicking 'Proceed to Memory Map' opens the AD4080 Memory Map tab (Figure 15). This tab displays and allows reading/writing of AD4080 registers. For normal operation, no register modifications are required.
Figure 15: AD4080 Memory Map Tab in the ACE Software: Screenshot of the AD4080 Memory Map tab in the ACE software, displaying AD4080 registers.
Analysis Tab
Clicking 'Proceed to Analysis' opens the ANALYSIS tab for data capture and analysis.
Figure 16: Analysis Tab in the ACE Software: Screenshot of the Analysis tab in the ACE software, detailing the CAPTURE, ANALYSIS, and RESULTS panels and the data plot area.
The ANALYSIS tab has three collapsible panels: CAPTURE (for sample acquisition settings), ANALYSIS (for frequency domain analysis options), and RESULTS (for metrics of the current dataset). The data plot area displays results.
Datasets can be displayed as a time-domain waveform (default), a frequency-domain plot (FFT), or a histogram, selected via buttons left of the CAPTURE panel.
Time Domain (Waveform) Plot
The active dataset is displayed as a time-domain waveform by default (Figure 17). The RESULTS panel shows time-domain metrics like minimum, maximum, average, and RMS values.
Figure 17: Dataset Plotted as Time Domain Waveform: Screenshot showing the acquired data displayed as a time-domain waveform in the ACE software.
Frequency Domain (FFT) Plot
Clicking the FFT area displays the dataset's Fast Fourier Transform (FFT) plot (Figure 18). The RESULTS panel shows frequency-domain metrics such as SNR, DR, SINAD, noise, and THD.
Figure 18: Dataset Plotted in the Frequency Domain: Screenshot showing the acquired data displayed as a frequency-domain (FFT) plot in the ACE software.
Histogram Plot
Clicking the Histogram area displays the dataset as a histogram (Figure 19). The vertical axis shows occurrences (bin hits), and the horizontal axis can represent code or voltage amplitude bins. The RESULTS panel provides histogram-specific metrics.
Figure 19: Dataset Plotted as a Histogram: Screenshot showing the acquired data displayed as a histogram in the ACE software.
Supported Configurations
This section details hardware and software configurations supported by the EVAL-AD4080ARDZ.
Analog Front-End (AFE)
Stage 1 Bypass
Stage 1 can be bypassed to allow direct drive of Stage 2 from the SMA connectors. To bypass Stage 1:
- Remove R3, R4, R9, and R10 to disconnect Stage 1 amplifiers.
- Populate R5 and R6 with 0Ω resistors to create the bypass path.
- Close Switch 1 and Switch 2 from Switch Array S1 (see Table 2) to power down unused amplifiers U1 and U2.
Stage 1 Gain
Stage 1 amplifiers are configured for unity gain by default but can be set to a noninverting gain configuration using the formula: Gain = 1 + RFB / RG. Changes involve selecting feedback resistors (RFB) R35/R36 and gain resistors (RG) R7/R8.
Stage 1 Filtering
A differential, first-order RC filter can be implemented at Stage 1's input to limit bandwidth and reduce noise. The cutoff frequency (f3dB) is determined by 1 / (2πRFCF). Changes involve selecting RF resistors (R3/R4) and CF capacitors (C67/C79). Capacitors C7/C8 across feedback networks can also be used for additional filtering.
Stage 1 Alternative Input Signal Sources
Differential Signal Source: The default configuration uses a fully differential signal source with 0V common mode at the SMA inputs. A 6V p-p differential signal results in a full-scale ADC measurement (-3V to +3V). The AD4080's common-mode requirement (1.5V ± 50mV) does not apply to the board input, as the ADA4945-1 sets the output common mode.
Single-Ended Input Source: A single-ended AC signal can be applied to one input (e.g., INP) with the other grounded. A 6V p-p amplitude results in a full-scale ADC measurement (-3V to +3V). The U1 amplifier buffering the other input (IN_N) can be optionally disabled and bypassed by removing R3/R9, populating R5 with 0Ω, and closing Switch 1 (S1-1) to power down U1.
Stage 2 Alternative Amplifiers
Stage 2 defaults to the ADA4945-1. Alternative amplifiers like the ADA4940-1 (lower power, potentially degraded performance) or ADA4932-1 (critical distortion performance, higher power) can be used. These require removing the ADA4945-1 and populating the alternative amplifier into the U3 footprint, with potential pin connection changes.
Common-Mode CMO Output Buffering
By default, the AD4080's CMO output is unbuffered. To connect it to the ADA4945-1's VOCM pin, R30 should be populated with 0Ω. Buffering the CMO output using an ADA4807-2 requires specific solder link (RJ8, RJ9) and resistor (R86) modifications.
Voltage Reference
The default reference is LTC6655-3 (U6). To use LT6657-3 (U7), remove R133 and populate R127 and R66 with 0Ω. For ADR4530B (U8), remove R133, R127, R66 and populate R131 and R132 with 0Ω, then solder U8 to its footprint.
Table 1: 3V Reference Comparison: Compares LT6657, LTC6655, and ADR4530B based on accuracy, temperature coefficient, noise, load, regulation, supply, shutdown, protection, current limit, thermal protection, shunt mode, supply current, and operating temperature.
Power Supply Rails
Internal AD4080 LDO Regulators for the 1.1V Rails
By default, the AD4080's 1.1V rails (VDD11, IOVDD) are supplied by on-board LDOs (U18, U19). To use the AD4080's internal LDOs, disconnect the external supplies by removing jumpers JP1, JP3, JP6, and connect the 2V rail to the VDDLDO pin using jumpers JP2, JP4, JP5.
Off-Board Powering of Individual Power Rails
On-board power rails can be externally supplied for evaluating different power solutions or measuring supply currents. Ensure the external source provides adequate voltage and current to prevent damage.
Link Configuration Options
The EVAL-AD4080ARDZ uses solder links, jumpers, and switches for configuration. Tables 2-7 summarize their functions and default settings.
Table 3: Solder Link Settings: Analog Front End: Details solder link settings (RJ3-RJ6) for analog front-end configurations, including signal connections and comments for swapping amplifiers.
Table 4: Solder Link Settings: External Reference Selection: Describes solder link RJ7 for selecting between on-board and external voltage references.
Table 5: Solder Link Settings: Common-Mode Buffering: Details solder links RJ8 and RJ9 for selecting the common-mode output buffering path.
Table 6: Solder Link Settings: Digital Interface: Explains solder links RJ12, RJ13, RJ14 for configuring the direction of SPI level translators.
Table 7: Jumper Settings: Internal LDOs and Enable Signals Control: Outlines jumper settings (JP1-JP6) for controlling internal LDO regulators and supply rail connections.
Analog Front End (AFE) Considerations
Modifying the AFE of the EVAL-AD4080ARDZ requires careful consideration of trade-offs for specific applications.
Input Signal Filtering
Limiting input bandwidth to the signal's region of interest reduces noise. This can be achieved via RC filters, DNI capacitors in feedback networks, or increasing feedback capacitors. Filter resistor values can impact overall SNR. The AD4080's internal digital filters (Sinc1 to Sinc5) can complement the AFE filter.
Power vs. Bandwidth vs. Noise
Achieving lower noise, distortion, and higher precision often requires more power in the AFE. Power-constrained applications must carefully select amplifiers.
Gain
Gain placement is critical for maximizing SNR. It may be more beneficial to add gain in a preceding low-noise amplifier stage rather than in the FDA, as FDA noise gain can significantly impact overall SNR.
ADC Driver Stage
Refer to the "Easy Drive Analog Inputs" section in the AD4080 data sheet for details.
Notes
[ESD Sensitive Device] ESD (electrostatic discharge) sensitive device. Handle with proper precautions to avoid performance degradation or loss of functionality.
Legal Terms and Conditions: By using this evaluation board, you agree to the terms and conditions outlined, which govern its use for evaluation purposes only. Analog Devices, Inc. disclaims all warranties and limits liability.
Mixed-signal and digital signal processing ICs | Analog Devices
