Analog Devices AD7386-4/AD7387-4/AD7388-4

Single-Ended Input, Quad, Simultaneous Sampling, 16-Bit/14-Bit/12-Bit, SAR ADC

FEATURES

16-bit, 14-bit, and 12-bit ADC family
Quad simultaneous sampling
Single-ended analog inputs
High throughput rate: 4 MSPS
SNR (typical): 84.7 dB (AD7386-4) at VREF = 3.3 V; 82.4 dB (AD7387-4) at VREF = 3.3 V; 73.7 dB (AD7388-4); 92 dB with OSR = 8, VREF = 3.3 V (AD7386-4)
On-chip oversampling function
2-bit resolution boost
Out of range indicator (ALERT)
INL (typical): ±4 LSB (AD7386-4); ±1 LSB (AD7387-4); ±0.2 LSB (AD7388-4)
High-speed serial interface
Temperature range: -40°C to +125°C
2.5 V internal reference at 10 ppm/°C (maximum)
24-lead LFCSP

APPLICATIONS

Motor control position feedback
Motor control current sense
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
Traveling wave fault detection
In-phase and quadrature demodulation

PRODUCT HIGHLIGHTS

Quad simultaneous sampling and conversion.
Pin-compatible product family.
High throughput rate, 4 MSPS at 16-bit, 14-bit, and 12-bit.
Space-saving, 24-lead LFCSP.
Integrated oversampling block to increase dynamic range, reduce noise, and reduce SCLK speed requirements.
Differential analog inputs with wide common-mode range.
Small sampling capacitor reduces amplifier drive burden.

FUNCTIONAL BLOCK DIAGRAM

The functional block diagram illustrates the AD7386-4/AD7387-4/AD7388-4 as a quad SAR ADC system. It includes analog inputs (AINA, AINB, AINC, AIND), oversampling blocks, an interface and control logic unit, and successive approximation register (SAR) ADCs. The diagram shows connections to VCC, VLOGIC, REFCAP, GND, and REFIO. Data outputs (SDOA, SDOB, SDOC, SDOD/ALERT) and control inputs (SCLK, SDI, CS) are also depicted.

GENERAL DESCRIPTION

The AD7386-4/AD7387-4/AD7388-4 are 16-bit, 14-bit, and 12-bit compatible, quad, simultaneous sampling, high-speed, successive approximation register (SAR) analog-to-digital converters (ADCs). They operate from a 3.0 V to 3.3 V power supply and achieve throughput rates up to 4 MSPS. The single-ended analog input accepts voltages from 0 V to VREF and is sampled on the falling edge of the Chip Select (CS) signal. These ADCs feature on-chip oversampling blocks to enhance dynamic range and reduce noise at lower bandwidths, potentially boosting resolution by up to two bits. The reference voltage (VREF) can be 2.5 V to 3.3 V, supplied via the REFIO pin. The conversion process and data acquisition utilize standard control inputs, facilitating easy interfacing with microprocessors or digital signal processors (DSPs). Conversion results can be clocked out via a 4-wire mode for faster throughput or a 1-wire serial mode for slower throughput. The device is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces using a separate logic supply. The AD7386-4/AD7387-4/AD7388-4 are available in a 24-lead lead frame chip scale package (LFCSP) and operate over a temperature range of -40°C to +125°C.

SPECIFICATIONS

The following tables detail the electrical characteristics of the AD7386-4, AD7387-4, and AD7388-4 under typical operating conditions (VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, external VREF = 2.5 V to 3.3 V, fSAMPLE = 4 MSPS, TA = -40°C to +125°C, no oversampling enabled, unless otherwise noted).

AD7386-4 Specifications

Parameter	Test Conditions/Comments	Min	Typ	Max	Unit
RESOLUTION			16		Bits
THROUGHPUT	Conversion Rate (fSAMPLE)
	Single-Channel Pair		4		MSPS
	Alternating Channels	SEQ = 1	2		MSPS
DC ACCURACY	No Missing Codes		16		Bits
	Differential Nonlinearity (DNL) Error		-0.99	±0.6	+1.0	LSB
	Integral Nonlinearity (INL) Error	External reference	-7.0	±4	+7.0	LSB
		Internal reference = 2.5 V		±3		LSB
Gain Error	External reference = 3.3 V	-0.08	±0.005	+0.08	% FS
	Internal reference = 2.5 V		±0.015		% FS
Gain Error Temperature Drift	External reference = 3.3 V	-5	±1	+5	ppm/°C
Gain Error Match			±0.01	+0.08	% FS
Offset Error	External reference = 3.3 V	-1	±0.07	+0.1	mV
	Internal reference		±0.055		mV
Offset Error Temperature Drift	External reference = 3.3 V	-8	±0.5	+8	µV/°C
Offset Error Match		-1.1	±0.2	+1.1	mV
AC ACCURACY	Input frequency (fIN) = 1 kHz
Dynamic Range	VREF = 3.3 V	86			dB
	VREF = 2.5 V	84.5			dB
Oversampled Dynamic Range	OSR = 4×, RES = 1 (decimal)	89			dB
Signal-to-Noise Ratio (SNR)	VREF = 3.3 V, VCC = 3.3 V	80.5	84.7		dB
	VREF = 2.5 V (internal)	81.7			dB
	Rolling average OSR = 8×, RES = 1 (decimal)	92			dB
Spurious-Free Dynamic Range (SFDR)	fIN = 100 kHz	83.5			dB
Total Harmonic Distortion (THD)		-103			dB
	fIN = 100 kHz	-100			dB
Signal-to-Noise-and-Distortion (SINAD) Ratio	VREF = 3.3 V, VCC = 3.3 V	80	84.5		dB
	VREF = 2.5 V (internal)	81.3			dB
Channel to Channel Isolation		-120			dB
Channel to Channel Memory		-95			dB
POWER SUPPLIES	IVCC
	Normal Mode (Operational)	39	45		mA
Power Dissipation	PTOTAL		165	191		mW
	PVCC Normal Mode (Operational)	141	162		mW

1 These specifications include full temperature range variation, but they do not include the error contribution from the external reference.

AD7387-4 Specifications

Parameter	Test Conditions/Comments	Min	Typ	Max	Unit
RESOLUTION			14		Bits
THROUGHPUT	Conversion Rate (fSAMPLE)
	Single-Channel Pair		4		MSPS
	Alternating Channels	SEQ = 1	2		MSPS
DC ACCURACY	No Missing Codes		14		Bits
	DNL Error		-0.99	+0.4	+1	LSB
	INL Error	External reference	-1.8	+1.0	+1.8	LSB
		Internal reference = 2.5 V		±0.75		LSB
Gain Error	External reference	-0.08	±0.005	+0.08	% FS
	Internal reference		±0.015		% FS
Gain Error Temperature Drift	External reference = 3.3 V	-5	±0.3	+5	ppm/°C
Gain Error Match		±0.01	+0.08	% FS
Offset Error	External reference = 3.3 V	-1	±0.1	+1	mV
	Internal reference = 2.5 V		±0.055		mV
Offset Error Temperature Drift	External reference = 3.3 V	-8	+1	+8	µV/°C
Offset Error Match		±0.2	+1.1	mV
AC ACCURACY	Input frequency (fIN) = 1 kHz
Dynamic Range	VREF = 3.3 V	84			dB
	VREF =2.5 V (internal)	83			dB
Oversampled Dynamic Range	OSR = 4×, RES = 1 (decimal)	87.2			dB
SNR	VREF = 3.3 V, VCC = 3.3 V	80	82.4		dB
	VREF = 2.5 V (internal)	80.4			dB
	Rolling average OSR = 8×, RES = 1 (decimal)	90			dB
SFDR	fIN = 100 kHz	81			dB
THD		-102			dB
	fIN = 100 kHz	-100			dB
SINAD Ratio	VREF = 3.3 V, VCC = 3.3 V	79.8	82.3		dB
	VREF = 2.5 V (internal)	79.2			dB
Channel to Channel Isolation		-120			dB
Channel to Channel Memory		-95			dB
POWER SUPPLIES	IVCC
	Normal Mode (Operational)	39	45		mA
Power Dissipation	PTOTAL	165	191		mW
	PVCC Normal Mode (Operational)	141	162		mW

1 These specifications include full temperature range variation, but they do not include the error contribution from the external reference.

AD7388-4 Specifications

Parameter	Test Conditions/Comments	Min	Typ	Max	Unit
RESOLUTION			12		Bits
THROUGHPUT	Conversion Rate (fSAMPLE)
	Single-Channel Pair		4		MSPS
	Alternating Channels	SEQ = 1	2		MSPS
DC ACCURACY	No Missing Codes		12		Bits
	DNL Error		-0.5	±0.25	+0.5	LSB
	INL Error	External reference = 3.3 V	-0.75	±0.2	+0.75	LSB
Gain Error		-0.08	±0.007	+0.08	% FS
Gain Error Temperature Drift	External reference = 3.3 V	-6.5	±1	+6.5	ppm/°C
Gain Error Match		±0.018	+0.1	% FS
Offset Error		-2	±0.3	+2	mV
Offset Error Temperature Drift	External reference = 3.3 V	-12	±1	+12	µV/°C
Offset Error Match		-2	±0.35	+2	mV
AC ACCURACY	Input frequency (fIN) = 1 kHz
Dynamic Range	VREF = 3.3 V, VCC = 3.3 V	74			dB
	VREF = 2.5 V (internal)		73.7		dB
Oversampled Dynamic Range	OSR = 4×, RES = 1 (decimal)	76.6			dB
SNR	VREF = 3.3 V	73	73.7		dB
	VREF = 2.5 V (internal)	73.3			dB
	Rolling average OSR = 8×, RES = 1 (decimal)	80			dB
SFDR	fIN = 100 kHz	73			dB
THD		-100			dB
	fIN = 100 kHz	-98			dB
SINAD Ratio	VREF = 3.3 V, VCC = 3.3 V	73	73.7		dB
	VREF = 2.5 V (internal)	71.8	73.1		dB
Channel to Channel Isolation		-120			dB
Channel to Channel Memory		-95			dB
POWER SUPPLIES	IVCC
	Normal Mode (Operational)	39	45		mA
Power Dissipation	PTOTAL	165	191		mW
	PVCC Normal Mode (Operational)	141	162		mW

1 These specifications include full temperature range variation, but they do not include the error contribution from the external reference.

All Devices Specifications

Parameter	Test Conditions/Comments	Min	Typ	Max	Unit
ANALOG INPUT	Voltage Range		0	+VREF	V
	DC Leakage Current	Track mode	0.1	1	µA
	Input Capacitance	Hold mode	18		pF
			5		pF
SAMPLING DYNAMICS	Input Bandwidth	At -0.1 dB	6		MHz
		At -3 dB	24		MHz
	Aperture Delay		2		ns
	Aperture Delay Match		310		ps
	Aperture Jitter		20		ps

Parameter	Test Conditions/Comments	Min	Typ	Max	Unit
REFERENCE INPUT	VREF Input Voltage Range	External reference	2.49	3.4	V
	VREF Input Current	External reference	0.9	1.2	mA
	VREF Output Voltage	At 25°C	2.495	2.5	2.505	V
	VREF Temperature Coefficient			2	10	ppm/°C
	VREF Regulation	Line	-40		ppm/V
		Load	-34		ppm/mA
	VREF Noise		7		µVrms
DIGITAL INPUTS (SCLK, SDI, CS)	Logic Levels
	Input Voltage Low (VIL)	VLOGIC < 2.3 V		0.45		V
		VLOGIC ≥ 2.3 V		0.7		V
	Input Voltage High (VIH)	VLOGIC < 2.3 V	VLOGIC - 0.45 V		V
		VLOGIC ≥ 2.3 V	0.8 × VLOGIC		V
	Input Current Low (IIL)		-1	+1	µA
	Input Current High (IIH)		-1	+1	µA
DIGITAL OUTPUTS (SDOA, SDOB, SDOC, SDOD/ALERT)	Output Coding	Straight binary			Bits
	Output Voltage Low (VOL)	Current sink (ISINK) = 300 µA	0.4		V
	Output Voltage High (VOH)	Current source (ISOURCE) = -300 µA	VLOGIC - 0.3		V
	Floating State Leakage Current		±1		µA
	Floating State Output Capacitance		10		pF
POWER SUPPLIES	VCC	External reference = 3.3 V	3.0	3.3	3.6	V
	VLOGIC		3.3		3.6	V
	VCC Supply Current (IVCC)		1.65		3.6	V
	Normal Mode (Static)		2.6	3.3		mA
	Shutdown Mode		98	200	µA
VLOGIC Current (IVLOGIC)	Normal Mode (Static)	Analog inputs at positive full scale	146	400	nA
	Normal Mode (Operational)		6.6	8		mA
	Shutdown Mode		47	400	nA
Power Dissipation	VCC Power (PVCC)
	Normal Mode (Static)		9.3	11.5	mW
	Shutdown Mode		375	720	µW
	VLOGIC Power (PVLOGIC)
	Normal Mode (Static)	Analog inputs at positive full scale	0.53	1.5	µW
	Normal Mode (Operational)		24	29	mW
	Shutdown Mode		0.17	1.5	µW

TIMING SPECIFICATIONS

Timing specifications are provided for various operations, including time between conversions, SCLK parameters, CS pulse width, interface quiet time, data setup and hold times, conversion time, acquire time, reset times, power-up times, and alert timing. These parameters are crucial for correct interface operation and are detailed in Table 5.

Parameter	Min	Typ	Max	Unit	Description
tCYC	250			ns	Time between conversions
	500			ns	Alternating conversion channels
tSCLKED	0.5			ns	CS falling edge to first serial clock (SCLK) falling edge
tSCLK	12.5			ns	SCLK period
tSCLKH	5.5			ns	SCLK high time
tSCLKL	5.5			ns	SCLK low time
tCSH	20			ns	CS pulse width
tQUIET	20			ns	Interface quiet time prior to conversion
tSDOEN	5.58			ns	CS low to SDOA, SDOB, SDOC, and SDOD enabled (VLOGIC > 2.25 V)
	8			ns	(1.65 V < VLOGIC < 2.25 V)
tSDOH	3			ns	SCLK rising edge to SDOA, SDOB, SDOC, and SDOD hold time
tSDOS	6			ns	SCLK rising edge to SDOA, SDOB, SDOC, and SDOD setup time (VLOGIC > 2.25 V)
	8			ns	(1.65 V < VLOGIC < 2.25 V)
tSDOT	8			ns	CS rising edge to SDOA, SDOB, SDOC, and SDOD high impedance
tSDIS	4			ns	SDI setup time prior to SCLK falling edge
tSDIH	4			ns	SDI hold time after SCLK falling edge
tSCLKCS	0			ns	SCLK rising edge to CS rising edge
tCONVERT		190		ns	Conversion time
tACQUIRE		110		ns	Acquire time
tRESET	250			ns	Valid time to start conversion after soft reset
	800			ns	Valid time to start conversion after hard reset
tPOWERUP			5	ms	Supply active to conversion
		11		ms	First conversion allowed
		5	ms	Settled to within 1% with internal reference
		5	ms	Settled to within 1% with external reference
tREGWRITE		5	ms	Supply active to register read write access allowed
tSTARTUP		10	µs	Exiting shutdown mode to conversion
tCONVERT0	6	8	10	ns	Conversion time for first sample in oversampling (OS) normal mode
tCONVERTx				ns	Conversion time for xth sample in OS normal mode, 4 MSPS, 16-bit devices
			tCONVERT0 + (320 × (x – 1))		ns	For AD7386-4, at 3 MSPS
			tCONVERT0 + (250 × (x – 1))		ns	For AD7387-4 and AD7388-4, at 4 MSPS
tALERTS		220		ns	Time from CS to ALERT indication
tALERTC		10		ns	Time from CS to ALERT clear
tALERTS_NOS		20		ns	Time from internal conversion with exceeded threshold to ALERT indication

Timing Diagrams: The datasheet includes diagrams illustrating Serial Interface Timing, Internal Conversion Acquire Timing, Power-Up Time to Conversion, Power-Up Time to Register Read Write Access, Shutdown Mode to Normal Mode Timing, Conversion Timing During OS Normal Mode, and ALERT Timing. These diagrams visually represent the sequence and timing of control signals (CS, SCLK, SDI, SDOx) and data transfers.

ABSOLUTE MAXIMUM RATINGS

Exceeding these ratings may cause permanent damage. These are stress ratings only, and functional operation under these conditions is not implied. Extended operation beyond specified conditions may affect reliability.

Parameter	Rating
VCC to GND	-0.3 V to +4 V
VLOGIC to GND	-0.3 V to +4 V
Analog Input Voltage to GND	-0.3 V to VREF + 0.3 V, or VCC + 0.3 V
Digital Input Voltage to GND	-0.3 V to VLOGIC + 0.3 V
Digital Output Voltage to GND	-0.3 V to VLOGIC + 0.3 V
REFIO Input to GND	-0.3 V to VCC + 0.3 V
Input Current to any Pin Except Supplies	±10 mA
Temperature
Operating Temperature Range	-40°C to +125°C
Storage Temperature Range	-65°C to +150°C
Maximum Junction Temperature (TJMAX)	150°C
Pb-Free Soldering Reflow Temperature	260°C

THERMAL RESISTANCE

Thermal performance is dependent on PCB design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction-to-ambient thermal resistance, and θJC is the junction-to-case thermal resistance.

Package Type	θJA	θJC	Unit
CP-24-25¹	48.4	0.431	°C/W

1 Test Condition 1: thermal impedance simulated values are based on JEDEC 2S2P thermal test board with four thermal vias.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charge device model (FICDM) per ANSI/ESDA/JEDEC JS-002.

ESD Ratings for AD7386-4, AD7387-4, and AD7388-4

ESD Model	Withstand Threshold (V)	Class
HBM	±4000	3A
FICDM	±1250	C3

ESD CAUTION: ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

The AD7386-4/AD7387-4/AD7388-4 are available in a 24-lead LFCSP package. Figure 9 shows the pin configuration.

Figure 9. Pin Configuration: A top view diagram of the 24-lead LFCSP package showing pin numbering from 1 to 24. Key pins include GND, VLOGIC, VCC, REGCAP, REFCAP, REFIO, CS, SCLK, SDI, SDOA, SDOB, SDOC, SDOD/ALERT, and an exposed pad (EPAD).

Pin No.	Mnemonic	Description
1, 5, 14, 16	GND	Ground Reference Point. These pins are the ground reference points for all circuitry on the device.
2	VLOGIC	Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 µF capacitor.
3	REGCAP	Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a 1 µF capacitor. The voltage at this pin is 1.9 V typical.
4	VCC	Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple this pin to GND using a 1 µF capacitor.
6, 7	AIND1, AIND0	Analog Inputs of ADC D. These are 2-channel multiplexed single-ended inputs.
8, 9	AINC1, AINC0	Analog Inputs of ADC C. These are 2-channel multiplexed single-ended inputs.
10, 11	AINB1, AINB0	Analog Inputs of ADC B. These are 2-channel multiplexed single-ended inputs.
12, 13	AINA1, AINA0	Analog Inputs of ADC A. These are 2-channel multiplexed single-ended inputs.
15	REFCAP	Decoupling Capacitor Pin for Band Gap Reference. Decouple REFCAP to GND with a 0.1 µF capacitor. The voltage at REFCAP is 2.5 V typical.
17	REFIO	Reference Input and Output. The on-chip reference of 2.5 V is available as an output on REFIO for external use if the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V can be connected to the REFIO pin as input. Set the REFSEL bit in the Configuration 1 register to 1 when using the external reference and apply the REFSEL bit after VCC and VLOGIC. Decoupling is required on REFIO for both the internal and external reference options. Apply a 1 µF capacitor from REFIO to GND.
18	CS	Chip Select Input. Active low logic input. This input provides the dual function of initiating conversions on the AD7386-4/AD7387-4/AD7388-4 and framing the serial data transfer.
19	SDOA	Serial Data Output A. This pin functions as a serial data output pin to access the conversion results and register contents.
20	SDOB	Serial Data Output B. This pin functions as a serial data output pin to access the conversion results.
21	SDI	Serial Data Input. This input provides the data written to the on-chip control registers.
22	SCLK	Serial Clock Input. This SCLK input is for data transfers to and from the ADC.
23	SDOC	Serial Data Output C. This pin functions as a serial data output pin to access the conversion results and register contents.
24	SDOD/ALERT	Serial Data Output D/Alert Indication Output. This pin can operate as a serial data output pin or alert indication output. SDOD. This pin functions as a serial data output pin to access the conversion results. ALERT. This pin operates as an alert pin going low to indicate that a conversion result has exceeded a configured threshold.
	EPAD	Exposed Pad. For correct operation of the device, the exposed pad must be connected to GND.

TYPICAL PERFORMANCE CHARACTERISTICS

Typical performance characteristics are presented for TA = 25°C, VCC = VLOGIC = 3.3 V, throughput rate = 4 MSPS, external VREF = 2.5 V and 3.3 V, external SCLK = 80 MHz, unless otherwise noted.

Frequency Domain Analysis (FFT)

Figure 10: FFT, AD7386-4 Internal VREF = 2.5 V: Shows FFT plot with input frequency 1kHz, SNR 83.22dB, THD -101.8dB.
Figure 11: FFT, AD7387-4 Internal VREF = 2.5 V: Shows FFT plot with input frequency 1kHz, SNR 81.5dB, THD -101.41dB.
Figure 12: FFT, AD7388-4 Internal VREF = 2.5 V: Shows FFT plot with input frequency 1kHz, SNR 73.5dB, THD -94.96dB.
Figure 13: FFT, AD7386-4 External VREF = 3.3 V: Shows FFT plot with input frequency 1kHz, SNR 84.57dB, THD -97.7dB.
Figure 14: FFT, AD7386-4 Oversampling, External VREF = 3.3 V: Shows FFT plot with input frequency 1kHz (-0.5dB), SNR 91.99dB, THD -93.96dB, with rolling average OSR = 8, RES = 1.

DC Accuracy

Figure 15: INL vs. Code: Plot showing Integral Nonlinearity (LSB) versus Code, illustrating typical INL behavior.
Figure 16: DNL vs. Code: Plot showing Differential Nonlinearity (LSB) versus Code, illustrating typical DNL behavior.
Figure 17: DC Histogram: Histogram showing the distribution of codes for a specific input voltage, indicating linearity and noise.

Signal-to-Noise Ratio (SNR) vs. Input Frequency

Figure 18: SNR vs. Input Frequency (AD7386-4): Plots SNR (dB) against input frequency (Hz) for both internal and external VREF conditions.
Figure 19: SNR vs. Input Frequency (AD7387-4): Plots SNR (dB) against input frequency (Hz) for both internal and external VREF conditions.
Figure 20: SNR vs. Input Frequency (AD7388-4): Plots SNR (dB) against input frequency (Hz) for both internal and external VREF conditions.

Total Harmonic Distortion (THD) vs. Input Frequency

Figure 21: THD vs. Input Frequency (AD7386-4): Plots THD (dB) against input frequency (Hz) for both internal and external VREF conditions.

Signal-to-Noise-and-Distortion (SINAD) vs. Input Frequency

Figure 22: SINAD vs. Input Frequency (AD7386-4): Plots SINAD (dB) against input frequency (Hz) for both internal and external VREF conditions.
Figure 23: SINAD vs. Input Frequency (AD7387-4): Plots SINAD (dB) against input frequency (Hz) for both internal and external VREF conditions.
Figure 24: SINAD vs. Input Frequency (AD7388-4): Plots SINAD (dB) against input frequency (Hz) for both internal and external VREF conditions.

Performance vs. Temperature

Figure 25: SNR vs. Temperature: Plots SNR (dB) against temperature (°C) for different channels and VREF conditions.
Figure 26: THD vs. Temperature: Plots THD (dB) against temperature (°C) for different channels and VREF conditions.

Power Characteristics

Figure 27: Dynamic Current vs. Throughput Rate: Shows the relationship between dynamic current consumption (mA) and throughput rate (MSPS).
Figure 28: Shutdown Current vs. Temperature: Plots shutdown current (µA) against temperature (°C).
Figure 29: PSRR vs. Ripple Frequency: Shows Power Supply Rejection Ratio (dB) against ripple frequency (MHz).

Oversampling Performance

Figure 30: Normal Averaging Oversampling: Plots SNR (dB) against oversampling ratio (2N) for normal averaging mode.
Figure 31: Rolling Average Oversampling: Plots SNR (dB) against oversampling ratio (2N) for rolling average mode.

TERMINOLOGY

Definitions for key performance metrics are provided:

Differential Nonlinearity (DNL): Maximum deviation from ideal 1 LSB code transition.
Integral Nonlinearity (INL): Deviation of each code from a straight line drawn from negative to positive full scale.
Gain Error: Deviation in the difference between the actual and ideal levels of the first and last code transitions.
Gain Error Temperature Drift: Change in gain error per degree Celsius change in temperature.
Gain Error Match: Difference in gain error between input channels.
Offset Error: Deviation of the first transition from analog ground.
Offset Error Temperature Drift: Change in offset error per degree Celsius change in temperature.
Offset Error Match: Difference in offset error between input channels.
Signal-to-Noise Ratio (SNR): Ratio of the RMS signal to the RMS sum of other spectral components (excluding harmonics and DC).
Spurious-Free Dynamic Range (SFDR): Difference between the RMS amplitude of the input signal and the peak spurious signal.
Total Harmonic Distortion (THD): Ratio of the RMS sum of the first five harmonic components to the RMS value of a full-scale input signal.
Signal-to-Noise-and-Distortion (SINAD): Ratio of the RMS signal to the RMS sum of all other spectral components (including harmonics, excluding DC).
Power Supply Rejection Ratio (PSRR): Measure of how power supply variations affect the full-scale transition point.
Aperture Delay: Time between CS falling edge and input signal being held for conversion.
Aperture Jitter: Variation in aperture delay.

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7386-4/AD7387-4/AD7388-4 are quad, single-ended SAR ADCs operating from a 3.0 V to 3.6 V supply at up to 4 MSPS. They feature four ADCs and a serial interface with four data output pins, housed in a 24-lead LFCSP for space saving. Data is accessed via the serial interface, which supports two, four, or one serial output. An on-chip 2.5 V internal reference is available, or an external reference (2.5 V to 3.3 V) can be used. The analog input range is 0 V to VREF. The devices include on-chip oversampling for performance enhancement and power-down options for power saving. Configuration is managed via the serial interface.

CONVERTER OPERATION

Each ADC uses two capacitive DACs. In the acquisition phase (Figure 32), SW2 is closed, SW1 is in Position A, and the sampling capacitor (CS) acquires the input signal. During the conversion phase (Figure 33), SW2 opens, SW1 moves to Position B, and the comparator becomes unbalanced. The control logic and charge redistribution DACs adjust charge on the sampling capacitor arrays to rebalance the comparator, completing the conversion. The output code is generated by the control logic.

ANALOG INPUT STRUCTURE

The analog input structure (Figure 34) includes diodes for ESD protection on the AINx pins. Input signals should not exceed supply rails by more than 300 mV to prevent forward-biasing these diodes. Capacitors C1 (approx. 3 pF) are attributed to pin capacitance, R1 resistors (approx. 200 Ω) are switch resistances, and C2 capacitors (approx. 15 pF) are the ADC sampling capacitors.

ADC TRANSFER FUNCTION

The AD7386-4/AD7387-4/AD7388-4 use a 2.5 V to 3.3 V reference. Analog inputs (AINx0 and AINx1) are converted to digital outputs. The conversion result is MSB first, straight binary. The LSB size is (VREF)/2N, where N is the ADC resolution. Table 10 provides LSB size values for different resolutions and reference voltages. Figure 35 illustrates the ideal ADC transfer function.

Resolution (Bits)	2.5 V Reference (µV)	3.3 V Reference (µV)
12	610.3	805.7
14	152.6	201.4
16	38.1	50.4
18	9.5	12.6

Figure 35. ADC Ideal Transfer Function: Depicts the quantized analog input voltage mapping to digital codes, showing step-wise transitions.

Figure 36. Typical Application Circuit: Shows a circuit diagram with the ADC connected to a digital host (microprocessor/FPGA) via serial interface pins (CS, SCLK, SDI, SDOx). It includes decoupling capacitors for VCC, VLOGIC, REGCAP, REFCAP, and REFIO, as well as analog input filtering (RC network) and a reference voltage source.

APPLICATIONS INFORMATION

Typical Application Circuit

Figure 36 illustrates a typical application circuit. Proper decoupling of power supply (VCC, VLOGIC), REGCAP, REFCAP, and REFIO pins with 1 µF capacitors is recommended. The exposed pad must be connected to ground. An RC filter (e.g., 33 Ω and 330 pF) should be placed on analog inputs for optimal performance. Table 11 lists recommended companion devices for signal chain components, including ADC drivers, external references, and LDO regulators.

Power Supply

The AD7386-4/AD7387-4/AD7388-4 can be powered by a 5 V supply, potentially derived from ADP7104. The ADC driver might require a ±5 V source from ADP5600 and a −2.5 V regulator (ADP7182). Independent power supplies for VCC and VLOGIC are recommended, using low quiescent current LDO regulators like ADP166. Decoupling capacitors are crucial for VCC and VLOGIC pins. An internal 1.9 V LDO is also present.

Power-Up

Power supply sequencing is flexible; VCC and VLOGIC can be applied in any order. The external reference must be applied after VCC and VLOGIC. Analog and digital signals should be applied after the external reference. A power-up time (tPOWERUP) is required for the ADC conversion results to stabilize. Issuing a software reset after power-up is recommended, though conversion results may not meet datasheet specifications immediately.

MODES OF OPERATION

CHANNEL SELECTION

Channel pairs (AINA0/AINB0, etc.) are selected via the CH bit in the Configuration 1 register. CH=0 converts AINx0 channels, while CH=1 converts AINx1 channels. Changing channels requires additional settling time, reducing maximum throughput to 2 MSPS.

SEQUENCER

The SEQ bit in Configuration 1 enables an on-chip sequencer to automatically cycle through AINx0 and AINx1 channels. When SEQ=1, the device alternates between AINx0 and AINx1, restarting the cycle after AINx1. The CH bit is ignored in sequencer mode. Maximum throughput when changing channels via the sequencer is 2 MSPS.

Figure 37. Manual Channel Selection Setup: Illustrates the serial interface timing for manual channel selection.

Figure 38. Channel Sequencer Setup: Illustrates the serial interface timing for the sequencer mode.

OVERSAMPLING

Oversampling improves ADC accuracy by averaging multiple samples to reduce quantization and thermal noise. The AD7386-4/AD7387-4/AD7388-4 support two modes: normal averaging and rolling average, configured via OS_MODE and OSR bits in Configuration 1.

Normal Averaging Oversampling

Suitable for applications requiring slower data rates and higher SNR/dynamic range. Multiple samples are averaged and the result is output. Sample data is cleared after processing. OS_MODE=0 and a valid OSR value configure this mode. Table 12 details OS ratios and resulting SNR.

Figure 39. Normal Averaging Oversampling Operation: Shows the timing diagram for normal averaging oversampling.

Rolling Average Oversampling

Used for higher output data rates with improved SNR/dynamic range. Samples are averaged using a FIFO buffer, allowing throughput to remain constant. OS_MODE=1 and a valid OSR value configure this mode. Table 13 details OS ratios and resulting SNR. The FIFO length is 8 samples.

Figure 40. Rolling Average OS Mode Configuration: Shows the timing diagram for rolling average oversampling.

RESOLUTION BOOST

The default resolutions are 16-bit (AD7386-4), 14-bit (AD7387-4), and 12-bit (AD7388-4). When oversampling is enabled, the RES bit in Configuration 1 can boost resolution by two bits (e.g., 18-bit for AD7386-4). This requires additional SCLK cycles for data propagation.

Figure 41. Resolution Boost: Illustrates the data output with increased resolution.

ALERT

The alert functionality provides an out-of-range indicator. An alert triggers if a conversion result exceeds the alert high threshold or falls below the alert low threshold. These thresholds are common to all ADCs. The ALERT_EN bit, along with SDO configuration and threshold register settings, enables the alert output on the SDOD/ALERT pin. Alert status bits are updated at the end of conversion and are cleared by reading the alert indication register or a falling CS edge.

POWER MODES

Two power modes are available: Normal Mode (PMODE=0) and Shutdown Mode (PMODE=1), configured via the Configuration 1 register. Normal mode provides the fastest throughput. Shutdown mode reduces power consumption by powering down analog circuitry, with the serial interface remaining active for exiting shutdown.

Figure 42. Shutdown Mode Operation: Shows timing for entering and exiting shutdown mode.

INTERNAL AND EXTERNAL REFERENCE

A 2.5 V internal reference is available. An external reference (2.5 V to 3.3 V) can be supplied via the REFIO pin. The REFSEL bit in Configuration 1 selects between internal (REFSEL=0) and external (REFSEL=1) references. A 1 µF capacitor on REFIO is recommended.

SOFTWARE RESET

Two reset modes exist: soft reset (0x3C) and hard reset (0xFF), configured in the Configuration 2 register. A soft reset refreshes blocks and clears alert status. A hard reset resets all registers and blocks, including the oscillator. A hard reset after power-up is recommended.

Figure 43. Software Reset Operation: Shows timing for software reset.

DIAGNOSTIC SELF TEST

A diagnostic self test runs after power-on or hard reset to verify configuration loading. The result is indicated by the SETUP_F bit in the alert indication register. A failure requires a software hard reset.

INTERFACE

The device uses a serial interface comprising CS, SCLK, SDOA, SDOB, SDOC, SDOD, and SDI pins. The CS signal initiates conversions and frames data transfers. SCLK synchronizes data in/out. The interface supports 2-wire, 1-wire, and 4-wire modes for outputting conversion results, with 4-wire offering the highest throughput. Cyclic Redundancy Check (CRC) can be enabled for enhanced interface robustness.

READING CONVERSION RESULTS

A high-to-low transition on CS initiates a conversion for all four ADCs. Conversion results are available with a one-cycle latency. Data is shifted out via SDO pins synchronized by SCLK. The number of SCLK cycles depends on the interface mode, resolution boost, and CRC settings (Table 14).

Table 14. Number of SCLK Cycles (n) Required for Reading Conversion Results: Details SCLK cycles for 4-wire, 2-wire, and 1-wire interfaces, with and without resolution boost and CRC.

Serial Interface Modes

Serial 4-Wire Mode: SDO bits set to 0b10 in Configuration 2. Outputs data on SDOA, SDOB, SDOC, SDOD.
Serial 2-Wire Mode: SDO bits set to 0b00. Outputs data on SDOA (ADC A, C) and SDOB (ADC B, D).
Serial 1-Wire Mode: For slower throughput or normal averaging OS. Outputs data on SDOA only (ADC A, B, C, D). Requires additional SCLK cycles.

LOW LATENCY READBACK

For lower throughput applications, latency can be reduced by using a second CS pulse after conversion completion to read back results (Figure 48).

Figure 45. Read Conversion Results, 4-Wire Mode: Timing diagram for 4-wire data output.

Figure 46. Read Conversion Results, 2-Wire Mode: Timing diagram for 2-wire data output.

Figure 47. Reading Conversion Results, 1-Wire Mode: Timing diagram for 1-wire data output.

Figure 48. Low Throughput Low Latency: Timing diagram showing reduced latency readback.

READING FROM DEVICE REGISTERS

Registers can be read via the serial interface using a register read command (D15=0) followed by an optional NOP command. Bits[D14:D12] specify the register address.

WRITING TO DEVICE REGISTERS

Registers can be written to via the serial interface. Write access length depends on CRC settings (16 bits if CRC disabled, 24 bits if enabled). Bits[D14:D12] specify the register address, and Bits[D11:D0] contain the data.

CRC

CRC checksum modes improve interface robustness. CRC_W and CRC_R bits in Configuration 1 control CRC functionality for writes and reads, respectively. CRC calculation uses the polynomial x⁸ + x² + x + 1. A CRC error is indicated by the CRCW_F bit.

Figure 49. Register Read: Timing diagram for reading registers.

Figure 50. Register Write: Timing diagram for writing to registers.

Figure 51. CRC Operation: Illustrates various CRC operations for different interface modes and data widths.

REGISTERS

The AD7386-4/AD7387-4/AD7388-4 feature user-programmable on-chip registers for device configuration. Table 16 provides an overview of available registers (read/write or read-only).

Addressing Registers

Serial register transfers use 16 SCLK cycles. The first four MSBs (REGADDR and WR bits) determine the register address and read/write operation. Table 17 shows the addressing format, and Table 18 describes the bits.

Configuration 1 Register

This register controls various device functions, including addressing, channel selection (CH), sequencer (SEQ), oversampling mode (OS_MODE), oversampling ratio (OSR), CRC functionality (CRC_W, CRC_R), alert enable (ALERT_EN), resolution (RES), reference select (REFSEL), and power mode (PMODE). Table 19 details each bit.

Configuration 2 Register

This register contains addressing bits, reserved bits, SDO output configuration (SDO), and reset control (RESET). Table 20 details each bit.

Alert Indication Register

This read-only register indicates the status of alerts (AL_D_HIGH, AL_D_LOW, etc.) for each channel, CRC errors (CRCW_F), and load errors (SETUP_F). Table 21 lists the bit descriptions.

Alert Low Threshold Register

Used to set the lower threshold for alert generation. Bits[11:0] define the ALERT_LOW value.

Alert High Threshold Register

Used to set the upper threshold for alert generation. Bits[11:0] define the ALERT_HIGH value.

RELATED DEVICES

Table 24 lists related devices from Analog Devices, categorized by number of channels, input type, and resolution.

No. of Channels	Input Type	16 Bits	14 Bits	12 Bits
4	Differential	AD7380-4	AD7381-4	AD7389-4
	Pseudo-differential	AD7383-4	AD7384-4
2	Differential	AD7380	AD7381	AD7388
		AD4680	AD4684
		AD4681	AD4685
	Pseudo-differential	AD7383	AD7384
		AD4682
		AD4683
	Single-ended	AD7386	AD7387	AD7388

OUTLINE DIMENSIONS

Figure 52 shows the dimensions for the 24-lead Lead Frame Chip Scale Package (LFCSP), measuring 4 mm x 4 mm body with a 0.55 mm package height (CP-24-25). Dimensions are shown in millimeters.

Figure 52. 24-Lead Lead Frame Chip Scale Package [LFCSP]: Diagram detailing the physical dimensions of the LFCSP package, including body size, height, and pin indicator placement. It notes compliance with JEDEC standards MO-248-UGGD and refers to the Pin Configuration section for exposed pad connection.

ORDERING GUIDE

The following table lists available models, their temperature ranges, package descriptions, packing quantities, package options, and marking codes.

Model¹	Temperature Range	Package Description	Packing Quantity	Package Option	Marking Code
AD7386-4BCPZ	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE		CP-24-25
AD7386-4BCPZ-RL	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE	Reel, 5000	CP-24-25
AD7386-4BCPZ-RL7	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE	Reel, 1000	CP-24-25
AD7387-4BCPZ	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE		CP-24-25	CA7
AD7387-4BCPZ-RL	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE	Reel, 5000	CP-24-25	CA7
AD7387-4BCPZ-RL7	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE	Reel, 1000	CP-24-25	CA7
AD7388-4BCPZ	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE		CP-24-25
AD7388-4BCPZ-RL	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE	Reel, 5000	CP-24-25
AD7388-4BCPZ-RL7	-40°C to +125°C	LFCSP:LEADFRM CHIP SCALE	Reel, 1000	CP-24-25

¹ Z = RoHS Compliant Part.

EVALUATION BOARDS

Model¹	Description
EVAL-AD7386-4FMCZ	Evaluation Board

¹ Z = RoHS Compliant Part.

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FEATURES

APPLICATIONS

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

SPECIFICATIONS

AD7386-4 Specifications

AD7387-4 Specifications

AD7388-4 Specifications

All Devices Specifications

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ELECTROSTATIC DISCHARGE (ESD) RATINGS

ESD Ratings for AD7386-4, AD7387-4, and AD7388-4

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

Frequency Domain Analysis (FFT)

DC Accuracy

Signal-to-Noise Ratio (SNR) vs. Input Frequency

Total Harmonic Distortion (THD) vs. Input Frequency

Signal-to-Noise-and-Distortion (SINAD) vs. Input Frequency

Performance vs. Temperature

Power Characteristics

Oversampling Performance

TERMINOLOGY

THEORY OF OPERATION

CIRCUIT INFORMATION

CONVERTER OPERATION

ANALOG INPUT STRUCTURE

ADC TRANSFER FUNCTION

APPLICATIONS INFORMATION

Typical Application Circuit

Power Supply

Power-Up

MODES OF OPERATION

CHANNEL SELECTION

SEQUENCER

OVERSAMPLING

Normal Averaging Oversampling

Rolling Average Oversampling

RESOLUTION BOOST

ALERT

POWER MODES

INTERNAL AND EXTERNAL REFERENCE

SOFTWARE RESET

DIAGNOSTIC SELF TEST

INTERFACE

READING CONVERSION RESULTS

Serial Interface Modes

LOW LATENCY READBACK

READING FROM DEVICE REGISTERS

WRITING TO DEVICE REGISTERS

CRC

REGISTERS

Addressing Registers

Configuration 1 Register

Configuration 2 Register

Alert Indication Register

Alert Low Threshold Register

Alert High Threshold Register

RELATED DEVICES

OUTLINE DIMENSIONS

ORDERING GUIDE

EVALUATION BOARDS

References

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