Evaluation Board for AD9278/AD9279

Features

• Full featured evaluation board for the AD9278/AD9279
• SPI and alternate clock options
• Internal and external reference options
• VisualAnalog and SPI Controller software interfaces

Equipment Needed

• Analog signal source and antialiasing filter
• 2 switching power supplies (6.0 V, 2.5 A) CUI EPS060250UH-PHP-SZ, provided
• Linear bench top dc voltage source (0 V to 1.6 V), not required for CW Doppler mode
• PC running Windows 98 (2nd edition), Windows 2000, Windows ME, or Windows XP
• USB 2.0 port, recommended (USB 1.1 compatible)
• AD9278/AD9279 evaluation board
• HSC-ADC-EVALCZ FPGA-based data capture kit
• For CW Doppler mode: spectrum analyzer

Documents Needed

• AD9278/AD9279 data sheet

Software Needed

• VisualAnalog
• SPI Controller

General Description

This document describes the AD9278/AD9279 evaluation board, which provides all of the support circuitry required to operate the AD9278/AD9279 in their various modes and configurations. The application software used to interface with the devices is also described.

The AD9278/AD9279 data sheets, available at www.analog.com, provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at http://www.analog.com/fifo. For any questions, send an email to highspeed.converters@analog.com.

Typical Measurement Setup

Figure 1 shows a typical measurement setup with the AD9278/AD9279 evaluation board and the HSC-ADC-EVALCZ Data Capture Board.

Evaluation Board Hardware

The AD9278/AD9279 evaluation board provides all of the support circuitry required to operate the AD9278/AD9279 in its various modes and configurations. Figure 2 shows the typical bench characterization setup used to evaluate the ac performance of the AD9278/AD9279. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance (see the AD9278 or AD9279 data sheet).

See the Evaluation Board Software Quick Start Procedures section to get started and Figure 20 to Figure 31 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level.

Power Supplies

This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P601. Once on the PC board, the 6 V supply is fused and conditioned before connecting to low dropout linear regulators that supply the proper bias to each of the various sections on the board.

When operating the evaluation board in a nondefault condition, L602, L603, L604, L605, L606, L607, L608 and L609 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P602, P603, and P606 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for 1.8 V AVDD and 1.8 V DRVDD; however, it is recommended that separate supplies be used for both analog and digital domains. An additional supply is also required to supply 3.0 V to the DUT, 3.0 V AVDD2. This should also have a 1 A current capability. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or 3.3VAVDD, should have a 1 A current capability. To bias the CW I/Q Demodulator section and differential gain drive circuitry, separate +5 V and –5 V supplies are required at P606. These should each have 1 A current capability.

Input Signals

When connecting the clock, 4LO and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644B signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude (refer to the specifications in the AD9278 or AD9279 data sheet). The evaluation board is set up to be clocked from the crystal oscillator, OSC501.

If a different or external clock source is desired, follow the instructions in the Clock section. Typically, most Analog Devices, Inc. evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band band-pass filter with 50 Ω terminations. Analog Devices uses TTE and K&L Microwave, Inc., band-pass filters. The filter should be connected directly to the evaluation board.

Output Signals

The default TGC setup uses the FIFO5 high speed, dual-channel FIFO data capture board (HSC-ADC-EVALCZ). Two of the eight TGC channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO.

The default I/Q demodulator setup uses two ADA4841 amplifiers for I-V conversion and two ADA4841 amplifiers for gain and filtering. The analog outputs can be evaluated using an oscilloscope or spectrum analyzer.

Default Operation and Jumper Selection Settings

This section explains the default and optional settings or modes allowed on the AD9278/AD9279 Rev. B evaluation board.

Power Circuitry

Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P601.

Analog Input Front-End Circuit

The evaluation board is set up for single ended Kelvin connection analog input with an optimum 50 Ω impedance match of 18 MHz of bandwidth. For a different bandwidth response, use the "manual tune” feature and antialiasing filter settings.

VREF

VREF is set to 1.0 V. This causes the ADC to operate with the internal reference in the 2.0 V p-p full-scale range. A separate external reference option using the ADR130 is also included on the evaluation board. Populate R320 with a 0 Ω resistor and remove C301. Note that ADC full-scale ranges less than 2.0 V p-p are not supported by the AD9278/AD9279.

RBIAS

RBIAS has a default setting of 10 kΩ (R304) to ground and is used to set the ADC core bias current. However, note that using other than a 10 kΩ, 1% resistor for RBIAS may degrade the performance of the device, depending on the resistor chosen.

Clock Circuitry

The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T501) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.

The evaluation board is already set up to be clocked from the crystal oscillator, OSC501. This oscillator is a low phase noise oscillator from Valpey Fisher (VFAC3HL-40MHz). If a different clock source is desired, remove R503, set Jumper J501 to disable the oscillator from running, and connect the external clock source to the SMA connector, J503.

A differential LVPECL clock driver can also be used to clock the ADC input using the AD9516 (U501). Populate C528 and C529 with 0.1 µF capacitors and remove C506 and C507 to disconnect the default clock path inputs. In addition, populate C511 and C512 with a 0.1 µF capacitor. The AD9516 has many SPI-selectable options that are set to a default mode of operation. Consult the AD9516 data sheet for more information about these and other options.

PDWN

To enable the power-down feature, short P301 (Pin 3 to Pin 4) to the on position (AVDD) on the PDWN pin.

STBY

To enable the standby feature, short P301 (Pin 1 to Pin 2) to the on position (AVDD) on the STBY pin.

GAIN+, GAIN-

To change the VGA attenuation, drive the GAIN+ pin from 0 V to 1.6 V on J401 using a linear supply, and use a single-ended method to change the VGA gain from 0 dB to 45 dB. U411 is available for users who wish to drive the gain pins (GAIN±) differentially. Install R426, R435, and R436 and remove C456, C457, and R440 to connect the amplifier correctly. In differential mode, a linear supply from -0.8 V to +0.8 V on J401 is required to change the VGA gain from 0 dB to 42 dB. If an external source is not available, remove R425, and install R438 to use the on-board resistive divider (R439) for gain adjustment in either the single-ended case.

CWI/Q+, CWI/Q-

To view the CWI+/CWI- and/or CWQ+/CWQ- outputs, configure the AD9278/AD9279 to be in CW Mode and enable each channel via the SPI Controller program. Apply a 13dBm, 20MHz reference clock on J303. Each enabled channel will be summed and will be available through J402/J403.

DOUTx+, DOUTx-

If an alternative data capture method to the setup described in Figure 2 is used, optional receiver terminations, R604 to R613, can be installed next to the high-speed backplane connector, P604.

Evaluation Board Software Quick Start Procedures

This section provides quick start procedures for using the AD9278/AD9279, either on the evaluation board or at the system level design. Both the default and optional settings are described.

Configuring the Board for TGC Mode

Before using the software for testing, configure the evaluation board as follows:

1. Connect the boards to each other as shown in Figure 1 and Figure 2.
2. Connect one 6 V, 2.5 A switching power supply (such as the CUI Inc. EPS060250UH-PHP-SZ supplied) to the AD9278/AD9279 board.
3. Connect one 6 V, 2.5 A switching power supply (such as the CUI EPS060250UH-PHP-SZ supplied) to the HSC-ADC-EVALCZ board.
4. Connect the HSC-ADC-EVALCZ board to the PC with a USB cable. Connect to J6.
5. On the AFE evaluation board, place jumpers on all five pin pairs of J404 to connect the SPI bus.
6. On the AFE evaluation board, ensure that J501 (OSC_EN) is jumpered to the OFF setting to use the on-board 40 MHz Valpey Fisher VFAC3 oscillator.
7. On the AFE evaluation board, use a clean signal generator with low phase noise to provide an input signal to the desired channel. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results, use a narrow-band band-pass filter with 50 Ω terminations and an appropriate center frequency (Analog Devices uses TTE, Allen Avionics, and K&L band-pass filters).

Using the Software for Testing

Set Up the ADC Data Capture Block

After configuring the board, set up the ADC data capture block using the following steps:

1. Open VisualAnalog™ on a PC. AD9278 or AD9279 should be listed in the status bar of the New Canvas window. Select the template that corresponds to the type of testing to be performed (see Figure 3).
2. After the template is selected, a dialog box opens, asking if the default configuration can be used to program the FPGA (see Figure 4). Click Yes, and the window closes. If a different program is desired, follow Step 3.
3. To view different channels or change features to settings other than the default settings, click the Expand Display button. This is located on the bottom right corner of the window, as shown in Figure 5. This process is described in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual. After you are finished, click the Collapse Display button (see Figure 6).

Set up the SPI Controller

Once the ADC data capture board setup has been completed, set up the SPI Controller:

1. Open the SPI Controller software by going to the Start menu or double-clicking the SPI Controller software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded. If necessary, choose Cfg Open from the File menu and select the appropriate one. Note that the CHIP ID(1) field should be filled to indicate whether the correct SPI Controller configuration file is loaded or not (see Figure 8).
2. Click the New DUT button in SPI Controller.
3. In the Global tab of SPI Controller, find the CHIP GRADE(2) box. Use the drop-down select box to select the correct speed mode, if necessary. See the AD9278 or AD9279 data sheet, the AN-878 Application Note, and the AN-877 Application Note for reference.
4. In the ADCBase 0 tab of SPI Controller, find the HIGHPASS(2B) box. Click the Manual Tune button to calibrate the antialiasing filter. See the AD9278 or AD9279 data sheet, the AN-878 Application Note, and the AN-877 Application Note for reference.
5. In the ADC A tab of SPI Controller, find the OFFSET(10) box. Use the drop-down select box labeled Offset Adj to perform an offset correction to the LNA if the LNA power setting BIAS_CURR_A(12) has been set low. The default value is 32.
6. Click the Run button in the VisualAnalog toolbar.

Adjust the Amplitude of the Input Signal

Next, adjust the amplitude of the input signal for each channel as follows:

1. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) If the gain pin voltage is too low, it is not possible to reach full scale without distortion. Use a higher gain setting or a lower input level to avoid distortion. This also depends on the PGA gain setting, which can be 30 dB, 27 dB, 24 dB (default), or 21 dB. See Figure 14 and Figure 15.
2. Repeat this procedure for the other seven channels.
3. Click the disk icon within the Graph window to save the performance plot. See Figure 16.

Using the Integrated I/Q Demodulator (CW Doppler Mode)

To examine the spectrum of the CW Doppler integrated I/Q demodulator output, use the following procedure:

1. Complete the steps in the Configuring the Board and Using the Software for Testing sections to ensure that the board is set up correctly.
2. Optionally, remove the voltage source from the gain pin, J401. It does not affect the CW Doppler output.
3. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the spectrum analyzer to J402 and/or J403.
4. Connect a 20 MHz signal source to J303, 4LO input. Use a clean signal generator with low phase noise to provide an input clock signal. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator.
5. Connect a 5.0123 MHz signal source to ChA, J101. Use a clean signal generator with low phase noise to provide an input signal to the desired channel. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results, use a narrow-band band-pass filter with 50 Ω terminations and an appropriate center frequency (Analog Devices uses TTE, Allen Avionics, and K&L band-pass filters).
6. In the ADCBase 0 tab of SPI Controller, find the MODES(8) box. Select the CW Mode option.
7. In the ADC x tab of SPI Controller, where x is the channel to which an analog input is applied, find the CW_IQ_DEMOD_PH(2D) box. Select the CW Channel Enable check box to enable the channel. Then select the phase rotation of the channel using the I/Q Demodulator Phase pull-down menu.
8. Examine the spectrum analyzer for the CW Doppler output (see Figure 19 for an example).

Evaluation Board Schematics and Artwork

• Figure 20. Evaluation Board Schematic, DUT Analog Input Circuits
• Figure 21. Evaluation Board Schematic, DUT Analog Input Circuits (Continued)
• Figure 22. Evaluation Board Schematic, DUT, VREF, and Decoupling
• Figure 23. Evaluation Board Schematic, I/Q Demodulator, SPI, and Gain Drive Circuitry
• Figure 24. Evaluation Board Schematic, Clock Circuitry
• Figure 25. Evaluation Board Schematic, Power Supply, Digital Output Interface
• Figure 26. Evaluation Board Layout, Top Side
• Figure 27. Evaluation Board Layout, Ground Plane (Layer 2)
• Figure 28. Evaluation Board Layout, Power Plane (Layer 3)
• Figure 29. Evaluation Board Layout, Power Plane (Layer 4)
• Figure 30. Evaluation Board Layout, Ground Plane (Layer 5)
• Figure 31. Evaluation Board Layout, Bottom Side

Ordering Information

Bill of Materials

Table 1 lists the components for the evaluation board.

ESD Caution

ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.