intel 4G Turbo-V FPGA IP
E pili ana i ka 4G Turbo-V Intel® FPGA IP
Hoʻomaikaʻi maʻamau nā code channel forward-error correction (FEC) i ka pono o ka ikehu o nā ʻōnaehana kamaʻilio uea. He kūpono nā code Turbo no nā kamaʻilio paʻa lima 3G a me 4G (e laʻa, ma UMTS a me LTE) a me nā kamaʻilio ukali. Hiki iā ʻoe ke hoʻohana i nā code Turbo i nā noi ʻē aʻe e koi ana i ka hoʻoili ʻana i ka ʻike hilinaʻi ma luna o ka bandwidth- a i ʻole ka latency-constrained loulou kamaʻilio ma ke alo o ka walaʻau hōʻino ʻikepili. Aia ka 4G Turbo-V Intel® FPGA IP i kahi downlink a uplink accelerator no vRAN a me ka Turbo Intel FPGA IP. Hoʻohui ka mea hoʻolele downlink i ka redundancy i ka ʻikepili ma ke ʻano o ka ʻike parity.
ʻIke pili
- Turbo Intel FPGA IP alakaʻi hoʻohana
- 3GPP TS 36.212 mana 15.2.1 Hoʻokuʻu 15
4G Turbo-V Intel FPGA IP hiʻona
Aia ka downlink accelerator:
- Pākuʻi code block cyclic redundancy code (CRC).
- Mea hoʻopili Turbo
- ʻO ka hoʻohālikelike ʻano turbo me:
- Pākuʻi hoʻopili
- ʻOhi bit
- Mea koho bit
- Bit pruner
Aia ka uplink accelerator:
- Hoʻopau hoʻokaʻawale subblock
- ʻO Turbo decoder me ka nānā CRC
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
Kākoʻo ʻohana 4G Turbo-V Intel FPGA IP Device
Hāʻawi ʻo Intel i kēia mau pae kākoʻo no ka Intel FPGA IP:
- Kākoʻo mua—loaʻa ka IP no ka hoʻohālikelike a me ka hoʻohui ʻana no kēia ʻohana hāmeʻa. FPGA papahana file ʻAʻole loaʻa ke kākoʻo (.pof) no ka polokalamu Quartus Prime Pro Stratix 10 Edition Beta a no laila ʻaʻole hiki ke hōʻoia ʻia ka pani ʻana o ka manawa IP. Hoʻokomo ʻia nā kumu hoʻohālike manawa i nā kuhi ʻenekinia mua o nā lohi e pili ana i ka ʻike ma hope o ka hoʻonohonoho mua ʻana. Hiki ke hoʻololi ʻia nā hiʻohiʻona manawa no ka hoʻomaikaʻi ʻana o ka hoʻāʻo silika i ka pilina ma waena o ke silikona maoli a me nā kumu hoʻohālike manawa. Hiki iā ʻoe ke hoʻohana i kēia IP core no ka hoʻolālā ʻōnaehana a me nā haʻawina hoʻohana waiwai, simulation, pinout, system latency assessments, basic time assessments (pipeline budgeting), a me I/O transfer strategy (data-alanui width, burst depth, I/O standard tradeoffs). ).
- Kākoʻo mua—hōʻoia ʻo Intel i ka IP core me nā hiʻohiʻona manawa mua no kēia ʻohana hāmeʻa. Hoʻokō ka IP core i nā pono hana āpau, akā ke hele nei paha ka nānā ʻana i ka manawa no ka ʻohana hāmeʻa. Hiki iā ʻoe ke hoʻohana iā ia i nā hoʻolālā hana me ka akahele.
- Kākoʻo hope—hōʻoia ʻo Intel i ka IP me nā hiʻohiʻona manawa hope no kēia ʻohana hāmeʻa. Hoʻokō ka IP i nā pono hana a me ka manawa no ka ʻohana hāmeʻa. Hiki iā ʻoe ke hoʻohana iā ia i nā hoʻolālā hana.
Kākoʻo ʻohana 4G Turbo-V IP Device
| ʻOhana Mea Hana | Kākoʻo |
| Intel Agilex™ | Holomua |
| Intel Arria® 10 | hope loa |
| ʻO Intel Stratix® 10 | Holomua |
| Nā ʻohana mea hana ʻē aʻe | ʻAʻohe kākoʻo |
Hoʻokuʻu i ka ʻike no ka 4G Turbo-V Intel FPGA IP
Kūlike nā mana Intel FPGA IP me nā mana polokalamu polokalamu Intel Quartus® Prime Design Suite a hiki i ka v19.1. E hoʻomaka ana ma Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP he polokalamu hoʻololi hou. Hiki ke loli ka helu Intel FPGA IP (XYZ) me kēlā me kēia polokalamu polokalamu Intel Quartus Prime. He hoʻololi i:
- Hōʻike ʻo X i kahi hoʻoponopono nui o ka IP. Inā hōʻano hou ʻoe i ka polokalamu Intel Quartus Prime, pono ʻoe e hana hou i ka IP.
- Hōʻike ʻo Y i ka IP me nā hiʻohiʻona hou. E hana hou i kāu IP e hoʻokomo i kēia mau hiʻohiʻona hou.
- Hōʻike ʻo Z i ka IP me nā loli liʻiliʻi. E hana hou i kāu IP e hoʻokomo i kēia mau hoʻololi.
4G Turbo-V IP Hoʻokuʻu ʻIke
| 'ikamu | wehewehe |
| Manao | 1.0.0 |
| Lā Hoʻokuʻu | ʻApelila 2020 |
4G Turbo-V hana a me ka hoʻohana waiwai
Ua hoʻokumu ʻo Intel i ka hoʻohana ʻana a me ka hana ʻana ma o ka hoʻohui ʻana i nā hoʻolālā me Intel Quartus Prime software v19.1. E hoʻohana wale i kēia mau hualoaʻa pili no ka helu mua ʻana i nā kumuwaiwai FPGA (e laʻa i nā modula loiloi adaptive (ALM)) e pono ai kahi papahana. ʻO 300 MHz ka alapine i manaʻo ʻia.
ʻO ka hoʻohana ʻana i nā kumuwaiwai ʻo Downlink Accelerator a me ke alapine kiʻekiʻe loa no nā polokalamu Intel Arria 10
| Module | fMAX (Mhz) | ALM | ALUTs | Kakau inoa | Hoʻomanaʻo (Bits) | Nā poloka RAM (M20K) | Nā poloka DSP |
| Mea hoʻokē ʻai iho | 325.63 | 9,373 | 13,485 | 14,095 | 297,472 | 68 | 8 |
| Hoʻopili CRC | 325.63 | 39 | 68 | 114 | 0 | 0 | 0 |
| Mea hoʻopili Turbo | 325.63 | 1,664 | 2,282 | 1154 | 16,384 | 16 | 0 |
| Mea hoʻohālikelike | 325.63 | 7,389 | 10,747 | 12,289 | 274,432 | 47 | 8 |
| Pākuʻi hoʻopili | 325.63 | 2,779 | 3,753 | 5,559 | 52,416 | 27 | 0 |
| ʻOhi bit | 325.63 | 825 | 1,393 | 2,611 | 118,464 | 13 | 4 |
| ʻO ka mea koho bit a me ka pruner | 325.63 | 3,784 | 5,601 | 4,119 | 103,552 | 7 | 4 |
Hoʻohana ʻia ʻo Uplink Accelerator Resource a me ka Frequency Maximum no Intel Arria 10 Devices
| Module | fMAX (Mhz) | ALM | Kakau inoa | Hoʻomanaʻo (Bits) | Nā poloka RAM (M20K) | Nā poloka DSP |
| Uplink accelerator | 314.76 | 29480 | 30,280 | 868,608 | 71 | 0 |
| Hoʻopau hoʻokaʻawale subblock | 314.76 | 253 | 830 | 402,304 | 27 | 0 |
| ʻO Turbo decoder | 314.76 | 29,044 | 29,242 | 466,304 | 44 | 0 |
Hoʻolālā me ka 4G Turbo-V Intel FPGA IP
4G Turbo-V IP Papa kuhikuhi
Pono ʻoe e hoʻokomo lima i ka IP mai ka mea hoʻonoho IP.
Hoʻonohonoho Papa kuhikuhi
Ke hana nei i kahi 4G Turbo-V IP
Hiki iā ʻoe ke hana i kahi downlink a i ʻole uplink accelerator. No ka uplink accelerator, e hoʻololi i ka dl me ka ul ma ka papa kuhikuhi a i ʻole file inoa.
- E wehe i ka polokalamu Intel Quartus Prime Pro.
- E koho File ➤ Wizard Papahana Hou.
- Kaomi aku.
- E hoʻokomo i ka inoa Project dl_fec_wrapper_top a komo i kahi o ka papahana.
- E koho iā Arria 10.
- Kaomi Hoʻopau.
- E wehe i ka dl_fec_wrapper_top.qpf file loaʻa ma ka papa kuhikuhi papahana Hōʻike ʻia ka wizard papahana.
- Ma ka ʻaoʻao Platform Designer:
- E hana i ka dl_fec_wrapper_top.ip file me ka hoʻohana ʻana i ka hardware tcl file.
- Kaomi i ka Generate HDL e hana i ka hoʻolālā files.
- Ma ka Generate tab, kaomi Generate Test bench system.
- Kaomi Add All e hoʻohui i ka synthesis files i ka papahana. ʻO ka files aia ma src\ip\dl_fec_wrapper_top\dl_fec_wrapper_10\synth.
- E hoʻonoho i ka dl_fec_wrapper_top.v file ma ke ʻano he hui kiʻekiʻe.
- Kaomi i ka Start Compilation e hōʻuluʻulu i kēia papahana.
Hoʻohālike i kahi 4G Turbo-V IP
ʻO kēia hana no ka hoʻohālikelike ʻana i kahi accelerator downlink. No ka hoʻohālike i ka uplink accelerator e hoʻololi i ka dl me ka ul i kēlā me kēia papa kuhikuhi a i ʻole file inoa.
- E wehe i ka ModelSim 10.6d FPGA Edition simulator.
- E hoʻololi i ka papa kuhikuhi i src\ip\dl_fec_wrapper_top_tb \dl_fec_wrapper_top_tb\sim\mentor
- E hoʻololi i ka QUARTUS_INSTALL_DIR i kāu papa kuhikuhi Intel Quartus Prime ma ka msim_setup.tcl file, aia ma ka papa kuhikuhi \sim\mentor
- E hoʻokomo i ke kauoha do load_sim.tcl kauoha ma ka puka makani transcript. Hoʻopuka kēia kauoha i ka waihona files a hōʻuluʻulu a hoʻohālikelike i ke kumu files i ka msim_setup.tcl file. Aia nā vectors hoʻāʻo filename_update.sv ma ka papa kuhikuhi \sim.
ʻO ka fileinoa hou File Hoʻolālā
- Vektor ho'āʻo kūpono files aia ma sim\mentor\test_vectors
- Loaʻa i ka Log.txt ka hopena o kēlā me kēia ʻeke hoʻāʻo.
- No ka mea hoʻokele downlink, encoder_pass_fileAia ka .txt i ka hōʻike pass o kēlā me kēia papa kuhikuhi o nā ʻeke hoʻāʻo a me ka encoder_fileAia ka _error.txt i ka hōʻike hemahema o kēlā me kēia papa kuhikuhi o nā ʻeke hoʻāʻo.
- No ka uplink accelerator, Error_fileAia ka .txt i ka hōʻike hāʻule o kēlā me kēia papa kuhikuhi o nā ʻeke hoʻāʻo.
4G Turbo-V Intel FPGA IP wehewehe hana
Loaʻa ka 4G Turbo-V Intel FPGA IP i kahi downlink accelerator a me kahi uplink accelerator.
- 4G Turbo-V Architecture ma ka ʻaoʻao 9
- Nā hōʻailona 4G Turbo-V a me nā Interfaces ma ka ʻaoʻao 11
- 4G Turbo-V Nā Kiʻikuhi manawa ma ka ʻaoʻao 15
- 4G Turbo-V Latency a me Throughput ma ka ʻaoʻao 18
Hoʻolālā 4G Turbo-V
Loaʻa ka 4G Turbo-V Intel FPGA IP i kahi downlink accelerator a me kahi uplink accelerator.
4G Downlink Accelerator
Aia ka 4G Turbo downlink accelerator me ka poloka code block CRC attachment block a me ka Turbo encoder (Intel Turbo FPGA IP) a me ka helu matcher. He 8-bit ka laulā ka ʻikepili hoʻokomo a he 24-bit ka laulā ka ʻikepili puka. ʻO ka mea hoʻohālikelike helu he ʻekolu mau subblock interleavers, kahi mea koho iki, a me kahi mea hōʻiliʻili iki.
Hoʻokomo ka 4G downlink accelerator i kahi hoʻopili code block CRC me ka 8-bit parallel CRC computation algorithm. ʻO ka mea hoʻokomo i ka poloka hoʻopili CRC he 8-bit ākea. Ma ke ʻano maʻamau, ʻo ka helu o nā mea hoʻokomo i ka poloka CRC he k-24, kahi k ka nui o ka poloka ma muli o ka helu helu nui. Hoʻopili ʻia ke kaʻina CRC hou o 24 bits i ka poloka code incoming code o ka ʻikepili i ka poloka hoʻopili CRC a laila hele i ka Turbo encoder. Ma ka CRC bypass mode, ʻo ka helu o nā mea hoʻokomo he k ka nui o ka 8-bit ākea i hāʻawi ʻia i ka poloka encoder Turbo.
Hoʻohana ka Turbo encoder i kahi code convolutional concatenated like. Hoʻopili ka mea hoʻopili hoʻopili i ke kaʻina ʻike a hoʻopaʻa inoa ʻē aʻe ka hoʻopili ʻana i kahi mana interleaved o ke kaʻina ʻike. ʻO ka Turbo encoder ʻelua 8-state constituent convolutional encoders a me hoʻokahi Turbo code internal interleaver. No ka 'ike hou aku e pili ana i ka Turbo encoder, e nānā i ka Turbo IP Core Guide User. Hoʻohālikelike ka mea hoʻohālikelike i ka helu o nā bits i ka pahu lawe i ka helu o nā bits i hoʻouna ʻia e ka IP ma ia ʻāpana. ʻO ka hoʻokomo a me ka puka o ka mea hoʻohālikelike helu he 24 mau bits. Hōʻike ka IP i ka hoʻohālikelike ʻana i ka helu no nā ala kaʻa kaʻa ʻo Turbo no kēlā me kēia poloka code. Aia ka mea hoʻohālikelike helu: subblock interleaver, bit collector a me bit selector. Hoʻonohonoho ka mea hoʻolele downlink i ka subblock interleaved no kēlā me kēia kahawai puka mai Turbo coding. Aia nā kahawai i kahi kahawai bit memo, 1st parity bit stream a me 2nd parity bit stream. ʻO ka hoʻokomo a me ka puka o ka subblock interleaved he 24 bits ākea. Hoʻohui ka ʻohi bit i nā kahawai e hele mai ana mai ka subblock interleaver. Aia kēia poloka i nā pale e mālama ai:
- Hoʻopili ʻia nā memo a me ka hoʻopiha piha ʻana i nā bits mai ka subblock.
- Hoʻopili ka subblock i nā ʻāpana parity a me ko lākou mau ʻāpana hoʻopihapiha.
ʻOhi Bit
4G Channel Uplink Accelerator
Aia ka 4G Turbo uplink accelerator me kahi subblock deinterleaver a me ka turbo decoder (Intel Turbo FPGA IP).
ʻO ka deinterleaver he ʻekolu poloka i ʻokoʻa nā poloka mua ʻelua a ʻokoʻa ke kolu o ka poloka.
ʻO ka latency o ka hōʻailona mākaukau he 0.
Deinterleaver
Inā hoʻohuli ʻoe i ke ʻano bypass no ka subblock deinterleaver, heluhelu ka IP i ka ʻikepili i kona kākau ʻana i ka ʻikepili i loko o nā poloka hoʻomanaʻo ma nā wahi e pili ana. Heluhelu ka IP i ka ʻikepili i ka wā e kākau ai i ka ʻikepili me ka ʻole o ka interleaving. ʻO ka helu o nā ʻikepili hoʻokomo i loko o ka subblock deinterleaver ʻo ia ʻo K_π ma ke ʻano bypass a ʻo ka lōʻihi o ka ʻikepili i hoʻopuka ʻia ʻo ka nui k (k ʻo ia ka nui o ka poloka code e pili ana i ka waiwai cb_size_index). ʻO ka latency o ka ʻikepili puka o ka subblock deinterleaver e pili ana i ka nui o ka poloka hoʻokomo K_π. Heluhelu ka IP i ka ʻikepili ma hope o kou kākau ʻana i ka nui o ka poloka K_π code o ka ʻikepili hoʻokomo. No laila ʻo ka latency o ka hoʻopuka pū kekahi me ka manawa kākau. ʻO K_π+17 ka lōʻihi o ka ʻikepili puka interleaver subblock. Hoʻohālikelike ka Turbo decoder i ke kaʻina i hoʻouna ʻia, ma muli o ka samples i loaa mai. No ka wehewehe kikoʻī, e nānā i ka Turbo Core IP User Guide. ʻO ka wehe ʻana i nā code hoʻoponopono hewa he hoʻohālikelike i nā probabilities no nā code convolutional like ʻole. Aia ka Turbo decoder i ʻelua mau decoders soft-in soft-out (SISO), e hana maʻamau. ʻO ka puka o ka mua (decoder luna) e hānai i ka lua e hana i kahi hoʻololi hoʻololi Turbo. Hoʻonohonoho hou ʻia nā ʻikepili ma kēia kaʻina hana Interleaver a me deinterleaver.
ʻIke pili
Turbo IP Core alakaʻi hoʻohana
Nā hōʻailona 4G Turbo-V a me nā mea hoʻopili
Hoʻoiho i lalo iho
Nā hōʻailona hōʻailona hōʻemi
| inoa hōʻailona | Kuhikuhi | Bit Laulā | wehewehe |
| clk | Hookomo | 1 | 300 MHz hoʻokomo uaki. ʻO nā hōʻailona kikowaena IP Turbo-V a pau me kēia uaki. |
| reset_n | Hookomo | 1 | Hoʻoponopono hou i ka loina kūloko o ka IP holoʻokoʻa. |
| sink_valid | Hookomo | 1 | Manaʻo ʻia inā kūpono ka ʻikepili ma sink_data. Ke ʻōlelo ʻole ʻia ʻo sink_valid, hoʻopau ka IP i ka hana ʻana a hiki i ka sink_valid i hōʻoia hou ʻia. |
| sink_data | Hookomo | 8 | Lawe maʻamau ka nui o ka ʻike e hoʻoili ʻia. |
| sink_sop | Hookomo | 1 | Hōʻike i ka hoʻomaka ʻana o kahi ʻeke komo |
| sink_eop | Hookomo | 1 | Hōʻike i ka hopena o kahi ʻeke komo mai |
| hoʻomākaukau ʻia | Hoʻopuka | 1 | Hōʻike i ka wā e hiki ai i ka IP ke ʻae i ka ʻikepili |
| Holoi_hewa | Hookomo | 2 | ʻElua-bit mask e hōʻike i nā hewa e pili ana i ka ʻikepili i hoʻoili ʻia i ka pōʻai o kēia manawa. |
| Crc_enable | Hookomo | 1 | Hiki i ka poloka CRC |
| Cb_size_index | Hookomo | 8 | K |
| sink_rm_out_size | Hookomo | 20 | ʻO ka nui o nā poloka puka hoʻohālikelike helu, e like me E. |
| sink_code_blocks | Hookomo | 15 | Ka nui pale paʻakikī no ka poloka code o kēia manawa Ncb |
| sink_rv_idx | Hookomo | 2 | Helu helu hōʻano hou (0,1,2 a i ʻole 3) |
| sink_rm_bypass | Hookomo | 1 | Ho'ā i ke ala kaʻawale i ka mea hoʻohālikelike helu |
| sink_filler_bits | Hookomo | 6 | ʻO ka helu o nā mea hoʻopihapiha e hoʻokomo i ka IP i ka mea hoʻouna i ka wā e hana ai ka IP i ka māhele code block. |
| kumu_pono | Hoʻopuka | 1 | Hōʻike ʻia e ka IP inā loaʻa ka ʻikepili kūpono e hoʻopuka. |
| hoʻomau… | |||
| inoa hōʻailona | Kuhikuhi | Bit Laulā | wehewehe |
| kumu_ʻikepili | Hoʻopuka | 24 | Lawe i ka nui o ka ʻike i hoʻoili ʻia. Loaʻa kēia ʻike ma kahi i hōʻoia ʻia. |
| kumu_sop | Hoʻopuka | 1 | Hōʻike i ka hoʻomaka o kahi ʻeke. |
| kumu_eop | Hoʻopuka | 1 | Hōʻike i ka hopena o kahi ʻeke. |
| mākaukau_kumu | Hookomo | 1 | Loaʻa ka loaʻa ʻana o ka ʻikepili i kahi i hōʻoia ʻia ai ka hōʻailona mākaukau. |
| kumu_hewa | Hoʻopuka | 2 | Hoʻolaha ʻia ka hōʻailona hewa mai Turbo Encoder e hōʻike ana i ka hewa o ka protocol Avalon-ST ma ka ʻaoʻao kumu
• 00: ʻAʻohe hewa • 01: Nalo ka hoʻomaka ʻana o ka ʻeke • 10: Nalo ka hope o ka ʻeke • 11: He 11 ka hopena i manaʻo ʻole ʻia o ka ʻeke. |
| Source_blk_size | Hoʻopuka | 13 | Ka nui o ka poloka helu K |
Uplink Accelerator Interfaces
Nā hōʻailona hōʻailona hōʻailona Uplink
| hōʻailona | Kuhikuhi | Bit Laulā | wehewehe |
| clk | Hookomo | 1 | 300 MHz hoʻokomo uaki. ʻO nā hōʻailona kikowaena IP Turbo-V a pau me kēia uaki. |
| reset_n | Hookomo | 1 | Hoʻoponopono hou i ka hōʻailona uaki hoʻokomo |
| sink_valid | Hookomo | 1 | Pono ka hoʻokomo ʻana o Avalon streaming |
| sink_data | Hookomo | 24 | ʻIkepili hoʻokomo ʻo Avalon |
| sink_sop | Hookomo | 1 | ʻO ka hoʻomaka ʻana o ka hoʻokomo ʻana o Avalon i ka ʻeke |
| sink_eop | Hookomo | 1 | ʻO Avalon streaming hoʻokomo hope o ka ʻeke |
| hoʻomau… | |||
| hōʻailona | Kuhikuhi | Bit Laulā | wehewehe |
| hoʻomākaukau ʻia | Hookomo | 1 | Ua mākaukau ka hoʻokomo ʻana o Avalon |
| conf_valid | Hookomo | 1 | Pono ke ala hoʻonohonoho hoʻokomo |
| cb_size_index | Hookomo | 8 | Papa kuhikuhi helu hoʻololi nui |
| max_iteration | Hookomo | 5 | ʻO ka hoʻonui kiʻekiʻe |
| rm_bypass | Hookomo | 1 | Hoʻā i ke ʻano kaʻalo |
| sel_CRC24A | Hookomo | 1 | Hōʻike i ke ʻano o ka CRC āu e pono ai no ka poloka ʻikepili o kēia manawa:
• 0: CRC24A • 1: CRC24B |
| conf_ready | Hookomo | 1 | Ua mākaukau ke alapili hoʻokomo |
| kumu_pono | Hoʻopuka | 1 | Loaʻa ka puka hoʻoheheʻe Avalon |
| kumu_ʻikepili | Hoʻopuka | 16 | Avalon kahe ana i ka ikepili puka |
| kumu_sop | Hoʻopuka | 1 | ʻO ka hoʻomaka ʻana o ka hoʻomaka ʻana o ka pākeʻe e kahe ana ʻo Avalon |
| kumu_eop | Hoʻopuka | 1 | ʻO ka hopena o ka ʻeke e kahe ana ʻo Avalon |
| kumu_hewa | Hoʻopuka | 2 | Hōʻailona hewa e hōʻike ana i ka uhaki ʻana o Avalon streaming protocol ma ka ʻaoʻao kumu:
• 00: ʻAʻohe hewa • 01: Nalo ka hoʻomaka ʻana o ka ʻeke • 10: Nalo ka hope o ka ʻeke • 11: He 11 ka hopena i manaʻo ʻole ʻia o ka ʻeke. |
| mākaukau_kumu | Hoʻopuka | 1 | Mākaukau ka puka hoʻoheheʻe ʻana o Avalon |
| CRC_type | Hoʻopuka | 1 | Hōʻike i ke ʻano o CRC i hoʻohana ʻia no ka poloka ʻikepili o kēia manawa:
• 0: CRC24A • 1: CRC24B |
| kumu_blk_size | Hoʻopuka | 13 | Hōʻike i ka nui poloka puka |
| CRC_pass | Hoʻopuka | 1 | Hōʻike inā ua holomua ʻo CRC:
• 0: hāʻule • 1: Holo |
| kumu_iter | Hoʻopuka | 5 | Hōʻike i ka helu o ka hapalua iterations a pau ka Turbo decoder i ka hana ʻana i ka poloka ʻikepili o kēia manawa. |
ʻO Avalon Streaming Interfaces ma DSP Intel FPGA IP
ʻO Avalon streaming interfaces e wehewehe i kahi protocol maʻamau, maʻalahi, a me ka modular no ka hoʻoili ʻana i ka ʻikepili mai kahi kumu kumu i kahi interface sink. ʻO ke kikowaena hoʻokomo he Avalon streaming sink a ʻo ka mea hoʻopuka hoʻopuka he kumu streaming Avalon. Kākoʻo ka Avalon streaming interface i nā hoʻoili packet me nā ʻeke i hoʻopili ʻia ma nā kahawai he nui. Hiki i nā hōʻailona hoʻoheheʻe Avalon ke wehewehe i nā kuʻuna streaming kuʻuna e kākoʻo ana i hoʻokahi kahawai o ka ʻikepili me ka ʻike ʻole o nā kahawai a i ʻole nā palena packet. Loaʻa i ia mau kikowaena nā ʻikepili, mākaukau, a me nā hōʻailona kūpono. Hiki i ka Avalon streaming interface ke kākoʻo i nā protocols paʻakikī no ka hoʻoili ʻana a me ka packet me nā packet i hoʻopili ʻia ma nā kahawai he nui. Hoʻopili maoli ka Avalon streaming interface i nā hoʻolālā multichannel, kahi e hiki ai iā ʻoe ke hoʻokō i ka hoʻokō pono a me ka manawa-multiplexed me ka ʻole e hoʻokō i ka loiloi mana paʻakikī. Kākoʻo ʻo Avalon streaming interfaces i ka backpressure, ʻo ia ka mea hoʻokele kahe e hiki ai i kahi poho ke hōʻailona i kahi kumu e hoʻōki i ka hoʻouna ʻana i ka ʻikepili. Hoʻohana maʻamau ka pahu i ka backpressure e hoʻōki i ke kahe ʻana o ka ʻikepili i ka wā i piha ai kāna mau pale FIFO a i ʻole i ka wā e paʻa ai kāna mea hoʻopuka.
ʻIke pili
ʻO Avalon Interface Specifications
4G Turbo-V kiʻi manawa
Hoʻolālā manawa no ke kākau ʻana i ka Logic me Codeblock 40
ʻO ka IP:
- E kau i nā ʻāpana 20 null ma ke kolamu 0 a i ka 19 a kākau i nā ʻikepili mai ke kolamu 20.
- Kākau i nā 44 bits a pau i ka hoʻomanaʻo ma 6 mau pōʻaiapuni.
- Kākau i nā ʻāpana hoʻopau trellis i ke kolamu 28 a 31.
- Hoʻonui ka helu helu no kēlā me kēia lālani.
- Hoʻokumu i ka hōʻailona hiki ke kākau no 8 RAM pākahi i ka manawa.
ʻAʻole kākau ka IP i nā bits filler i loko o ka RAM. Akā, haʻalele ka IP i ka mea paʻa no nā kānana bits i ka RAM a hoʻokomo i nā NULL bits i ka puka i ka wā o ka heluhelu ʻana. Hoʻomaka ka kākau mua mai ke kolamu 20.
Hoʻolālā manawa no ka heluhelu ʻana i ka Logic me Codeblock 40
No kēlā me kēia heluhelu ʻana, ʻike ʻoe i 8 bits i hoʻokahi pōʻaiapuni uaki akā ʻelua wale nō mau bits i kūpono. Kākau ka IP i kēia mau ʻāpana ʻelua i ka papa inoa hoʻololi. Ke hoʻokumu ka IP i 8 mau bits e hoʻouna iā lākou i ke kikowaena puka.
Hoʻolālā manawa no ke kākau ʻana i ka Logic me Codeblock 6144
Mai ke kolamu 0 a hiki i ka 27 nā ʻāpana ʻikepili mai ke kolamu 28. ʻO IP:
- Kākau i nā 6,148 bits a pau i ka hoʻomanaʻo ma 769 mau pōʻaiapuni.
- Kākau i nā ʻāpana hoʻopau trellis i ke kolamu 28 a 31.
- Hoʻonui ka helu helu no kēlā me kēia lālani.
- Hana ʻia ka hōʻailona hiki ke kākau no 8 RAM pākahi i ka manawa.
ʻAʻole kākau ka IP i nā mea hoʻopiha piha i ka RAM. Ma kahi o ka IP haʻalele i ka mea paʻa no nā kānana bits ma luna o ka RAM a hoʻokomo i nā NULL bits i ka hoʻopuka i ka wā heluhelu. Hoʻomaka ka kākau mua mai ke kolamu 28.
Hoʻolālā manawa no ka heluhelu ʻana i ka Logic me Codeblock 6144
Ma ka ʻaoʻao heluhelu, hāʻawi kēlā me kēia heluhelu i 8 mau ʻāpana. I ka heluhelu ʻana i ka lālani 193rd, heluhelu ka IP i 8 bits, akā hoʻokahi wale nō mea kūpono. Hoʻokumu ka IP i ʻewalu mau bits me nā papa inoa hoʻololi a hoʻouna iā lākou ma ka heluhelu ʻana mai ke kolamu aʻe.
Kiʻikuhi manawa hoʻokomo
Kiʻikuhi manawa hoʻopuka
4G Turbo-V Latency a me Throughput
Ana 'ia ka latency ma waena o ka SOP packet mua a i ka SOP packet mua. Ana ʻia ka manawa hana ma waena o ka hoʻokomo ʻana i ka ʻeke SOP mua a i ka hoʻopuka ʻana i ka ʻeke hope EOP.
Mea hoʻokē ʻai iho
ʻO ka throughput ka helu e hiki ai i ka IP ke pā i ka hoʻokomo i loko o ka downlink accelerator i kona mākaukau.
Downlink Accelerator Latency, Wā Hana Hana, a me Throughput
Me ka nui K nui o 6,144 a me ka nui E o 11,522. Ua ana ʻia ka manawa hana no nā poloka code 13. ʻO 300 MHz ka wikiwiki o ka uaki.
| K | E | Latency | Ka manawa hana | Hoʻokomo ma waena | ||
| (pōkole) | (mākou) | (pōkole) | (mākou) | (%) | ||
| 6,144 | 11,552 | 3,550 | 11.8 | 14,439 | 48.13 | 95 |
Ka helu ʻana i ka manawa lohi a me ka hana
- Hōʻike ke kiʻi i ke kaʻina hana e helu i ka latency, ka manawa hana, a me ka throughput.
Ka nui K me ka Latency
Ka nui K me ka Latency
- k=40 a hiki i 1408
Uplink Accelerator Latency and Processing Time
- Me ka helu hoʻonui kiʻekiʻe = 6. He 300 MHz ka wikiwiki o ka uaki.
K E Latency Ka manawa hana (pōkole) (mākou) (pōkole) (mākou) 86 40 316 1.05 318 1.06 34,560 720 2,106 7.02 2,150 7.16 34,560 1,408 3,802 12.67 3,889 12.96 34,560 1,824 4,822 16.07 4,935 16.45 28,788 2,816 7,226 24.08 7,401 24.67 23,742 3,520 8,946 29.82 9,165 30.55 34,560 4,032 10,194 33.98 10,445 34.81 26,794 4,608 11,594 38.64 11,881 39.60 6,480 5,504 13,786 45.95 14,129 47.09 12,248 6,144 15,338 51.12 15,721 52.40
Uplink Accelerator Latency and Processing Time
- Me ka helu hoʻonui kiʻekiʻe = 8
| K | E | Latency | Ka manawa hana | ||
| (pōkole) | (mākou) | (pōkole) | (mākou) | ||
| 86 | 40 | 366 | 1.22 | 368 | 1.22 |
| 34,560 | 720 | 2,290 | 7.63 | 2,334 | 7.78 |
| 34,560 | 1,408 | 4,072 | 13.57 | 4,159 | 13.86 |
| 34,560 | 1,824 | 5,144 | 17.14 | 5,257 | 17.52 |
| 28,788 | 2,816 | 7,672 | 25.57 | 7,847 | 26.15 |
| hoʻomau… | |||||
| 23,742 | 3,520 | 9,480 | 31.6 | 9,699 | 32.33 |
| 34,560 | 4,032 | 10,792 | 35.97 | 11,043 | 36.81 |
| 26,794 | 4,608 | 12,264 | 40.88 | 12,551 | 41.83 |
| 6,480 | 5,504 | 14,568 | 48.56 | 14,911 | 49.70 |
| 12,248 | 6,144 | 16,200 | 54 | 16,583 | 55.27 |
K Laki vs Latency
- No ka max_iter=6
Kiʻi 19. K Nui vs ka manawa hana
- No ka max_iter=6
K Laki vs Latency
- No ka max_iter=8
Ka Nui K me ka manawa hana
- No ka max_iter=8
Moʻolelo Hoʻoponopono Hou no ka 4G Turbo-V Intel FPGA IP alakaʻi hoʻohana
| Lā | Manaʻo IP | ʻO Intel Quartus Prime Software Version | Nā hoʻololi |
| 2020.11.18 | 1.0.0 | 20.1 | Wehe ʻia ka papa i loko 4G Turbo-V hana a me ka hoʻohana waiwai |
| 2020.06.02 | 1.0.0 | 20.1 | Hoʻokuʻu mua. |
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
Palapala / Punawai
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intel 4G Turbo-V FPGA IP [pdf] Ke alakaʻi hoʻohana 4G Turbo-V FPGA IP, 4G Turbo-V, FPGA IP |
