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intel 4G Turbo-V FPGA IP

intel-4G-Turbo-V-FPGA-IP-ọja

Nipa 4G Turbo-V Intel® FPGA IP

Awọn koodu ikanni atunṣe-aṣiṣe siwaju (FEC) ni igbagbogbo mu imunadoko agbara ti awọn eto ibaraẹnisọrọ alailowaya pọ si. Awọn koodu Turbo dara fun awọn ibaraẹnisọrọ alagbeka 3G ati 4G (fun apẹẹrẹ, ni UMTS ati LTE) ati awọn ibaraẹnisọrọ satẹlaiti. O le lo awọn koodu Turbo ni awọn ohun elo miiran ti o nilo gbigbe alaye ti o gbẹkẹle lori bandiwidi- tabi awọn ọna asopọ ibaraẹnisọrọ ti o ni idiwọ ni iwaju ariwo data-ibajẹ. 4G Turbo-V Intel® FPGA IP ni ọna asopọ isalẹ ati imuyara isopo fun vRAN ati pẹlu Turbo Intel FPGA IP. Awọn ohun imuyara downlink ṣe afikun apọju si data ni irisi alaye ti o jọmọ.Ohun imuyara uplink nilo apọju lati ṣe atunṣe nọmba to tọ ti awọn aṣiṣe ikanni.

Alaye ti o jọmọ

  • Turbo Intel FPGA IP Itọsọna olumulo
  • 3GPP TS 36.212 version 15.2.1 Tu 15

4G Turbo-V Intel FPGA IP Awọn ẹya ara ẹrọ

Ohun imuyara isale pẹlu:

  • Koodu dina koodu cyclic apọju (CRC) asomọ
  • Turbo kooduopo
  • Ibaramu oṣuwọn Turbo pẹlu:
    • Subblock interleaver
    • Bit-odè
    • Aṣayan Bit
    • Pireje Bit

Ohun imuyara uplink pẹlu:

  • Subblock deinterleaver
  • Turbo decoder pẹlu CRC ayẹwo

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

4G Turbo-V Intel FPGA IP Device Support Ìdílé

Intel nfunni ni awọn ipele atilẹyin ẹrọ atẹle fun Intel FPGA IP:

  • Atilẹyin ilosiwaju — IP wa fun kikopa ati akopọ fun ẹbi ẹrọ yii. FPGA siseto file Atilẹyin (.pof) ko si fun Quartus Prime Pro Stratix 10 Edition Beta software ati bi iru pipade akoko IP ko le ṣe iṣeduro. Awọn awoṣe akoko pẹlu awọn iṣiro imọ-ẹrọ akọkọ ti awọn idaduro ti o da lori alaye ni kutukutu lẹhin-ipinlẹ. Awọn awoṣe akoko jẹ koko ọrọ si iyipada bi idanwo ohun alumọni ṣe ilọsiwaju ibamu laarin ohun alumọni gangan ati awọn awoṣe akoko. O le lo ipilẹ IP yii fun faaji eto ati awọn ẹkọ lilo awọn orisun, kikopa, pinout, awọn igbelewọn lairi eto, awọn igbelewọn akoko ipilẹ (isuna opo gigun), ati ilana gbigbe I/O (iwọn-ọna data, ijinle ti nwaye, awọn iṣowo awọn iṣedede I/O ).
  • Atilẹyin alakoko-Intel ṣe idaniloju ipilẹ IP pẹlu awọn awoṣe akoko alakoko fun ẹbi ẹrọ yii. Ipilẹ ipilẹ IP pade gbogbo awọn ibeere iṣẹ ṣiṣe, ṣugbọn o le tun wa ni ṣiṣe itupalẹ akoko fun ẹbi ẹrọ naa. O le lo ni awọn aṣa iṣelọpọ pẹlu iṣọra.
  • Atilẹyin ipari-Intel ṣe idaniloju IP pẹlu awọn awoṣe akoko ipari fun ẹbi ẹrọ yii. IP pade gbogbo iṣẹ ṣiṣe ati awọn ibeere akoko fun ẹbi ẹrọ. O le lo ni awọn apẹrẹ iṣelọpọ.

4G Turbo-V IP Device Support Ìdílé

Ẹrọ Ìdílé Atilẹyin
Intel Agilex™ Ilọsiwaju
Intel Arria® 10 Ipari
Intel Stratix® 10 Ilọsiwaju
Miiran ẹrọ idile Ko si atilẹyin

Alaye itusilẹ fun 4G Turbo-V Intel FPGA IP

Awọn ẹya Intel FPGA IP ibaamu awọn ẹya sọfitiwia Intel Quartus® Prime Design Suite titi di v19.1. Bibẹrẹ ni Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2, Intel FPGA IP ni ero ti ikede tuntun kan. Nọmba Intel FPGA IP ẹya (XYZ) le yipada pẹlu ẹya sọfitiwia Intel Quartus Prime kọọkan. Iyipada ninu:

  • X tọkasi atunyẹwo pataki ti IP. Ti o ba ṣe imudojuiwọn sọfitiwia Intel Quartus Prime, o gbọdọ tun IP ṣe.
  • Y tọkasi IP pẹlu awọn ẹya tuntun. Tun IP rẹ ṣe lati ni awọn ẹya tuntun wọnyi.
  • Z tọkasi IP pẹlu awọn ayipada kekere. Tun IP rẹ ṣe lati fi awọn ayipada wọnyi kun.

4G Turbo-V IP Alaye Tu

Nkan Apejuwe
Ẹya 1.0.0
Ojo ifisile Oṣu Kẹrin Ọjọ 2020

4G Turbo-V Performance ati Resource Lilo

Intel ṣe ipilẹṣẹ iṣamulo orisun ati iṣẹ nipasẹ ṣiṣe akopọ awọn apẹrẹ pẹlu sọfitiwia Intel Quartus Prime v19.1. Lo awọn abajade isunmọ wọnyi nikan fun iṣiro ni kutukutu ti awọn orisun FPGA (fun apẹẹrẹ awọn modulu adaṣe adaṣe (ALMs)) ti iṣẹ akanṣe kan nilo. Awọn igbohunsafẹfẹ afojusun jẹ 300 MHz.

Imudara orisun Imuyara Downlink ati Igbohunsafẹfẹ ti o pọju fun awọn Ẹrọ Intel Arria 10

Modulu fMAX (MHz) Awọn ALMs ALUTs Awọn iforukọsilẹ Iranti (Bits) Awọn bulọọki Ramu (M20K) Awọn bulọọki DSP
Downlink ohun imuyara 325.63 9,373 13,485 14,095 297,472 68 8
CRC asomọ 325.63 39 68 114 0 0 0
Turbo kooduopo 325.63 1,664 2,282 1154 16,384 16 0
Oṣuwọn ibaamu 325.63 7,389 10,747 12,289 274,432 47 8
Subblock interleaver 325.63 2,779 3,753 5,559 52,416 27 0
Bit-odè 325.63 825 1,393 2,611 118,464 13 4
Bit selector ati pruner 325.63 3,784 5,601 4,119 103,552 7 4

Uplink Accelerator Resource iṣamulo ati Igbohunsafẹfẹ to pọju fun Intel Arria 10 Awọn ẹrọ

Modulu fMAX (MHz) Awọn ALMs Awọn iforukọsilẹ Iranti (Bits) Awọn bulọọki Ramu (M20K) Awọn bulọọki DSP
Uplink ohun imuyara 314.76 29480 30,280 868,608 71 0
Subblock deinterleaver 314.76 253 830 402,304 27 0
Turbo decoder 314.76 29,044 29,242 466,304 44 0

Apẹrẹ pẹlu 4G Turbo-V Intel FPGA IP

4G Turbo-V IP Directory Be

O gbọdọ fi sori ẹrọ IP pẹlu ọwọ lati inu insitola IP.

Fifi sori Directory Beintel-4G-Turbo-V-FPGA-IP-FIG-1

Ṣiṣẹda 4G Turbo-V IP

O le ṣe ina isale tabi isare oke. Fun ohun imuyara uplink, ropo dl pẹlu ul ni liana tabi file awọn orukọ.

  1. Ṣii sọfitiwia Intel Quartus Prime Pro.
  2. Yan File ➤ New Project oso.
  3. Tẹ Itele.
  4. Tẹ orukọ Project dl_fec_wrapper_top sii ki o si tẹ ipo iṣẹ naa sii.
  5. Yan ẹrọ Arria 10.
  6. Tẹ Pari.
  7. Ṣii dl_fec_wrapper_top.qpf file wa ni iwe ilana ise agbese Oluṣeto iṣẹ yoo han.
  8. Lori taabu Onise Platform:
    • Ṣẹda dl_fec_wrapper_top.ip file lilo hardware tcl file.
    • Tẹ Ina HDL lati ṣe ina apẹrẹ files.
  9. Lori awọn ina taabu, tẹ ina igbeyewo ibujoko eto.
  10. Tẹ Fi gbogbo rẹ kun lati ṣafikun iṣelọpọ files si ise agbese. Awọn files wa ni src \ ip \ dl_fec_wrapper_top \ dl_fec_wrapper_10 \ synth.
  11. Ṣeto dl_fec_wrapper_top.v file bi oke ipele nkankan.
  12. Tẹ Ipilẹṣẹ Ibẹrẹ lati ṣajọ iṣẹ yii.

Simulating a 4G Turbo-V IP

Iṣẹ-ṣiṣe yii jẹ fun simulating isare ọna asopọ isalẹ. Lati ṣe afiwe ohun imuyara uplink ropo dl pẹlu ul ni kọọkan liana tabi file oruko.

  1. Ṣii Simulator ModelSim 10.6d FPGA Edition.
  2. Yi liana pada si src\ip\dl_fec_wrapper_top_tb \dl_fec_wrapper_top_tb\sim\ mentor
  3. Yi QUARTUS_INSTALL_DIR pada sinu ilana Intel Quartus Prime ninu msim_setup.tcl file, eyi ti o wa ni \ sim \ director director
  4. Tẹ aṣẹ naa ṣe load_sim.tcl aṣẹ ni window tiransikiripiti. Yi aṣẹ gbogbo awọn ìkàwé files ati akopọ ati ki o simulates awọn orisun files ninu msim_setup.tcl file. Awọn fekito idanwo wa ninu filename_update.sv ninu \ sim liana.

Awọn fileimudojuiwọn orukọ File Ilana

  • Fekito idanwo ti o baamu files wa ni sim \ olutojueni \ test_vectors
  • Log.txt ni abajade ti gbogbo awọn apo-iwe idanwo.
  • Fun isale isale, encoder_pass_file.txt ni ijabọ igbasilẹ ti gbogbo atọka ti awọn apo-iwe idanwo ati koodu koodu_file_error.txt ni ijabọ ikuna ti gbogbo atọka ti awọn apo-iwe idanwo.
  • Fun imuyara oke, Aṣiṣe_file.txt ni ijabọ ikuna ti gbogbo atọka ti awọn apo-iwe idanwo.intel-4G-Turbo-V-FPGA-IP-FIG-2

4G Turbo-V Intel FPGA IP išẹ Apejuwe

4G Turbo-V Intel FPGA IP ni ohun imuyara isale isalẹ ati imuyara oke.

  • 4G Turbo-V Architecture ni oju-iwe 9
  • Awọn ifihan agbara Turbo-V 4G ati Awọn atọkun loju iwe 11
  • Awọn aworan akoko Turbo-V 4G ni oju-iwe 15
  • 4G Turbo-V Lairi ati Gbigbe ni oju-iwe 18

4G Turbo-V Architecture

4G Turbo-V Intel FPGA IP ni ohun imuyara isale isalẹ ati imuyara oke.

4G Downlink ohun imuyara

4G Turbo downlink ohun imuyara oriširiši koodu Àkọsílẹ CRC asomọ koodu ati ki o kan Turbo encoder (Intel Turbo FPGA IP) ati oṣuwọn baramu. Awọn data igbewọle jẹ 8-bit fife ati awọn ti o wu data jẹ 24-bit fife. Ibaramu oṣuwọn ni awọn interleavers subblock mẹta, oluyan diẹ, ati olugba diẹ.intel-4G-Turbo-V-FPGA-IP-FIG-3

Ohun imuyara isale isalẹ 4G ṣe imuse koodu Àkọsílẹ CRC asomọ pẹlu 8-bit ni afiwe CRC iṣiro algorithm. Iṣagbewọle si bulọọki asomọ CRC jẹ iwọn 8-bit. Ni ipo deede, nọmba awọn igbewọle si bulọọki CRC jẹ k-24, nibiti k jẹ iwọn bulọki ti o da lori atọka iwọn. Ilana afikun CRC ti awọn die-die 24 ni a so mọ koodu koodu ti nwọle ti data ninu bulọọki asomọ CRC ati lẹhinna kọja si koodu Turbo. Ni ipo fori CRC, nọmba awọn igbewọle jẹ iwọn k ti 8-bit fife kọja si bulọọki encoder Turbo.

Encoder Turbo nlo koodu concatenated concatenated ti o jọra. Ayipada convolutional n ṣe koodu itọsẹ alaye kan ati koodu iyipada convolution miiran n ṣe koodu koodu ti ẹya interleaved ti ọkọọkan alaye naa. Awọn koodu koodu Turbo ni awọn koodu iyipada convolutional meji-ipinle 8 ati koodu Turbo kan ti inu interleaver. Fun alaye diẹ sii nipa koodu koodu Turbo, tọka si Itọsọna olumulo Turbo IP Core. Ibaramu oṣuwọn baamu nọmba awọn die-die ni idina gbigbe si nọmba awọn die-die ti IP n gbejade ni ipin yẹn. Iṣagbewọle ati iṣejade ti ibaamu oṣuwọn jẹ awọn bit 24. IP n ṣalaye ibaramu oṣuwọn fun awọn ikanni irinna koodu Turbo fun bulọọki koodu kọọkan. Ibaramu oṣuwọn ni ninu: interleaver subblock, olugba bit ati yiyan bit. Ohun imuyara ọna asopọ isalẹ ṣeto idawọle subblock fun ṣiṣanjade kọọkan lati ifaminsi Turbo. Awọn ṣiṣan naa pẹlu ṣiṣan ifiranṣẹ bit, ṣiṣan 1st parity bit ṣiṣan ati ṣiṣan 2nd parity bit. Iṣagbewọle ati iṣejade ti isale interleaved jẹ awọn bit 24 fife. Alakojo bit daapọ awọn ṣiṣan ti o wa lati subblock interleaver. Àkọsílẹ yii ni awọn ifipamọ ti o tọju:

  • Awọn ifiranšẹ ati kikun ti n mu awọn die-die laaye lati inu subblock ti wa ni interleaved.
  • Subblock interleaved paraty bits ati awọn oniwun wọn die-die kikun.

Bit-odè

intel-4G-Turbo-V-FPGA-IP-FIG-4

4G ikanni Uplink imuyara

4G Turbo uplink ohun imuyara oriširiši subblock deinterleaver ati turbo decoder (Intel Turbo FPGA IP).intel-4G-Turbo-V-FPGA-IP-FIG-5

Deinterleaver ni awọn bulọọki mẹta ninu eyiti awọn bulọọki meji akọkọ jẹ iṣiro ati bulọọki kẹta yatọ.

Lairi ifihan agbara ti o ṣetan jẹ 0.

Deinterleaver

intel-4G-Turbo-V-FPGA-IP-FIG-6

Ti o ba tan ipo fori fun subblock deinterleaver, IP naa ka data naa bi o ṣe n kọ data sinu awọn bulọọki iranti ni awọn ipo ti o tẹle. IP naa ka data bi ati nigba ti o kọ data laisi eyikeyi interleaving. Nọmba ti data titẹ sii sinu subblock deinterleaver jẹ K_π ni ipo fori ati ipari data ijade jẹ iwọn k (k jẹ iwọn Àkọsílẹ koodu ti o da lori iye cb_size_index). Lairi data ijade ti subblock deinterleaver da lori iwọn bulọọki igbewọle K_π. IP naa ka data naa nikan lẹhin ti o kọ iwọn idina koodu K_π ti data igbewọle. Nitorinaa lairi ti iṣelọpọ tun pẹlu akoko kikọ. Lairi ninu data idajade interleaver subblock jẹ K_π+17. Oluyipada Turbo ṣe iṣiro ọna ti o ṣeeṣe julọ ti a firanṣẹ, da lori sampki o gba. Fun alaye alaye, tọka si Itọsọna olumulo Turbo Core IP. Yiyipada awọn koodu atunṣe aṣiṣe jẹ afiwe awọn iṣeeṣe fun oriṣiriṣi awọn koodu ariyanjiyan. Turbo decoder oriširiši meji nikan asọ-ni asọ-jade (SISO) decoders, eyi ti o ṣiṣẹ leralera. Ijade ti akọkọ (decoder oke) ifunni sinu keji lati ṣe agbekalẹ iyipada iyipada Turbo kan. Interleaver ati deinterleaver di awọn bulọọki atunbere data ninu ilana yii.

Alaye ti o jọmọ
Turbo IP mojuto User Itọsọna

4G Turbo-V Awọn ifihan agbara ati awọn atọkun

Isalẹ ohun imuyaraintel-4G-Turbo-V-FPGA-IP-FIG-7

Downlink imuyara Awọn ifihan agbara

Orukọ ifihan agbara Itọsọna Iwọn Bit Apejuwe
clk Iṣawọle 1 300 MHz aago input. Gbogbo awọn ifihan agbara wiwo Turbo-V IP jẹ amuṣiṣẹpọ si aago yii.
atunto_n Iṣawọle 1 Tun awọn ti abẹnu kannaa ti gbogbo IP.
sink_wulo Iṣawọle 1 Ti fi idi rẹ mulẹ nigbati data ni sink_data wulo. Nigbati sink_valid ko ba fi idi rẹ mulẹ, IP n ṣiṣẹ sisẹ titi ti sink_valid yoo tun fi sii.
rì_data Iṣawọle 8 Ni igbagbogbo n gbe ọpọlọpọ alaye ti a gbe lọ.
rii_sop Iṣawọle 1 Tọkasi ibẹrẹ ti apo ti nwọle
sinki_eop Iṣawọle 1 Tọkasi ipari ti apo ti nwọle
rì_ṣetan Abajade 1 Tọkasi nigbati IP le gba data
Rin_aṣiṣe Iṣawọle 2 Iboju-meji-bit lati tọka awọn aṣiṣe ti o kan data ti o ti gbe ni ọmọ lọwọlọwọ.
Crc_ṣiṣẹ Iṣawọle 1 Mu idinamọ CRC ṣiṣẹ
Cb_size_index Iṣawọle 8 Iwọn idinaki koodu igbewọle K
sink_rm_out_size Iṣawọle 20 Oṣuwọn iwọn idinajade ti o baamu, ti o baamu si E.
sink_code_blocks Iṣawọle 15 Iwọn ifipamọ asọ fun idinamọ koodu lọwọlọwọ Ncb
sink_rv_idx Iṣawọle 2 Atọka ẹya apọju (0,1,2 tabi 3)
sink_rm_bypass Iṣawọle 1 Mu ipo fori ṣiṣẹ ni ibaamu oṣuwọn
sink_filler_bits Iṣawọle 6 Nọmba ti kikun nfa awọn ifibọ IP ni atagba nigbati IP ṣe ipin idina koodu.
orisun_wulo Abajade 1 Ijẹrisi nipasẹ IP nigbati data to wulo wa lati ṣejade.
tesiwaju…
Orukọ ifihan agbara Itọsọna Iwọn Bit Apejuwe
orisun_data Abajade 24 O gbe ọpọlọpọ alaye ti o ti gbe. Alaye yii wa nibiti o ti jẹri.
orisun_sop Abajade 1 Tọkasi ibẹrẹ ti apo-iwe kan.
orisun_eop Abajade 1 Tọkasi opin ti a soso.
orisun_ṣetan Iṣawọle 1 Gbigba data wulo nibiti ifihan ti o ti ṣetan ti jẹri.
orisun_aṣiṣe Abajade 2 Ifihan aṣiṣe ti tan kaakiri lati Turbo Encoder ti n tọka si awọn irufin ilana Avalon-ST ni ẹgbẹ orisun

• 00: Ko si aṣiṣe

• 01: Sonu ibere ti soso

• 10: sonu opin ti soso

• 11: Ipari airotẹlẹ ti apo-iwe miiran Awọn iru aṣiṣe le tun jẹ samisi bi 11.

Orisun_blk_iwọn Abajade 13 Iwọn bulọki koodu Ijade K

Uplink imuyara atọkun

intel-4G-Turbo-V-FPGA-IP-FIG-8

Uplink imuyara Awọn ifihan agbara

Ifihan agbara Itọsọna Iwọn Bit Apejuwe
clk Iṣawọle 1 300 MHz aago input. Gbogbo awọn ifihan agbara wiwo Turbo-V IP jẹ amuṣiṣẹpọ si aago yii.
atunto_n Iṣawọle 1 Tun ifihan aago titẹ sii
sink_wulo Iṣawọle 1 Iṣagbewọle ṣiṣanwọle Avalon wulo
rì_data Iṣawọle 24 Avalon data igbewọle ṣiṣanwọle
rii_sop Iṣawọle 1 Ibẹrẹ titẹ sii ṣiṣanwọle Avalon ti apo
sinki_eop Iṣawọle 1 Avalon śiśanwọle input opin ti soso
tesiwaju…
Ifihan agbara Itọsọna Iwọn Bit Apejuwe
rì_ṣetan Iṣawọle 1 Iṣagbewọle ṣiṣanwọle Avalon ti ṣetan
conf_wulo Iṣawọle 1 Opopona atunto igbewọle wulo
cb_size_index Iṣawọle 8 Àkọsílẹ iwọn aṣetunṣe atọka
max_iteration Iṣawọle 5 O pọju aṣetunṣe
rm_bypass Iṣawọle 1 Mu ipo fori ṣiṣẹ
sel_CRC24A Iṣawọle 1 Ni pato iru CRC ti o nilo fun idinamọ data lọwọlọwọ:

• 0: CRC24A

• 1: CRC24B

conf_setan Iṣawọle 1 Conduit iṣeto ni igbewọle setan
orisun_wulo Abajade 1 Avalon śiśanwọle o wu wulo
orisun_data Abajade 16 Avalon śiśanwọle o wu data
orisun_sop Abajade 1 Ibẹrẹ ṣiṣanwọle Avalon ti apo
orisun_eop Abajade 1 Avalon śiśanwọle o wu opin ti soso
orisun_aṣiṣe Abajade 2 Ifihan aṣiṣe ti n tọka si awọn irufin ilana ṣiṣanwọle Avalon ni ẹgbẹ orisun:

• 00: Ko si aṣiṣe

• 01: Sonu ibere ti soso

• 10: sonu opin ti soso

• 11: Ipari airotẹlẹ ti apo-iwe miiran Awọn iru aṣiṣe le tun jẹ samisi bi 11.

orisun_ṣetan Abajade 1 Avalon ṣiṣanwọle ti ṣetan
CRC_type Abajade 1 Tọkasi iru CRC ti a lo fun idinamọ data lọwọlọwọ:

• 0: CRC24A

• 1: CRC24B

orisun_blk_size Abajade 13 Ṣe apejuwe iwọn bulọọki ti njade
CRC_pass Abajade 1 Tọkasi boya CRC ṣaṣeyọri:

• 0: Ikuna

• 1: Kọja

source_iter Abajade 5 Ṣe afihan nọmba awọn iterations idaji lẹhin eyiti Turbo decoder duro ṣiṣiṣẹ bulọọki data lọwọlọwọ.

Awọn atọkun ṣiṣanwọle Avalon ni DSP Intel FPGA IP
Awọn atọkun ṣiṣanwọle Avalon ṣe asọye boṣewa, rọ, ati ilana modular fun awọn gbigbe data lati wiwo orisun si wiwo ifọwọ kan. Ni wiwo input jẹ ẹya Avalon sisanwọle rii ati awọn ti o wu ni wiwo jẹ ẹya Avalon sisanwọle orisun. Ni wiwo ṣiṣanwọle Avalon ṣe atilẹyin awọn gbigbe soso pẹlu awọn apo-iwe ti o wa laarin awọn ikanni pupọ. Awọn ifihan agbara ṣiṣanwọle Avalon le ṣe apejuwe awọn atọkun ṣiṣanwọle ibile ti n ṣe atilẹyin ṣiṣan kan ti data laisi imọ ti awọn ikanni tabi awọn aala apo. Iru awọn atọkun ni igbagbogbo ni data ninu, ṣetan, ati awọn ifihan agbara to wulo. Awọn atọkun ṣiṣanwọle Avalon tun le ṣe atilẹyin awọn ilana ti eka diẹ sii fun ti nwaye ati awọn gbigbe soso pẹlu awọn apo-iwe ti o wa laarin awọn ikanni lọpọlọpọ. Ni wiwo ṣiṣanwọle Avalon n muuṣiṣẹpọ awọn aṣa multichannel, eyiti o fun ọ laaye lati ṣaṣeyọri daradara, awọn imuse akoko-pupọ laisi nini lati ṣe imuṣiṣẹ ọgbọn iṣakoso eka. Awọn atọkun ṣiṣanwọle Avalon ṣe atilẹyin ifẹhinti ẹhin, eyiti o jẹ ilana iṣakoso ṣiṣan nibiti ifọwọ kan le ṣe ifihan si orisun kan lati da fifiranṣẹ data duro. Awọn ifọwọ ojo melo nlo backpressure lati da awọn sisan ti data nigbati awọn oniwe-FIFO buffers ti kun tabi nigbati o ni o ni awọn go slo lori awọn oniwe-jade.

Alaye ti o jọmọ
Avalon Interface pato

4G Turbo-V Awọn aworan atọka akoko

Aworan akoko fun Kọ kannaa pẹlu Codeblock 40

IP naa:

  • Gbe asan 20 die-die ni iwe 0 si 19 ati kọ awọn die-die data lati ori 20.
  • Kọ gbogbo awọn die-die 44 si iranti ni awọn akoko aago mẹfa.
  • Kọ awọn iwọn ifopinsi trellis sinu iwe 28 si 31.
  • Awọn ilọsiwaju kọ adirẹsi fun ila kọọkan.
  • Awọn ipilẹṣẹ kikọ agbara ifihan agbara fun 8 Ramu kọọkan ni akoko kan.

IP naa ko kọ awọn iwọn kikun sinu Ramu. Dipo, IP fi aaye dimu silẹ fun awọn die-die àlẹmọ ninu Ramu ati fi awọn NULL die-die sinu iṣelọpọ lakoko ilana kika. Ikọwe akọkọ bẹrẹ lati iwe 20.intel-4G-Turbo-V-FPGA-IP-FIG-9

Aworan akoko fun kika kannaa pẹlu Codeblock 40

Fun kika kọọkan, o rii awọn iwọn 8 ni iwọn aago kan ṣugbọn awọn die-die meji nikan ni o wulo. IP naa kọ awọn die-die meji wọnyi sinu iforukọsilẹ iyipada. Nigbati awọn IP fọọmu 8 die-die o rán wọn si awọn wu ni wiwo.intel-4G-Turbo-V-FPGA-IP-FIG-10

Aworan akoko fun Kọ kannaa pẹlu Codeblock 6144

Awọn die-die kikun jẹ lati iwe 0 si 27 ati awọn die-die data wa lati ọwọn 28. IP naa:

  • Kọ gbogbo awọn die-die 6,148 si iranti ni awọn akoko aago mẹfa.
  • Kọ awọn iwọn ifopinsi trellis sinu iwe 28 si 31.
  • Awọn ilọsiwaju kọ adirẹsi fun ila kọọkan.
  • Ṣe ipilẹṣẹ kikọ agbara ifihan agbara ti ipilẹṣẹ fun 8 Ramu kọọkan ni akoko kan.

IP naa ko kọ awọn iwọn kikun sinu Ramu. Dipo IP fi aaye dimu silẹ fun awọn iwọn àlẹmọ lori Ramu ati ki o fi awọn NULL die-die sinu iṣelọpọ lakoko ilana kika. Ikọwe akọkọ bẹrẹ lati iwe 28.intel-4G-Turbo-V-FPGA-IP-FIG-11

Aworan akoko fun kika kannaa pẹlu Codeblock 6144

Ni ẹgbẹ kika, kika kọọkan n fun awọn die-die 8. Lakoko ti o ti ka awọn 193rd kana, IP ka 8 die-die, sugbon nikan kan bit jẹ wulo. IP naa ṣe awọn iwọn mẹjọ pẹlu awọn iforukọsilẹ iṣipopada ati firanṣẹ wọn jade nipa kika lati iwe atẹle.intel-4G-Turbo-V-FPGA-IP-FIG-12

Aworan Aago Input

intel-4G-Turbo-V-FPGA-IP-FIG-13

Aworan akoko ti o wu jade

intel-4G-Turbo-V-FPGA-IP-FIG-14

4G Turbo-V Lairi ati Nipasẹ

Lairi naa jẹ wiwọn laarin iṣagbewọle akọkọ soso SOP lati jade soso akọkọ SOP. Akoko sisẹ naa jẹ iwọn laarin iṣagbewọle akọkọ soso SOP lati ṣe agbejade apo-iwe ti o kẹhin EOP.

Downlink ohun imuyara
Imujade jẹ oṣuwọn eyiti IP le fa titẹ sii sinu isare isale bi o ti ṣetan.

Isalẹ Accelerator Lairi, Akoko Sisẹ, ati Gbigbe
Pẹlu iwọn K ti o pọju ti 6,144 ati iwọn E ti 11,522. Akoko ṣiṣe iwọn fun awọn bulọọki koodu 13. Iyara aago jẹ 300 MHz.

K E Lairi Akoko ṣiṣe Iṣagbewọle ti nwọle
    (awọn iyipo) (awa) (awọn iyipo) (awa) (%)
6,144 11,552 3,550 11.8 14,439 48.13 95

Lairi ati Iṣiro Time Time

  • Nọmba naa fihan ilana lati ṣe iṣiro lairi, akoko sisẹ, ati igbejade.intel-4G-Turbo-V-FPGA-IP-FIG-15

K Iwon dipo Lairi

intel-4G-Turbo-V-FPGA-IP-FIG-16

K Iwon dipo Lairi

  • k=40 si 1408intel-4G-Turbo-V-FPGA-IP-FIG-17

Uplink Accelerator Lairi ati Akoko Ilana

  • Pẹlu max aṣetunṣe nọmba = 6. Aago iyara jẹ 300 MHz.
    K E Lairi Akoko ṣiṣe
        (awọn iyipo) (awa) (awọn iyipo) (awa)
    86 40 316 1.05 318 1.06
    34,560 720 2,106 7.02 2,150 7.16
    34,560 1,408 3,802 12.67 3,889 12.96
    34,560 1,824 4,822 16.07 4,935 16.45
    28,788 2,816 7,226 24.08 7,401 24.67
    23,742 3,520 8,946 29.82 9,165 30.55
    34,560 4,032 10,194 33.98 10,445 34.81
    26,794 4,608 11,594 38.64 11,881 39.60
    6,480 5,504 13,786 45.95 14,129 47.09
    12,248 6,144 15,338 51.12 15,721 52.40

Uplink Accelerator Lairi ati Akoko Ilana

  • Pẹlu nọmba aṣetunṣe ti o pọju = 8
K E Lairi Akoko ṣiṣe
    (awọn iyipo) (awa) (awọn iyipo) (awa)
86 40 366 1.22 368 1.22
34,560 720 2,290 7.63 2,334 7.78
34,560 1,408 4,072 13.57 4,159 13.86
34,560 1,824 5,144 17.14 5,257 17.52
28,788 2,816 7,672 25.57 7,847 26.15
tesiwaju…
23,742 3,520 9,480 31.6 9,699 32.33
34,560 4,032 10,792 35.97 11,043 36.81
26,794 4,608 12,264 40.88 12,551 41.83
6,480 5,504 14,568 48.56 14,911 49.70
12,248 6,144 16,200 54 16,583 55.27

K Iwon vs Lairi

  • Fun max_iter=6intel-4G-Turbo-V-FPGA-IP-FIG-18

olusin 19. K Iwon vs Processing Time

  • Fun max_iter=6intel-4G-Turbo-V-FPGA-IP-FIG-19

K Iwon vs Lairi

  • Fun max_iter=8intel-4G-Turbo-V-FPGA-IP-FIG-20

K Iwon vs Processing Time

  • Fun max_iter=8intel-4G-Turbo-V-FPGA-IP-FIG-21

Itan Atunyẹwo iwe fun 4G Turbo-V Intel FPGA IP Itọsọna olumulo

Ọjọ Ẹya IP Intel Quartus NOMBA Software Version Awọn iyipada
2020.11.18 1.0.0 20.1 Yiyọ tabili ni 4G Turbo-V Performance ati Resource Lilo
2020.06.02 1.0.0 20.1 Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

Awọn iwe aṣẹ / Awọn orisun

intel 4G Turbo-V FPGA IP [pdf] Itọsọna olumulo
4G Turbo-V FPGA IP, 4G Turbo-V, FPGA IP

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