User Guide for intel models including: 4G Turbo-V FPGA IP, 4G Turbo-V, FPGA IP
2. Designing with the 4G Turbo-V Intel FPGA IP
1.2. 4G Turbo-V Intel FPGA IP Device Family Support
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DocumentDocument4G Turbo-V Intel® FPGA IP User Guide Updated for Intel® Quartus® Prime Design Suite: 20.1 IP Version: 1.0.0 Online Version Send Feedback UG-20279 ID: 683882 Version: 2020.11.18 Contents Contents 1. About the 4G Turbo-V Intel® FPGA IP............................................................................. 3 1.1. 4G Turbo-V Intel FPGA IP Features........................................................................... 3 1.2. 4G Turbo-V Intel FPGA IP Device Family Support........................................................4 1.3. Release Information for the 4G Turbo-V Intel FPGA IP.................................................4 1.4. 4G Turbo-V Performance and Resource Utilization...................................................... 5 2. Designing with the 4G Turbo-V Intel FPGA IP................................................................. 6 2.1. 4G Turbo-V IP Directory Structure............................................................................6 2.2. Generating a 4G Turbo-V IP.................................................................................... 7 2.3. Simulating a 4G Turbo-V IP..................................................................................... 7 3. 4G Turbo-V Intel FPGA IP Functional Description........................................................... 9 3.1. 4G Turbo-V Architecture......................................................................................... 9 3.2. 4G Turbo-V Signals and Interfaces......................................................................... 11 3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP........................................ 14 3.3. 4G Turbo-V Timing Diagrams................................................................................. 15 3.4. 4G Turbo-V Latency and Throughput.......................................................................18 4. Document Revision History for the 4G Turbo-V Intel FPGA IP User Guide..................... 23 4G Turbo-V Intel® FPGA IP User Guide 2 Send Feedback 683882 | 2020.11.18 Send Feedback 1. About the 4G Turbo-V Intel® FPGA IP Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems. Turbo codes are suitable for 3G and 4G mobile communications (e.g., in UMTS and LTE) and satellite communications. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of datacorrupting noise. The 4G Turbo-V Intel® FPGA IP comprises a downlink and uplink accelerator for vRAN and includes the Turbo Intel FPGA IP. The downlink accelerator adds redundancy to the data in the form of parity information.The uplink accelerator exploits redundancy to correct a reasonable number of channel errors. Related Information · Turbo Intel FPGA IP User Guide · 3GPP TS 36.212 version 15.2.1 Release 15 1.1. 4G Turbo-V Intel FPGA IP Features The downlink accelerator includes: · Code block cyclic redundancy code (CRC) attachment · Turbo encoder · Turbo rate matcher with: -- Subblock interleaver -- Bit collector -- Bit selector -- Bit pruner The uplink accelerator includes: · Subblock deinterleaver · Turbo decoder with CRC check Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 1. About the 4G Turbo-V Intel® FPGA IP 683882 | 2020.11.18 1.2. 4G Turbo-V Intel FPGA IP Device Family Support Intel offers the following device support levels for Intel FPGA IP: · Advance support--the IP is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs). · Preliminary support--Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution. · Final support--Intel verifies the IP with final timing models for this device family. The IP meets all functional and timing requirements for the device family. You can use it in production designs. Table 1. 4G Turbo-V IP Device Family Support Device Family Intel AgilexTM Intel Arria® 10 Intel Stratix® 10 Other device families Advance Final Advance No support Support 1.3. Release Information for the 4G Turbo-V Intel FPGA IP Intel FPGA IP versions match the Intel Quartus® Prime Design Suite software versions until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP has a new versioning scheme. The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime software version. A change in: · X indicates a major revision of the IP. If you update the Intel Quartus Prime software, you must regenerate the IP. · Y indicates the IP includes new features. Regenerate your IP to include these new features. · Z indicates the IP includes minor changes. Regenerate your IP to include these changes. Table 2. 4G Turbo-V IP Release Information Version Release Date Item 1.0.0 April 2020 Description 4G Turbo-V Intel® FPGA IP User Guide 4 Send Feedback 1. About the 4G Turbo-V Intel® FPGA IP 683882 | 2020.11.18 1.4. 4G Turbo-V Performance and Resource Utilization Intel generated the resource utilization and performance by compiling the designs with Intel Quartus Prime software v19.1. Only use these approximate results for early estimation of FPGA resources (e.g. adaptive logic modules (ALMs)) that a project requires. The target frequency is 300 MHz. Table 3. Downlink Accelerator Resource Utilization and Maximum Frequency for Intel Arria 10 Devices Module Downlink accelerator CRC attachment fMAX (MHz) ALMs ALUTs Registers Memory (Bits) RAM Blocks (M20K) DSP Blocks 325.63 9,373 13,485 14,095 297,472 68 8 325.63 39 68 114 0 0 0 Turbo encoder 325.63 1,664 2,282 1154 16,384 16 0 Rate matcher 325.63 7,389 10,747 12,289 274,432 47 8 Subblock interleaver 325.63 2,779 3,753 5,559 52,416 27 0 Bit collector 325.63 825 1,393 2,611 118,464 13 4 Bit selector and pruner 325.63 3,784 5,601 4,119 103,552 7 4 Table 4. Uplink Accelerator Resource Utilization and Maximum Frequency for Intel Arria 10 Devices Module Uplink accelerator Subblock deinterleaver Turbo decoder fMAX (MHz) ALMs 314.76 29480 314.76 253 314.76 29,044 Registers Memory (Bits) 30,280 868,608 830 402,304 29,242 466,304 RAM Blocks (M20K) 71 27 44 DSP Blocks 0 0 0 Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 5 683882 | 2020.11.18 Send Feedback 2. Designing with the 4G Turbo-V Intel FPGA IP 2.1. 4G Turbo-V IP Directory Structure You must manually install the IP from the IP installer. Figure 1. Installation Directory Structure Turbo-V-IP Encrypted Docs -- Contains the Release Document for Turbo-V-IP Proj DL_Accelerator UL_Accelerator Src altera_turbo DL_Accelerator UL_Accelerator lib (Contains the Encrypted Library packages for synthesis as well as simulation) Src DL_Accelerator UL_Accelerator Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 2. Designing with the 4G Turbo-V Intel FPGA IP 683882 | 2020.11.18 2.2. Generating a 4G Turbo-V IP You can generate a downlink or uplink accelerator. For the uplink accelerator, replace dl with ul in directory or file names. 1. Open the Intel Quartus Prime Pro software. 2. Select File New Project Wizard. 3. Click Next. 4. Enter Project name dl_fec_wrapper_top and enter the project location. 5. Select Arria 10 device. 6. Click Finish. 7. Open the dl_fec_wrapper_top.qpf file available at project directory The project wizard appears. 8. On the Platform Designer tab: a. Create the dl_fec_wrapper_top.ip file using hardware tcl file. b. Click Generate HDL to generate the design files. 9. On the Generate tab, click Generate Test bench system. 10. Click Add All to add the synthesis files to the project. The files are in src\ip\dl_fec_wrapper_top\dl_fec_wrapper_10\synth. 11. Set dl_fec_wrapper_top.v file as top level entity. 12. Click Start Compilation to compile this project. 2.3. Simulating a 4G Turbo-V IP This task is for simulating a downlink accelerator. To simulate an uplink accelerator replace dl with ul in each directory or file name. 1. Open the ModelSim 10.6d FPGA Edition simulator. 2. Change the directory to src\ip\dl_fec_wrapper_top_tb \dl_fec_wrapper_top_tb\sim\mentor 3. Change the QUARTUS_INSTALL_DIR into your Intel Quartus Prime directory in the msim_setup.tcl file, which is in \sim\mentor directory 4. Enter the command do load_sim.tcl command in transcript window. This command generates the library files and compiles and simulates the source files in the msim_setup.tcl file. The test vectors are in filename_update.sv in the \sim directory. Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 7 2. Designing with the 4G Turbo-V Intel FPGA IP 683882 | 2020.11.18 Figure 2. The filename update File Structure · Corresponding test vector files are in sim\mentor\test_vectors · Log.txt contains the result of every test packets. · For the downlink accelerator, encoder_pass_file.txt contains the pass report of every index of test packets and encoder_file_error.txt contains the fail report of every index of test packets. · For the uplink accelerator, Error_file.txt contains the fail report of every index of test packets. 4G Turbo-V Intel® FPGA IP User Guide 8 Send Feedback 683882 | 2020.11.18 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description The 4G Turbo-V Intel FPGA IP comprises a downlink accelerator and an uplink accelerator. 4G Turbo-V Architecture on page 9 4G Turbo-V Signals and Interfaces on page 11 4G Turbo-V Timing Diagrams on page 15 4G Turbo-V Latency and Throughput on page 18 3.1. 4G Turbo-V Architecture The 4G Turbo-V Intel FPGA IP comprises a downlink accelerator and an uplink accelerator. 4G Downlink Accelerator Figure 3. 4G Downlink Accelerator The 4G Turbo downlink accelerator consists of a code block CRC attachment block and a Turbo encoder (Intel Turbo FPGA IP) and rate matcher. The input data is 8-bit wide and the output data is 24-bit wide. The rate matcher consists of three subblock interleavers, a bit selector, and a bit collector. DL_FEC_ACCELERATOR LL_Rate_Matcher 8 Sub-block 8 Interleaver 8 Code Block 8 CRC Attachment Turbo 24 24 8 Sub-block 8 24 Bit Encoder Interleaver Collector 24 Bit Selector & Pruner 24 8 Sub-block 8 Interleaver The 4G downlink accelerator implements a code block CRC attachment with 8-bit parallel CRC computation algorithm. The input to the CRC attachment block is 8-bit wide. In the normal mode, the number of inputs to the CRC block is k-24, where k is the block size based on the size index. The additional CRC sequence of 24 bits is attached to the incoming code block of data in the CRC attachment block and then passes to the Turbo encoder. In the CRC bypass mode, the number of inputs is k size of 8-bit wide passed to the Turbo encoder block. Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 4. The Turbo encoder uses a parallel concatenated convolutional code. A convolutional encoder encodes an information sequence and another convolutional encoder encodes an interleaved version of the information sequence. The Turbo encoder has two 8state constituent convolutional encoders and one Turbo code internal interleaver. For more information about the Turbo encoder, refer to the Turbo IP Core User Guide. The rate matcher matches the number of bits in transport block to the number of bits that the IP transmits in that allocation. The input and output of the rate matcher is 24 bits. The IP defines the rate matching for Turbo coded transport channels for each code block. The rate matcher comprises: subblock interleaver, bit collector and bit selector. The downlink accelerator sets up the subblock interleaver for each output stream from Turbo coding. The streams include a message bit stream, 1st parity bit stream and 2nd parity bit stream. The input and output of the subblock interleaver is 24 bits wide. The bit collector combines the streams that come from the subblock interleaver. This block contains buffers that store: · Messages and filler enabling bits from the subblock interleaver. · The subblock interleaver parity bits and their respective filler bits. Bit Collector d (0) k Sub-block v (0) k Message Bit Interleaver Bit Collector d (1) k Sub-block v (1) k Interleaver 1st Parity Bit d (2) k Sub-block v (2) k Interleaver 2nd Parity Bit v (2) k v (1) k 1 . . . . . . . . . . . . . . 6144 Virtual Circular Buffer Figure 5. 4G Channel Uplink Accelerator 4G Channel Uplink Accelerator The 4G Turbo uplink accelerator consists of an subblock deinterleaver and a turbo decoder (Intel Turbo FPGA IP). Uplink FEC Accelerator Simulation Testbench 24-Bit Data Generator Sub-block De-interleaver 24-Bit Turbo Decoder Simulation 16-Bit 16-Bit Testbench Data Comparator The deinterleaver consists of three blocks in which the first two blocks are symmetrical and the third block is different. 4G Turbo-V Intel® FPGA IP User Guide 10 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 6. The latency of the ready signal is 0. Deinterleaver Sub-block De-interleaver V (0) k D0 LSB [7:0] Pk R DC subblock d (0) k 24-bit V (1) k D1 Bits [15:8] d (1) k V (2) k D2 d (2) k MSB [23:16] Concatenator 24-bit If you turn on the bypass mode for the subblock deinterleaver, the IP reads the data as it writes the data in the memory blocks in the successive locations. The IP reads the data as and when it writes the data without any interleaving. The number of input data into the subblock deinterleaver is K_ in the bypass mode and the output data length is k size (k is the code block size based on the cb_size_index value). The latency of the output data of the subblock deinterleaver depends on the input block size K_. The IP reads the data only after you write the K_ code block size of input data. Hence the latency of the output also includes the write time. The latency in the subblock interleaver output data is K_+17. The Turbo decoder calculates the most likely transmitted sequence, based on the samples that it receives. For a detailed explanation, refer to the Turbo Core IP User Guide. Decoding of error correcting codes is a comparison of the probabilities for different convolutional codes. The Turbo decoder consists of two single soft-in soft-out (SISO) decoders, which work iteratively. The output of the first (upper decoder) feeds into the second to form a Turbo decoding iteration. Interleaver and deinterleaver blocks reorder data in this process. Related Information Turbo IP Core User Guide 3.2. 4G Turbo-V Signals and Interfaces Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 11 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 7. Downlink Accelerator Downlink Accelerator Interfaces Avalon Streaming Sink sink_valid sink_data[7:0] sink_sop sink_eop sink_error[1:0] sink_ready crc_enable [0:0] cb_size_index [7:0] Input sink_rm_out_size [19:0] Configuration Conduit sink_code_blocks [14:0] sink_rv_idx [1:0] sink_rm_bypass [0:0] sink_filler_bits [5:0] TURBO V-IP DL clk reset_n soure_valid source_data [23:0] source_sop source_eop source_error[1:0] source_ready Avalon Streaming Source source_blk_size [12:0] Output Configuration Conduit Table 5. Downlink Accelerator Signals Signal Name clk Direction Bit Width Description Input 1 300 MHz clock input. All Turbo-V IP interface signals are synchronous to this clock. reset_n Input 1 Resets the internal logic of whole IP. sink_valid Input 1 Asserted when data at sink_data is valid. When sink_valid is not asserted, the IP strops processing until sink_valid is reasserted. sink_data Input 8 Typically carries the bulk of the information being transferred. sink_sop sink_eop Input 1 Input 1 Indicates the start of an incoming packet Indicates the end of an incoming packet sink_ready Sink_error Output 1 Input 2 Indicates when the IP can accept data Two-bit mask to indicate errors affecting the data transferred in the current cycle. Crc_enable Input 1 Enables the CRC block Cb_size_index Input 8 Input code block size K sink_rm_out_size Input 20 Rate matcher output block size, corresponding to E. sink_code_blocks Input 15 sink_rv_idx Input 2 Soft buffer size for current code block Ncb Redundancy version index (0,1,2 or 3) sink_rm_bypass Input 1 sink_filler_bits Input 6 Enables bypass mode in the rate matcher The number of filler bits the IP inserts at the transmitter when the IP performs code block segmentation. source_valid Output 1 Asserted by the IP when there is valid data to output. continued... 4G Turbo-V Intel® FPGA IP User Guide 12 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Signal Name Direction Bit Width Description source_data Output 24 Carries the bulk of the information transferred. This information is available where valid is asserted. source_sop Output 1 Indicates the beginning of a packet. source_eop Output 1 Indicates the end of a packet. source_ready Input 1 Data reception is valid where the ready signal is asserted. source_error Output 2 Error signal propagated from Turbo Encoder indicating Avalon-ST protocol violations on source side · 00: No error · 01: Missing start of packet · 10: Missing end of packet · 11: Unexpected end of packet Other types of errors may also be marked as 11. Source_blk_size Output 13 Output code block size K Figure 8. Uplink Accelerator Uplink Accelerator Interfaces Avalon Streaming Sink sink_valid sink_data[23:0] sink_sop sink_eop sink_error[1:0] sink_ready Input Configuration Conduit conf_valid Cb_size_index [7:0] max_iter [4:0] sel_CRC24A sink_rm_bypass conf_ready TURBO V-IP UL soure_valid source_data [15:0] source_sop source_eop source_error[1:0] source_ready Avalon Streaming Source source_blk_size [12:0] CRC_type Output Configuration CRC_pass Conduit source_iter clk reset_n Table 6. Uplink Accelerator Signals Signal clk Direction Bit Width Description Input 1 300 MHz clock input. All Turbo-V IP interface signals are synchronous to this clock. reset_n sink_valid Input 1 Input 1 Reset of input clock signal Avalon streaming input valid sink_data Input 24 Avalon streaming input data sink_sop Input 1 Avalon streaming input start of packet sink_eop Input 1 Avalon streaming input end of packet continued... Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 13 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Signal sink_ready conf_valid cb_size_index max_iteration rm_bypass sel_CRC24A conf_ready source_valid source_data source_sop source_eop source_error source_ready CRC_type Direction Bit Width Description Input 1 Avalon streaming input ready Input 1 Input configuration conduit valid Input 8 Block size iteration index Input 5 Maximum iteration Input 1 Enables bypass mode Input 1 Specifies the type of CRC that you need for the current data block: · 0: CRC24A · 1: CRC24B Input 1 Input configuration conduit ready Output 1 Avalon streaming output valid Output 16 Avalon streaming output data Output 1 Avalon streaming output start of packet Output 1 Avalon streaming output end of packet Output 2 Error signal indicating Avalon streaming protocol violations on source side: · 00: No error · 01: Missing start of packet · 10: Missing end of packet · 11: Unexpected end of packet Other types of errors may also be marked as 11. Output 1 Avalon streaming output ready Output 1 Indicates the type of CRC that was used for the current data block: · 0: CRC24A · 1: CRC24B source_blk_size Output 13 CRC_pass Output 1 source_iter Output 5 Specifies the outgoing block size Indicates whether CRC was successful: · 0: Fail · 1: Pass Shows the number of half iterations after which the Turbo decoder stops processing the current data block. 3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP Avalon streaming interfaces define a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface. The input interface is an Avalon streaming sink and the output interface is an Avalon streaming source. The Avalon streaming interface supports packet transfers with packets interleaved across multiple channels. Avalon streaming interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready, and valid signals. Avalon streaming interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels. The Avalon streaming 4G Turbo-V Intel® FPGA IP User Guide 14 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 interface inherently synchronizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic. Avalon streaming interfaces support backpressure, which is a flow control mechanism where a sink can signal to a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output. Related Information Avalon Interface Specifications 3.3. 4G Turbo-V Timing Diagrams Figure 9. Downlink Accelerator Timing Diagram for Write Logic with Codeblock 40 The IP: · Places null 20 bits in column 0 to 19 and writes the data bits from column 20. · Writes all 44 bits to memory in 6 clock cycles. · Writes trellis termination bits into column 28 to 31. · Increments write address for each row. · Generates write enable signal for 8 individual RAM at a time. The IP does not write filler bits into RAM. Instead, the IP leaves the place holder for filter bits in the RAM and inserts the NULL bits into the output during the read process. The first write starts from column 20. Clock Wr_Data Wr_Addr_RAM(0-31) Filler Bits [ 0- 19] D[0 -3] D[4-11] D[12-19] D[20-27] D[28-35] D[36-43] 0 1 Write_En_RAM(0-7) Write_En_RAM(8-15) Write_En_RAM(16-R23) Write_En_RAM(24-R31) Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 15 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 10. Timing Diagram for Read Logic with Codeblock 40 For each read, you see 8 bits in one clock cycle but only two bits are valid. The IP writes these two bits into the shift register. When the IP forms 8 bits it sends them to the output interface. Clock Rd_Addr_RAM0 Read_En_RAM0 Rd_Addr_RAM1 Read_En_RAM1 01 01 Rd_Addr_RAM31 Read_En_RAM31 01 Rd_Data Shift_Register_out Shift_Register_valid D[0-1] D[0-1] D[0-1] D[0-1] 2 bit 2 bit 2 bit 2 bit D[0-7] 8 bit D[0-1] D[0-1] D[0-1] D[0-1] 2 bit 2 bit 2 bit 2 bit D[0-7] D[0-7] 8 bit 8 bit Figure 11. Timing Diagram for Write Logic with Codeblock 6144 The filler bits are from column 0 to 27 and the data bits are from column 28. The IP: · Writes all 6,148 bits to memory in 769 clock cycles. · Writes trellis termination bits into column 28 to 31. · Increments write address for each row. · Generates write enable signal generated for 8 individual RAM at a time. The IP does not write filler bits into RAM. Instead the IP leaves the place holder for filter bits over in the RAM and inserts the NULL bits into output during the read process. The first write starts from column 28. Clock Wr_Data Wr_Addr_RAM(0-31) Write_En_RAM(0-7) Write_En_RAM(8-15) Write_En_RAM(16-R23) Write_En_RAM(24-R31) Filler Bits [ 0- 27] DD D D D [0-3] [12-19] [20-27] [28-35] [36-43] 0 1 D[6117 D[6125 D[6133 D[6141 -6124] -6132] -6140 -6148] 192 4G Turbo-V Intel® FPGA IP User Guide 16 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 12. Timing Diagram for Read Logic with Codeblock 6144 On the read side, each read gives 8 bits. While reading the 193rd row, the IP read 8 bits, but only one bit is valid. The IP forms eight bits with shift registers and sends them out by reading from the next column. Clock Rd_Addr_RAM0 01 192 Read_En_RAM0 Rd_Addr_RAM1 01 192 Read_En_RAM1 Rd_Addr_RAM31 Read_En_RAM31 Rd_Data Shift_Register_out D[0_7] D[8_15] 8 bit 8 bit D[X] D[0_7] D[8_15] D[X] 1 bit 8 bit 8 bit 1 bit D[0_7] D[8_15] 8 bit 8 bit D[X-8] D[0_7] D[8_15] 8 bit 8 bit 8 bit Uplink Accelerator Figure 13. Input Timing Diagram clk reset_n sink_data V0 V1 V2 V3 V4 sink_valid sink_sop 01 192 D[0_7] D[8_15] D[X] 8 bit 8 bit 1 bit D[X-8] D[0_7] D[8_15] D[X-8] 8 bit 8 bit 8 bit 8 bit V(Kpi-1) sink_eop sink_ready cb_size_index Index Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 17 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 14. Output Timing Diagram clk reset_n source_data C [15:0] C [31:16] C [(k-1:k-16) source_valid source_sop source_eop source_ready source_blk_size Block Size Index 3.4. 4G Turbo-V Latency and Throughput The latency is measured between input first packet SOP to output first packet SOP. The processing time is measured between input first packet SOP to output last packet EOP. Downlink accelerator The throughput is the rate at which the IP can pump the input into the downlink accelerator as it is ready. Table 7. K 6,144 Downlink Accelerator Latency, Processing Time, and Throughput With the maximum K size of 6,144 and E size of 11,522. Processing time measured for 13 code blocks. Clock speed is 300 MHz. E Latency Processing time Input Throughput (cycles) (us) (cycles) (us) (%) 11,552 3,550 11.8 14,439 48.13 95 4G Turbo-V Intel® FPGA IP User Guide 18 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 15. Latency and Processing Time Calculation The figure shows the procedure to calculate latency, processing time, and throughput. Clock Data Input to Turbo-V IP Valid SOP EOP Ready D0 D1 D2 D3 D4 D5 D6 CodeBlock 1 Throughput D7 D0 D1 D2 D3 D4 D5 D6 D7 CodeBlock 2 Clock Output of Data Turbo-V IP Valid SOP EOP Ready D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Latency CodeBlock 1 CodeBlock 2 Processing_Time Figure 16. K Size versus Latency D0 D1 D2 D3 D4 D5 D6 D7 CodeBlock 13 Latency (µs) 14 12 10 8 6 4 2 0 40 720 1408 2048 2752 3456 4096 4800 5440 6144 K Size Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 19 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Latency (µs) 40 56 72 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1088 1152 1216 1280 1312 1344 1376 1408 Figure 17. K Size versus Latency k=40 to 1408 3 2.5 2 1.5 1 0.5 0 Table 8. K 86 34,560 34,560 34,560 28,788 23,742 34,560 26,794 6,480 12,248 Table 9. K 86 34,560 34,560 34,560 28,788 K Size Uplink Accelerator Uplink Accelerator Latency and Processing Time With max iteration number = 6. Clock speed is 300 MHz. E Latency Processing time (cycles) (us) (cycles) 40 316 1.05 318 720 2,106 7.02 2,150 1,408 3,802 12.67 3,889 1,824 4,822 16.07 4,935 2,816 7,226 24.08 7,401 3,520 8,946 29.82 9,165 4,032 10,194 33.98 10,445 4,608 11,594 38.64 11,881 5,504 13,786 45.95 14,129 6,144 15,338 51.12 15,721 Uplink Accelerator Latency and Processing Time With max iteration number = 8 E Latency Processing time (cycles) (us) (cycles) 40 366 1.22 368 720 2,290 7.63 2,334 1,408 4,072 13.57 4,159 1,824 5,144 17.14 5,257 2,816 7,672 25.57 7,847 (us) 1.06 7.16 12.96 16.45 24.67 30.55 34.81 39.60 47.09 52.40 (us) 1.22 7.78 13.86 17.52 26.15 continued... 4G Turbo-V Intel® FPGA IP User Guide 20 Send Feedback 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 23,742 34,560 26,794 6,480 12,248 3,520 4,032 4,608 5,504 6,144 9,480 10,792 12,264 14,568 16,200 Figure 18. K Size vs Latency For max_iter=6 31.6 35.97 40.88 48.56 54 9,699 11,043 12,551 14,911 16,583 32.33 36.81 41.83 49.70 55.27 60 50 40 Latency (µs) 30 20 10 0 40 720 1408 1824 2816 3520 4032 4608 5504 6144 K Size Figure 19. K Size vs Processing Time For max_iter=6 Processing Time (µs) 60 50 40 30 20 10 0 40 720 1408 1824 2816 3520 4032 4608 5504 6144 K Size Send Feedback 4G Turbo-V Intel® FPGA IP User Guide 21 3. 4G Turbo-V Intel FPGA IP Functional Description 683882 | 2020.11.18 Figure 20. K Size vs Latency For max_iter=8 60 50 40 Latency (µs) 30 20 10 0 40 720 1408 1824 2816 3520 4032 4608 5504 6144 K Size Figure 21. K Size vs Processing Time For max_iter=8 Processing Time (µs) 60 50 40 30 20 10 0 40 720 1408 1824 2816 3520 4032 4608 5504 6144 K Size 4G Turbo-V Intel® FPGA IP User Guide 22 Send Feedback 683882 | 2020.11.18 Send Feedback 4. Document Revision History for the 4G Turbo-V Intel FPGA IP User Guide Date 2020.11.18 2020.06.02 IP Version 1.0.0 1.0.0 Intel Quartus Prime Software Version 20.1 20.1 Changes Removed table in 4G Turbo-V Performance and Resource Utilization Initial release. Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. 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1. About the 4G Turbo-V Intel® FPGA IP1. About the Turbo Intel® FPGA IPIntel® FPGAs and Programmable Devices-Intel® FPGA