SST25VF080B 8-Mbit SPI Serial Flash
Features
- Single Voltage Read and Write Operations: 2.7V-3.6V
- Serial Interface Architecture: SPI Compatible: Mode 0 and Mode 3
- High-Speed Clock Frequency: Up to 66 MHz
- Superior Reliability: Endurance: 100,000 Cycles (typical), Greater than 100 years Data Retention
- Low-Power Consumption: Active Read Current: 10 mA (typical), Standby Current: 5 µA (typical)
- Flexible Erase Capability: Uniform 4-Kbyte sectors, Uniform 32-Kbyte overlay blocks, Uniform 64-Kbyte overlay blocks
- Fast Erase and Byte Program: Chip Erase Time: 35 ms (typical), Sector/Block Erase Time: 18 ms (typical), Byte Program Time: 7 µs (typical)
- Auto Address Increment (AAI) Programming: Decrease total chip programming time over Byte Program operations
- End of Write Detection: Software polling the BUSY bit in STATUS Register, Busy Status readout on SO pin in AAI Mode
- Hold Pin (HOLD#): Suspends a serial sequence to the memory without deselecting the device
- Write Protection (WP#): Enables/Disables the Lock-Down function of the STATUS register
- Software Write Protection: Write protection through Block Protection bits in STATUS register
- Temperature Range: Commercial: 0°C to +70°C, Industrial: -40°C to +85°C
- All devices are RoHS compliant
Packages
- 8-lead PDIP (300 mils)
- 8-lead SOIC (200 mils)
- 8-contact WSON (6 mm x 5 mm)
- 16-ball XFBGA (Z-Scale™)
- See Figure 2-1 for pin assignments.
Description
The SST25VF080B is part of the 25 series Serial Flash family, featuring a four-wire, SPI-compatible interface. This interface allows for a low pin-count package, reducing board space and system costs. The SST25VF080B offers enhanced operating frequency and lower power consumption, manufactured using Microchip's proprietary, high-performance CMOS SuperFlash® technology. Its split-gate cell design and thick-oxide tunneling injector contribute to improved reliability and manufacturability.
The devices significantly enhance performance and reliability while lowering power consumption. They operate with a single power supply of 2.7V-3.6V. The total energy consumed is dependent on applied voltage, current, and application time. SuperFlash technology's lower current consumption for programming and shorter erase times result in less total energy consumed compared to alternative flash memory technologies.
1.0 BLOCK DIAGRAM
Figure 1-1 illustrates the Functional Block Diagram of the SST25VF080B. It comprises Address Buffers and Latches, an X-Decoder, SuperFlash Memory, a Y-Decoder, Control Logic, I/O Buffers and Data Latches, and a Serial Interface. The Serial Interface connects to pins CE#, SCK, SI, SO, WP#, and HOLD#.
2.0 PIN DESCRIPTION
Figure 2-1 shows the Pin Assignments for various packages (8-Lead PDIP, 8-Lead SOIC, 8-Contact WSON, and 16-Ball XFBGA). Table 2-1 details the function of each pin:
| Symbol | Pin Name | Functions |
|---|---|---|
| SCK | Serial Clock | Provides timing for the serial interface. Latches commands, addresses, or input data on the rising clock edge; outputs data on the falling clock edge. |
| SI | Serial Data Input | Transfers commands, addresses, or data serially. Inputs are latched on the rising edge of the serial clock. |
| SO | Serial Data Output | Transfers data serially. Data is shifted out on the falling edge of the serial clock. Can output Flash busy status (RY/BY#) during AAI Programming. |
| CE# | Chip Enable | Enables the device via a high-to-low transition. Must remain low for the duration of any command sequence. |
| WP# | Write-Protect | Enables/disables the Block Protection Lock bit (BPL) in the STATUS register. |
| HOLD# | Hold | Temporarily suspends serial communication without resetting the device. |
| VDD | Power Supply | Provides power supply voltage (2.7V-3.6V). |
| VSS | Ground | Ground connection. |
3.0 MEMORY ORGANIZATION
The SST25VF080B memory array is organized into uniform 4-Kbyte erasable sectors, 32 Kbyte overlay blocks, and 64 Kbyte overlay erasable blocks.
4.0 DEVICE OPERATION
The SST25VF080B is accessed via the SPI (Serial Peripheral Interface) bus protocol, using Chip Enable (CE#), Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The device supports SPI modes 0 (0,0) and 3 (1,1). The primary difference is the SCK signal state when the bus master is in standby mode. In Mode 0, SCK is low; in Mode 3, SCK is high. In both modes, SI is sampled on the rising SCK edge, and SO is driven after the falling SCK edge.
Figure 4-1 illustrates the SPI Protocol timing.
4.1 Hold Operation
The HOLD# pin pauses serial sequences without resetting the clock. To activate HOLD mode, CE# must be low. The mode begins when SCK is low and HOLD# falls, and ends when SCK is low and HOLD# rises. If edges don't align with SCK's low state, the device enters/exits Hold mode on the next SCK low transition. While in Hold mode, SO is high-impedance; SI and SCK can be VIL or VIH. Driving CE# high during Hold resets internal logic. HOLD# must remain low for the memory to stay in Hold. To resume, HOLD# must be driven high, and CE# driven low.
Figure 4-2 shows the Hold Condition Waveform.
4.2 Write Protection
Software write protection is provided. The WP# pin controls the lock-down function of the STATUS Register. Block Protection bits (BP3-BP0) and the BPL bit in the STATUS register protect the memory array and the register itself.
Table 4-1 outlines the conditions for executing Write STATUS Register instructions based on WP# and BPL states.
4.2.1 WRITE PROTECTION PIN (WP#)
The WP# pin enables the lock-down function of the BPL bit (bit 7) in the STATUS Register. When WP# is low, the BPL bit determines WRSR instruction execution. When WP# is high, the lock-down function is disabled.
4.3 STATUS Register
The STATUS Register provides information on memory availability for read/write operations, Write Enable status, and memory write protection status. It can be read during erase/program operations to check for completion.
Table 4-2 details the function of each bit in the STATUS Register, including BUSY (write operation in progress), WEL (Write Enable Latch), BP0-BP3 (Block Protection), AAI (Auto Address Increment Programming), and BPL (Block Protection Lock-down).
The BUSY bit (bit 0) indicates if an internal write operation is in progress. The WEL bit (bit 1) indicates if the device is Write enabled. BP0-BP3 bits (bits 2-5) indicate the level of block write protection. The AAI bit (bit 6) shows the Auto Address Increment programming status. The BPL bit (bit 7) determines if BP3-BP0 are read-only or read/writable.
The WEL bit is automatically reset on power-up, after Write Disable (WRDI), Byte Program, AAI programming completion, Sector/Block/Chip Erase, or Write STATUS Register instructions.
4.3.1 BUSY
The BUSY bit (bit 0) indicates the status of internal Erase or Program operations. '1' means busy, '0' means ready.
4.3.2 WRITE ENABLE LATCH (WEL)
The WEL bit (bit 1) reflects the status of the internal Write Enable Latch. '1' means Write enabled, '0' means not Write enabled. The WEL bit resets automatically under various conditions, including power-up, WRDI instruction, Byte Program completion, AAI programming completion, Sector/Block/Chip Erase completion, and Write STATUS Register instructions.
4.3.3 AUTO ADDRESS INCREMENT (AAI)
The AAI status bit indicates whether the device is in AAI programming mode or Byte-Program mode. The default at power-up is Byte-Program mode.
4.3.4 BLOCK PROTECTION (BP3,BP2, BP1, BP0)
These bits define memory areas protected against write (program/erase) operations. The Write STATUS Register (WRSR) instruction programs these bits when WP# is high or BPL is '0'. Chip Erase is only possible if all Block Protection bits are '0'. By default, BP3, BP2, BP1, and BP0 are set to '1' at power-up.
Table 4-3 details the software status register block protection levels and the corresponding protected memory addresses.
4.3.5 BLOCK PROTECTION LOCK-DOWN (BPL)
The WP# pin, when low, enables the BPL bit. Setting BPL to '1' prevents further changes to BPL and BP3-BP0 bits. When WP# is high, BPL has no effect. BPL resets to '0' at power-up.
4.4 Instructions
Microchip's SST25VF080B supports various instructions for reading, writing (erasing and programming), and configuring the device. These instructions use 8-bit Op Codes, addresses, and data. A Write Enable (WREN) instruction is required before any write operation (Byte Program, AAI programming, Sector Erase, Block Erase, Write STATUS Register, or Chip Erase).
Table 4-4 lists the device operation instructions, their Op Codes, and cycle counts.
Key instructions include:
- Read (03H): Reads memory up to 25 MHz. Data output is continuous until CE# goes high.
- High-Speed Read (0BH): Reads memory up to 66 MHz, requiring an 8-bit command, address, and a dummy byte.
- Byte Program (02H): Programs a single data byte. The target byte must be erased (FFH) first.
- AAI Word Program (ADH): Allows programming multiple bytes sequentially without re-issuing addresses, reducing programming time.
- Sector Erase (20H): Clears a 4-Kbyte sector.
- Block Erase (52H, D8H): Clears 32-Kbyte or 64-Kbyte blocks.
- Chip Erase (60H or C7H): Clears the entire memory array.
- Write Enable (WREN, 06H): Sets the Write Enable Latch.
- Write Disable (WRDI, 04H): Resets the Write Enable Latch.
- Read STATUS Register (RDSR, 05H): Reads the status register.
- Write STATUS Register (WRSR, 01H): Writes new values to status bits.
- JEDEC Read-ID (9FH): Identifies the device and manufacturer.
- Read-ID (RDID, 90H or ABH): Backward compatible command for device identification.
Figure 4-3 through Figure 4-19 illustrate the timing sequences for various operations like Read, High-Speed Read, Byte Program, AAI Word Program, Erase operations, Status Register access, Write Enable/Disable, and ID reads.
4.4.1 READ (25 MHZ)
The 25 MHz Read instruction (03H) outputs data sequentially from a specified address. The address pointer increments automatically. Once the highest address is reached, it wraps around to the beginning. The read operation continues until CE# transitions from low to high.
Figure 4-3 shows the Read Sequence timing.
4.4.2 HIGH-SPEED READ (66 MHZ)
The 66 MHz High-Speed Read instruction (0BH) requires an 8-bit command, address bits [A23-A0], and a dummy byte. Data output is continuous until CE# transitions from low to high. The address pointer increments and wraps around as in the standard read operation.
Figure 4-4 illustrates the High-Speed Read Sequence timing.
4.4.3 BYTE PROGRAM
The Byte Program instruction (02H) programs a single byte. The target byte must be in the erased state (FFH). Protected memory areas are ignored. A Write Enable (WREN) instruction must precede this operation. CE# must remain low during the instruction. Data is input MSb first. The user can poll the BUSY bit or wait for TBP to confirm completion. Figure 4-5 shows the Byte Program Sequence timing.
4.4.4 AUTO ADDRESS INCREMENT (AAI) WORD PROGRAM
The AAI Word Program instruction (ADH) allows programming multiple bytes without re-issuing addresses, significantly reducing programming time. It requires the target memory area to be erased. Valid instructions during AAI programming are AAI Word (ADH), WRDI (04H), and RDSR (05H) for software detection, or ADH and WRDI (04H) for hardware detection.
Completion can be determined by hardware (SO pin status), software (polling BUSY bit), or waiting for TBP. The instruction involves an 8-bit command (ADH), followed by addresses, and then data bytes (two bytes per sequence). CE# must be driven high after the instruction. Figure 4-8 and Figure 4-9 show the AAI Word programming sequences for hardware and software end-of-write detection, respectively.
4.4.5 END OF WRITE DETECTION
Three methods determine AAI Word program completion: hardware detection (Serial Output), software detection (polling BUSY bit), or waiting for TBP. The Hardware End of Write detection method is detailed below.
4.4.6 HARDWARE END OF WRITE DETECTION
This method avoids polling the BUSY bit by configuring the Serial Output (SO) pin to indicate Flash Busy status during AAI programming using command 70H. A '0' on SO means busy, '1' means ready. CE# must be asserted for status output. Only AAI Word (ADH) and WRDI (04H) are valid instructions in this mode. To exit, WRDI (04H) and then DBSY (80H) are executed.
Figure 4-6 shows enabling SO for RY/BY# status, and Figure 4-7 shows disabling it.
Figure 4-8 and Figure 4-9 illustrate the AAI Word Program sequences with hardware and software end-of-write detection.
4.4.7 4-KBYTE SECTOR ERASE
The Sector Erase instruction (20H) clears all bits in a selected 4-Kbyte sector to FFH. It is ignored if the area is protected. WREN must be executed first. CE# must remain low during the sequence. Address bits [A23-A0] are used, with [AMS-A12] determining the sector address. The user can poll the BUSY bit or wait for TSE for completion.
Figure 4-10 shows the Sector Erase Sequence timing.
4.4.8 32-KBYTE AND 64-KBYTE BLOCK ERASE
These instructions (52H for 32-Kbyte, D8H for 64-Kbyte) clear selected blocks to FFH. They are ignored if the area is protected. WREN must be executed first. CE# must remain low. Address bits [A23-A0] are used, with [AMS-A15] determining the block address. The user can poll the BUSY bit or wait for TBE for completion.
Figure 4-11 shows the 32-Kbyte Block Erase Sequence, and Figure 4-12 shows the 64-Kbyte Block Erase Sequence.
4.4.9 CHIP ERASE
The Chip Erase instruction (60H or C7H) clears all bits in the device to FFH. It is ignored if any memory area is protected. WREN must be executed first. CE# must remain low. The user can poll the BUSY bit or wait for TCE for completion.
Figure 4-13 shows the Chip Erase Sequence timing.
4.4.10 READ STATUS REGISTER (RDSR)
The RDSR instruction (05H) reads the STATUS Register, which can be done anytime, even during write operations. The BUSY bit can be checked to ensure proper command reception. CE# must be low during the instruction and remain low until data is read. The read is continuous until CE# transitions high.
Figure 4-14 shows the RDSR Sequence timing.
4.4.11 WRITE ENABLE (WREN) SEQUENCE
The WREN instruction (06H) sets the Write Enable Latch bit to '1', allowing write operations. It must be executed before any write operation and also before the WRSR instruction. CE# must be driven high after execution.
Figure 4-15 shows the WREN Sequence timing.
4.4.12 WRITE DISABLE (WRDI)
The WRDI instruction (04H) resets the Write Enable Latch and AAI bits to '0', disabling new write operations. It does not terminate ongoing programming operations. CE# must be driven high after execution.
Figure 4-16 shows the WRDI Sequence timing.
4.4.13 ENABLE WRITE STATUS REGISTER (EWSR)
The EWSR instruction arms the WRSR instruction, enabling alteration of the STATUS Register. It must be immediately followed by the WRSR instruction. This two-step sequence provides software data protection.
4.4.14 WRITE STATUS REGISTER (WRSR)
The WRSR instruction (01H) writes new values to the BP3-BP0 and BPL bits of the STATUS Register. CE# must be low during the command sequence and driven high before execution. WRSR is ignored if WP# is low and BPL is '1'. When WP# is low, BPL can only be set from '0' to '1' (lock-down), not reset. When WP# is high, BPL and BP bits are changeable.
Figure 4-17 shows sequences for EWSR/WREN and WRSR.
4.4.15 JEDEC READ-ID
The JEDEC Read-ID instruction (9FH) identifies the device as SST25VF080B and the manufacturer as Microchip. It outputs the manufacturer's ID (BFH), followed by a 16-bit device ID. Byte 2 (25H) indicates SPI Serial Flash, and Byte 3 (8EH) confirms the SST25VF080B model. The read operation terminates when CE# transitions high.
Table 4-5 lists the JEDEC Read-ID data. Figure 4-18 shows the JEDEC Read-ID Sequence timing.
4.4.16 READ-ID (RDID)
The RDID instruction (90H or ABH) is a backward-compatible command for device identification. It outputs the manufacturer's ID at address 00000H and the device ID at address 00001H. The output toggles between these addresses until CE# transitions high.
Table 4-6 provides Product Identification data. Figure 4-19 shows the Read-ID Sequence timing.
5.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
These ratings represent stress limits beyond which permanent device damage may occur. Functional operation is not implied at these levels.
- Temperature under bias: -55°C to +125°C
- Storage temperature: -65°C to +150°C
- DC voltage on any pin to ground: -0.5V to VDD+0.5V
- Transient voltage (<20 ns) on any pin to ground: -2.0V to VDD+2.0V
- Package power dissipation capability (TA = 25°C): 1.0W
- Surface mount solder reflow temperature: 260°C for 10 seconds
- Output short circuit current: 50 mA (Note 1: Output shorted for no more than one second, no more than one output at a time).
5.1 Power-Up Specifications
Functionalities and DC specifications are valid for a VDD ramp rate greater than 1V per 100 ms (0V to 3.0V in less than 300 ms).
Table 5-1 lists the Operating Range for Ambient Temperature and VDD.
Table 5-2 specifies the AC Conditions of Test (Input Rise/Fall Time, Output Load).
Table 5-3 details Recommended System Power-Up/Power-Down Timings (TPU-READ, TPU-WRITE).
Figure 5-1 illustrates the Power-Up Timing Diagram, showing VDD levels and device accessibility. Figure 5-2 shows Input/Output Reference Waveforms, and Figure 5-3 depicts a Test Load Example.
6.0 DC CHARACTERISTICS
Table 6-1 lists DC Operating Characteristics, including Read Current, Program/Erase Current, Standby Current, Input/Output Leakage Current, and Input/Output Voltage levels (VIL, VIH, VOL, VOH) under specified test conditions.
Table 6-2 provides Capacitance values (Output Pin Capacitance, Input Capacitance) measured at 25°C, 1 MHz.
Table 6-3 outlines Reliability Characteristics, including Endurance (10,000 Cycles), Data Retention (100 Years), and Latch Up.
7.0 AC CHARACTERISTICS
Table 7-1 details AC Operating Characteristics for Serial Clock Frequency, Serial Clock High/Low Times, Rise/Fall Times, CE# and HOLD# timing parameters (Setup, Hold, Active, Not Active, High-to-Low Z Output), Data In Setup/Hold Times, and Output Hold/Valid times. It also lists Erase and Program times (Sector Erase, Block Erase, Chip Erase, Byte Program).
Figure 7-1 shows the Serial Input Timing Diagram. Figure 7-2 shows the Serial Output Timing Diagram. Figure 7-3 shows the Hold Timing Diagram.
8.0 PACKAGING INFORMATION
Section 8.1 describes Package Marking Information for various packages, including PDIP, SOIC, WSON, and XFBGA. It provides examples of markings and a legend for interpretation.
Detailed package drawings and dimensions are provided for:
- 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] (Figures showing Top, Side, End views, and dimensions).
- 8-Lead Small Outline Integrated Circuit (S2AE/F) - .208 Inch Body [SOIC] (Figures showing Top, Side, End views).
- 8-Lead Very, Very Thin Small Outline No-Leads (QAE/F) - 5x6 mm Body [WSON] (Figures showing Top, Side, Bottom, Cross Section views).
- 16-bump Super-thin-profile, Fine-pitch, Ball Grid Array [XFBGA] (Figures showing Top, Side, Bottom views, and inner section details).
9.0 REVISION HISTORY
This section details the history of revisions to the datasheet, starting from the initial release in September 2005 (Revision 00) up to March 2020 (Revision D). Each revision entry lists the date, summary of changes, and updated page numbers or figures.
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This section explains how to order or obtain information for Microchip products. The PART NO. format is detailed, including codes for Device, Operating Frequency, Minimum Endurance, Temperature Range, Package, Package Modifier, Environmental Attribute, and Tape and Reel Indicator.
A table lists valid combinations for ordering various SST25VF080B configurations.
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