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Microchip 25AA256/25LC256: 256K SPI Bus Serial EEPROM

Device Selection Table

Part Number Vcc Range Page Size Temp. Ranges Packages
25LC256 2.5V-5.5V 64 Bytes I, E MF, P, SN, SM, ST
25AA256 1.8V-5.5V 64 Bytes I, E MF, P, SN, SM, ST

Features

Packages

8-Lead DFN-S, 8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ and 8-Lead TSSOP

Package Types (not to scale)

DFN-S, PDIP/SOIC, Rotated TSSOP, TSSOP

Pin Function Table

Name Function
CS Chip Select Input
SO Serial Data Output
WP Write-Protect
Vss Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
Vcc Supply Voltage

Description

The Microchip Technology Inc. 25AA256/25LC256 (25XX256) are 256-Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input.

Communication to the device can be paused via the HOLD pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts.

Note 1: 25XX256 is used in this document as a generic part number for the 25AA256/25LC256 devices.

Electrical Characteristics

Absolute Maximum Ratings (†)

† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.

DC CHARACTERISTICS

Param. No. Symbol Characteristic Minimum Maximum Units Test Conditions
D001 VIH High-Level Input Voltage 0.7 Vcc Vcc +1 V
D002 VIL Low-Level Input Voltage -0.3 0.3 Vcc V Vcc ≥ 2.5V
D003 VIL Low-Level Input Voltage -0.3 0.2 Vcc V Vcc < 2.5V
D004 VOL Low-Level Output Voltage — 0.4 V IOL = 2.1 mA, Vcc = 4.5V
D005 VOL Low-Level Output Voltage — 0.2 V IOL = 1.0 mA, Vcc = 2.5V
D006 VOH High-Level Output Voltage Vcc -0.5 — V IOH = -400 µA
D007 ILI Input Leakage Current — ±1 µA CS = Vcc, VIN = Vss or Vcc
D008 ILO Output Leakage Current — ±1 µA CS = Vcc, VOUT = Vss or Vcc
D009 CINT Internal Capacitance (All Inputs and Outputs) — 7 pF TA = 25°C, FCLK = 1.0 MHz, Vcc = 5.0V (Note 2)
D010 ICC Read Operating Current — 6 mA Vcc = 5.5V; FCLK = 10.0 MHz; SO = Open
2.5 mA Vcc = 2.5V; FCLK = 5.0 MHz; SO = Open
D011 ICC Write 5 mA Vcc = 5.5V
3 mA Vcc = 2.5V
D012 Iccs Standby Current 5 µA CS = Vcc = 5.5V, Inputs tied to Vcc or Vss, +125°C
1 µA CS = Vcc = 5.5V, Inputs tied to Vcc or Vss, +85°C

Note 1: Typical measurements taken at room temperature (+25°C).

2: This parameter is periodically sampled and not 100% tested.

AC CHARACTERISTICS

Param. No. Symbol Characteristic Minimum Maximum Units Test Conditions
1 FCLK Clock Frequency 50 — MHz 4.5V ≤ Vcc ≤ 5.5V
5 — MHz 2.5V ≤ Vcc < 4.5V
3 — MHz 1.8V ≤ Vcc < 2.5V
2 Tcss CS Setup Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V
150 — ns 2.5V ≤ Vcc < 4.5V
200 — ns 1.8V ≤ Vcc < 2.5V
3 TCSH CS Hold Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V
200 — ns 2.5V ≤ Vcc < 4.5V
250 — ns 1.8V ≤ Vcc < 2.5V
4 TCSD CS Disable Time 50 — ns 4.5V ≤ Vcc ≤ 5.5V
10 — ns 2.5V ≤ Vcc < 4.5V
5 Tsu Data Setup Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V
30 — ns 2.5V ≤ Vcc < 4.5V
40 — ns 1.8V ≤ Vcc < 2.5V
6 THD Data Hold Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V
40 — ns 2.5V ≤ Vcc < 4.5V
50 — ns 1.8V ≤ Vcc < 2.5V
7 TR CLK Rise Time 100 — ns Note 1
8 TF CLK Fall Time 100 — ns Note 1
9 THI Clock High Time 50 — ns 4.5V ≤ Vcc ≤ 5.5V
100 — ns 2.5V ≤ Vcc < 4.5V
150 — ns 1.8V ≤ Vcc < 2.5V
10 TLO Clock Low Time 50 — ns 4.5V ≤ Vcc ≤ 5.5V
100 — ns 2.5V ≤ Vcc < 4.5V
150 — ns 1.8V ≤ Vcc < 2.5V
11 TCLD Clock Delay Time 50 — ns Note 1
12 TCLE Clock Enable Time 50 — ns
13 Tv Output Valid from Clock Low 50 — ns 4.5V ≤ Vcc ≤ 5.5V
100 — ns 2.5V ≤ Vcc < 4.5V
160 — ns 1.8V ≤ Vcc < 2.5V
14 THO Output Hold Time 0 — ns Note 1
15 TDIS Output Disable Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V (Note 1)
80 — ns 2.5V ≤ Vcc ≤ 4.5V (Note 1)
160 — ns 1.8V ≤ Vcc ≤ 2.5V (Note 1)
16 THS HOLD Setup Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V
40 — ns 2.5V ≤ Vcc < 4.5V
80 — ns 1.8V ≤ Vcc < 2.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: Twc begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.

3: This parameter is not tested but ensured by characterization.

HOLD TIMING

A diagram illustrating HOLD timing is provided, showing the relationship between CS, SCK, SO, SI, and HOLD signals over time, including transitions and data states.

SERIAL INPUT TIMING

A diagram illustrating SERIAL INPUT TIMING is provided, showing the relationship between CS, SCK, SI, and SO signals during data input, including modes and data bits.

SERIAL OUTPUT TIMING

A diagram illustrating SERIAL OUTPUT TIMING is provided, showing the relationship between CS, SCK, SO, and SI signals during data output, including MSB and LSB data.

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

Name DFN-S(1) PDIP SOIC TSSOP Rotated TSSOP Function
CS 1 1 1 1 3 Chip Select Input
SO 2 2 2 2 4 Serial Data Output
WP 3 3 3 3 5 Write-Protect Pin
Vss 4 4 4 4 6 Ground
SI 5 5 5 5 7 Serial Data Input
SCK 6 6 6 6 8 Serial Clock Input
HOLD 7 7 7 7 1 Hold Input
Vcc 8 8 8 8 2 Supply Voltage

Note 1: Exposed pad on DFN-S package can be connected to Vss or left floating.

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequence being initiated.

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX256. During a read cycle, data are shifted out on this pin after the falling edge of the serial clock.

2.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX256 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high.

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data are latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication between a host and the 25XX256. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the 25XX256 while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25XX256 must remain selected during this sequence. The SI and SCK levels are "don't cares" during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to-low transition of the HOLD pin and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK.

FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25XX256 is a 32,768-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular micro controller families, including Microchip's PIC® micro-controllers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol.

The 25XX256 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation.

Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSb first, LSb last. Data (SI) are sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX256 in HOLD mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.

BLOCK DIAGRAM

A block diagram illustrates the internal components of the 25AA256/25LC256, including the HV Generator, Memory Array, Page Latches, Y Decoder, Sense Amp. R/W Control, I/O Control Logic, and STATUS Register, connected via various buses.

Instruction Name Instruction Format Description
READ 0000 0100 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WRDI 0000 0101 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0001 Read STATUS register
WRSR 0000 0011 Write STATUS register

Read Sequence

The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX256 followed by the 16-bit address, with the first MSb of the address being a "don't care" bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address are shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (7FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1).

FIGURE 3-1: READ SEQUENCE

A timing diagram illustrates the READ SEQUENCE, showing the relationship between CS, SCK, SI, and SO signals, including instruction, 16-bit address, and data out.

Write Sequence

Prior to any attempt to write data to the 25XX256, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX256. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set.

Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the first MSb of the address being a "don't care" bit and then the data to be written. Up to 64 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page.

Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or 'page size') and, end at addresses that are integer multiples of page size - 1. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the Write-In-Process (WIP) bit (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

FIGURE 3-2: BYTE WRITE SEQUENCE

A timing diagram illustrates the BYTE WRITE SEQUENCE, showing the relationship between CS, SCK, SI, and SO signals, including instruction, 16-bit address, and data byte.

FIGURE 3-3: PAGE WRITE SEQUENCE

A timing diagram illustrates the PAGE WRITE SEQUENCE, showing the relationship between CS, SCK, and SI signals over multiple data bytes.

Write Enable (WREN) and Write Disable (WRDI)

The 25XX256 contains a write enable latch. See Table 5-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch and the WRDI will reset the latch.

The following is a list of conditions under which the write enable latch will be reset:

FIGURE 3-4: WRITE ENABLE SEQUENCE (WREN)

A timing diagram illustrates the WRITE ENABLE SEQUENCE (WREN), showing the relationship between CS, SCK, SI, and SO signals.

FIGURE 3-5: WRITE DISABLE SEQUENCE (WRDI)

A timing diagram illustrates the WRITE DISABLE SEQUENCE (WRDI), showing the relationship between CS, SCK, and SI signals.

Read STATUS Register Instruction (RDSR)

The Read STATUS Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows:

7 6 5 4 3 2 1 0
W/R — W/R W/R R R R R
BP1 BP0 WEL WIP

Note 1: W/R = writable/readable. R = read-only.

The Write Enable Latch (WEL) bit indicates the STATUS of the write enable latch and is read-only. When set to a '1', the latch allows writes to the array, when set to a '0', the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands, regardless of the state of write protection on the STATUS register. These commands are shown in Figure 3-4 and Figure 3-5.

The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile and are shown in Table 3-3. See Figure 3-6 for the RDSR timing sequence.

The Write-In-Process (WIP) bit indicates whether the 25XX256 is busy with a write operation. When set to a '1', a write is in progress, when set to a '0', no write is in progress. This bit is read-only.

FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

A timing diagram illustrates the READ STATUS REGISTER TIMING SEQUENCE (RDSR), showing the relationship between CS, SCK, SI, and SO signals.

Write STATUS Register Instruction (WRSR)

The Write STATUS Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3.

The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware Write-Protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 5-1 for a matrix of functionality on the WPEN bit.

See Figure 3-7 for the WRSR timing sequence.

BP1 BP0 Array Addresses Write Protected
0 0 none
1 0 upper 1/4 (6000h-7FFFh)
0 1 upper 1/2 (4000h-7FFFh)
1 1 all (0000h-7FFFh)
FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

A timing diagram illustrates the WRITE STATUS REGISTER TIMING SEQUENCE (WRSR), showing the relationship between CS, SCK, SI, and SO signals.

DATA PROTECTION

The following protection has been implemented to prevent inadvertent writes to the array:

WEL (SR bit 1) WPEN (SR bit 7) WP pin Protected Blocks Unprotected Blocks STATUS Register
0 X X Protected Protected Protected
1 0 X Protected Writable Writable
1 1 0 (low) Protected Writable Protected
1 1 1 (high) Protected Writable Writable

Note 1: X = don't care

POWER-ON STATE

The 25XX256 powers on in the following state:

PACKAGING INFORMATION

6.1 Package Marking Information

Examples of package marking for various package types (DFN-S, PDIP, SOIC, SOIJ, TSSOP) are provided, showing the typical characters and their meaning.

The table below summarizes the 1st line marking codes for different devices and packages.

Device DFN-S PDIP SOIC SOIJ TSSOP Rotated TSSOP
25AA256 25AA256 25AA256 25AA256 25AA256 5AE 5AEX
25LC256 25LC256 25LC256 25LC256 25LC256 5LE 5LEX

Legend: XX...X Part number or part number code, T Temperature (I, E), Y Year code (last digit of calendar year), YY Year code (last 2 digits of calendar year), WW Week code (week of January 1 is week '01'), NNN Alphanumeric traceability code (2 characters for small packages), e3 RoHS-compliant JEDEC designator for Matte Tin (Sn).

Note: For very small packages with no room for the RoHS-compliant JEDEC designator (e3), the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S]

Dimensional drawings and recommended land pattern for the 8-Lead Plastic Dual Flat, No Lead Package (MF) are provided.

TOP VIEW

Top view diagram of the DFN-S package with dimensions.

SIDE VIEW

Side view diagram of the DFN-S package with dimensions.

BOTTOM VIEW

Bottom view diagram of the DFN-S package with dimensions.

A table provides the MIN, NOM, and MAX dimensions in millimeters for the DFN-S package.

Notes regarding visual index feature, tie bars, saw singulation, and dimensioning/tolerancing are included.

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Dimensional drawings and recommended land pattern for the 8-Lead Plastic Dual In-Line (P) are provided.

TOP VIEW

Top view diagram of the PDIP package with dimensions.

SIDE VIEW

Side view diagram of the PDIP package with dimensions.

END VIEW

End view diagram of the PDIP package with dimensions.

A table provides the MIN, NOM, and MAX dimensions in inches for the PDIP package.

Notes regarding visual index feature, significant characteristic, mold flash/protrusions, dimensioning/tolerancing, and lead design are included.

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Dimensional drawings and recommended land pattern for the 8-Lead Plastic Small Outline (SN) are provided.

TOP VIEW

Top view diagram of the SOIC package with dimensions.

SIDE VIEW

Side view diagram of the SOIC package with dimensions.

VIEW A-A

View A-A of the SOIC package showing lead details.

VIEW C

View C of the SOIC package showing lead angle details.

A table provides the MIN, NOM, and MAX dimensions in millimeters for the SOIC package.

Notes regarding visual index feature, significant characteristic, dimensions/tolerancing, and datums are included.

8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIJ]

Dimensional drawings and recommended land pattern for the 8-Lead Plastic Small Outline (SM) are provided.

TOP VIEW

Top view diagram of the SOIJ package with dimensions.

SIDE VIEW

Side view diagram of the SOIJ package with dimensions.

VIEW A-A

View A-A of the SOIJ package showing lead details.

A table provides the MIN, NOM, and MAX dimensions in millimeters for the SOIJ package.

Notes regarding standard designation, significant characteristic, dimensions/tolerancing, and mold flash/protrusions are included.

8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]

Dimensional drawings and recommended land pattern for the 8-Lead Plastic Thin Shrink Small Outline (ST) are provided.

TOP VIEW

Top view diagram of the TSSOP package with dimensions.

SIDE VIEW

Side view diagram of the TSSOP package with dimensions.

VIEW A-A

View A-A of the TSSOP package showing lead details.

A table provides the MIN, NOM, and MAX dimensions in millimeters for the TSSOP package.

Notes regarding visual index feature, dimensions/tolerancing, and mold flash/protrusions are included.

REVISION HISTORY

The revision history details changes made to the document across various versions, from Revision C (11/03) to Revision J (07/2021), including updates to electrical characteristics, package drawings, product ID systems, and terminology.

THE MICROCHIP WEBSITE

Microchip provides online support via its website at www.microchip.com. The website offers product support (datasheets, errata, application notes, sample programs, design resources, user's guides, hardware support documents, latest software releases, archived software), general technical support (FAQ, technical support requests, online discussion groups, consultant program member listing), and business information (product selector, ordering guides, press releases, seminar listings, sales office and distributor listings).

CUSTOMER SUPPORT

Users can receive assistance through several channels: Distributor or Representative, Local Sales Office, Field Application Engineer (FAE), and Technical Support. Technical support is also available via the website at http://microchip.com/support.

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip's customer notification service provides e-mail notifications for changes, updates, revisions, or errata related to specified product families or development tools. To register, visit www.microchip.com, navigate to "Support", click on "Customer Change Notification", and follow the registration instructions.

PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE)

This section details the product identification system for ordering and obtaining information on Microchip products. It includes tables for Part No., Device, Tape and Reel Option, Temperature Range, and Package, along with examples of part numbers.

PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE)

This section details the product identification system for automotive-grade Microchip products. It includes tables for Part No., Device, Tape and Reel Option, Temperature Range, Package, and Variant, along with examples of automotive part numbers and notes regarding the VAO/VXX variants and PPAP.


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