Microchip MCP23017/MCP23S17 16-Bit I/O Expander with Serial Interface
Datasheet for Microchip's MCP23017 (I2C) and MCP23S17 (SPI) 16-bit I/O expanders.
Features
- 16-Bit Remote Bidirectional I/O Port: I/O pins default to input
- High-Speed I2C Interface (MCP23017): 100 kHz, 400 kHz, 1.7 MHz
- High-Speed SPI Interface (MCP23S17): 10 MHz (maximum)
- Three Hardware Address Pins to Allow Up to Eight Devices On the Bus
- Configurable Interrupt Output Pins: Configurable as active-high, active-low or open-drain
- INTA and INTB Can Be Configured to Operate Independently or Together
- Configurable Interrupt Source: Interrupt-on-change from configured register defaults or pin changes
- Polarity Inversion Register to Configure the Polarity of the Input Port Data
- External Reset Input
- Low Standby Current: 1 μA (max.)
- Operating Voltage: 1.8V to 5.5V @ -40°C to +85°C; 2.7V to 5.5V @ -40°C to +85°C; 4.5V to 5.5V @ -40°C to +125°C
Packages
- 28-pin QFN, 6 x 6 mm Body
- 28-pin SOIC, Wide, 7.50 mm Body
- 28-pin SPDIP, 300 mil Body
- 28-pin SSOP, 5.30 mm Body
Functional Block Diagram
The MCP23X17 integrates an SPI interface (MCP23S17) or an I2C interface (MCP23017). Both interfaces connect to a Serializer/Deserializer, which communicates with a Control block. The Control block manages Configuration/Control Registers and interacts with the Interrupt Logic. The device features two 8-bit GPIO ports (PORTA and PORTB) connected to the Control block, providing 16-bit bidirectional I/O expansion. Control signals include CS, SCK, SI, SO for SPI, and SCL, SDA for I2C. Other control signals include A2:A0 for addressing and RESET, INTA, INTB for interrupt and reset functions.
Electrical Characteristics
Absolute Maximum Ratings
- Ambient temperature under bias: -40°C to +125°C
- Storage temperature: -65°C to +150°C
- Voltage on VDD with respect to VSS: -0.3V to +5.5V
- Voltage on all other pins with respect to VSS (except VDD): -0.6V to (VDD + 0.6V)
- Total power dissipation: 700 mW
- Maximum current out of VSS pin: 150 mA
- Maximum current into VDD pin: 125 mA
- Input clamp current (VI < 0 or VI > VDD): ±20 mA
- Output clamp current (VO < 0 or VO > VDD): ±20 mA
- Maximum output current sunk by any output pin: 25 mA
- Maximum output current sourced by any output pin: 25 mA
- ESD protection on all pins (HBM:MM): 4 kV:400V
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
| Param. No. | Characteristic | Sym. | Min. | Typ.(1) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| D001 | Supply Voltage | VDD | 1.8 | -- | 5.5 | V | -- |
| D002 | VDD Start Voltage to ensure Power-on Reset | VPOR | -- | -- | VSS | V | -- |
| D003 | VDD Rise Rate to ensure Power-on Reset | SVDD | -- | 0.05 | -- | V/ms | Design guidance only. Not tested. |
| D004 | Supply Current | IDD | -- | -- | 1 | mA | SCL/SCK = 1 MHz |
| D005 | Standby current | IDDS8 | -- | -- | 1 | μA | -40°C ≤ TA ≤ +85°C |
| -- | -- | 3 | μA | 4.5V ≤ VDD ≤ 5.5V, +85°C ≤ TA ≤+125°C (Note 1) | |||
| Input Low Voltage | |||||||
| D030 | A0, A1, A2 (TTL buffer) | VIL | VSS | -- | 0.15 VDD | V | -- |
| D031 | CS, GPIO, SCL/SCK, SDA, RESET (Schmitt Trigger) | VIL | VSS | -- | 0.2 VDD | V | -- |
| Input High Voltage | |||||||
| D040 | A0, A1, A2 (TTL buffer) | VIH | 0.25 VDD + 0.8 | -- | VDD | V | -- |
| D041 | CS, GPIO, SCL/SCK, SDA, RESET (Schmitt Trigger) | VIH | 0.8 VDD | -- | VDD | V | For entire VDD range |
| Input Leakage Current | |||||||
| D060 | I/O port pins | IIL | -- | -- | ±1 | μA | VSS ≤ VPIN ≤ VDD |
| Output Leakage Current | |||||||
| D065 | I/O port pins | ILO | -- | -- | ±1 | μA | VSS ≤ VPIN ≤ VDD |
| D070 | GPIO weak pull-up current | IPU | 40 | 75 | 115 | μA | VDD = 5V, GP pins = VSS |
| Output Low-Voltage | |||||||
| D080 | GPIO | VOL | -- | -- | 0.6 | V | IOL = 8.0 mA, VDD = 4.5V |
| INT | VOL | -- | -- | 0.6 | V | IOL = 1.6 mA, VDD = 4.5V | |
| SO, SDA | VOL | -- | -- | 0.6 | V | IOL = 3.0 mA, VDD = 1.8V | |
| SDA | VOL | -- | -- | 0.8 | V | IOL = 3.0 mA, VDD = 4.5V | |
| Output High-Voltage | |||||||
| D090 | GPIO, INT, SO | VOH | VDD - 0.7 | -- | VDD - 0.7 | V | IOH = -3.0 mA, VDD = 4.5V; IOH = -400 μA, VDD = 1.8V |
| Capacitive Loading Specs on Output Pins | |||||||
| D101 | GPIO, SO, INT | CIO | -- | -- | 50 | pF | -- |
| D102 | SDA | CB | -- | -- | 400 | pF | -- |
AC Characteristics
Load Conditions for Device Timing Specifications
The timing specifications are measured under specific load conditions. For I2C, this includes a 1 kΩ pull-up resistor (RPU) and a 135 pF load capacitance (CL) on SCL and SDA pins. For SPI, typical conditions are also provided.
Reset and Device Reset Timer Timing
Diagrams illustrate the timing for RESET pulse width (TRSTL), device active after reset high (THLD), and output high-impedance from RESET low (TIOZ).
| Param. No. | Characteristic | Sym. | Min. | Typ. (1) | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| 30 | RESET Pulse Width (Low) | TRSTL | 1 | -- | -- | μs | -- |
| 32 | Device Active After Reset high | THLD | -- | 0 | -- | ns | VDD = 5.0V |
| 34 | Output High-Impedance From RESET Low | TIOZ | -- | -- | 1 | μs | -- |
I2C Bus Timing
Timing diagrams show the START/STOP bits and data transfer sequences for I2C communication. Key parameters include Clock High Time (THIGH), Clock Low Time (TLOW), SDA and SCL Rise/Fall Times (TR, TF), START Condition Setup/Hold Times (TSU:STA, THD:STA), Data Input Hold/Setup Times (THD:DAT, TSU:DAT), Stop Condition Setup Time (TSU:STO), Output Valid From Clock (TAA), Bus Free Time (TBUF), Bus Capacitive Loading (CB), and Input Filter Spike Suppression (TSP).
| Param. No. | Characteristic | Sym. | Min. | Typ. | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| 100 | Clock High Time: | THIGH | 4.0 | -- | -- | μs | 100 kHz mode: 1.8V - 5.5V |
| 0.6 | -- | -- | μs | 400 kHz mode: 2.7V - 5.5V | |||
| 0.12 | -- | -- | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 101 | Clock Low Time: | TLOW | 4.7 | -- | -- | μs | 100 kHz mode: 1.8V - 5.5V |
| 1.3 | -- | -- | μs | 400 kHz mode: 2.7V - 5.5V | |||
| 0.32 | -- | -- | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 102 | SDA and SCL Rise Time: | TR (1) | 20 + 0.1 CB (2) | -- | 1000 | ns | 100 kHz mode: 1.8V - 5.5V |
| 20 | -- | 300 | ns | 400 kHz mode: 2.7V - 5.5V | |||
| 20 | -- | 160 | ns | 1.7 MHz mode: 4.5V - 5.5V | |||
| 103 | SDA and SCL Fall Time: | TF (1) | -- | -- | 300 | ns | 100 kHz mode: 1.8V - 5.5V |
| 20 + 0.1 CB (2) | -- | 300 | ns | 400 kHz mode: 2.7V - 5.5V | |||
| 20 | -- | 80 | ns | 1.7 MHz mode: 4.5V - 5.5V | |||
| 90 | START Condition Setup Time: | TSU:STA | 4.7 | -- | -- | μs | 100 kHz mode: 1.8V - 5.5V |
| 0.6 | -- | -- | μs | 400 kHz mode: 2.7V - 5.5V | |||
| 0.16 | -- | -- | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 91 | START Condition Hold Time: | THD:STA | 4.0 | -- | -- | μs | 100 kHz mode: 1.8V - 5.5V |
| 0.6 | -- | -- | μs | 400 kHz mode: 2.7V - 5.5V | |||
| 0.16 | -- | -- | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 106 | Data Input Hold Time: | THD:DAT | 0 | -- | 3.45 | μs | 100 kHz mode: 1.8V - 5.5V |
| 0 | -- | 0.9 | μs | 400 kHz mode: 2.7V - 5.5V | |||
| 0 | -- | 0.15 | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 107 | Data Input Setup Time: | TSU:DAT | 250 | -- | -- | ns | 100 kHz mode: 1.8V - 5.5V |
| 100 | -- | -- | ns | 400 kHz mode: 2.7V - 5.5V | |||
| 0.01 | -- | -- | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 92 | Stop Condition Setup Time: | TSU:STO | 4.0 | -- | -- | μs | 100 kHz mode: 1.8V - 5.5V |
| 0.6 | -- | -- | μs | 400 kHz mode: 2.7V - 5.5V | |||
| 0.16 | -- | -- | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 109 | Output Valid From Clock: | TAA | -- | -- | 3.45 | μs | 100 kHz mode: 1.8V - 5.5V |
| -- | -- | 0.9 | μs | 400 kHz mode: 2.7V - 5.5V | |||
| -- | -- | 0.18 | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 110 | Bus Free Time: | TBUF | 4.7 | -- | -- | μs | 100 kHz mode: 1.8V - 5.5V |
| 1.3 | -- | -- | μs | 400 kHz mode: 2.7V - 5.5V | |||
| N/A | -- | N/A | μs | 1.7 MHz mode: 4.5V - 5.5V | |||
| 111 | Bus Capacitive Loading: | CB | -- | -- | 400 | pF | 100 kHz and 400 kHz (Note 1) |
| -- | -- | 100 | pF | 1.7 MHz (Note 1) | |||
| 112 | Input Filter Spike Suppression (SDA and SCL): | TSP | -- | -- | 50 | ns | 100 kHz and 400 kHz |
| -- | -- | 10 | ns | 1.7 MHz (Spike suppression off) |
SPI Interface Timing
Timing diagrams illustrate SPI input and output operations, including Chip Select (CS), Clock (SCK), Serial Data Input (SI), and Serial Data Output (SO). Key parameters include Clock Frequency (FCLK), CS Setup/Hold Times (TCSS, TCSH), CS Disable Time (TCSD), Data Setup/Hold Times (TSU, THD), CLK Rise/Fall Times (TR, TF), Clock High/Low Times (THI, TLO), Clock Delay Time (TCLD), Clock Enable Time (TCLE), Output Valid from Clock Low (TV), Output Hold Time (THO), and Output Disable Time (TDIS).
| Param. No. | Characteristic | Sym. | Min. | Typ. | Max. | Units | Conditions |
|---|---|---|---|---|---|---|---|
| -- | Clock Frequency | FCLK | -- | 5 | -- | MHz | 1.8V – 5.5V |
| -- | 10 | -- | MHz | 2.7V – 5.5V | |||
| -- | 10 | -- | MHz | 4.5V – 5.5V | |||
| 1 | CS Setup Time | TCSS | 50 | -- | -- | ns | -- |
| 2 | CS Hold Time | TCSH | 100 | -- | -- | ns | 1.8V-5.5V |
| 50 | -- | -- | ns | 2.7V - 5.5V | |||
| 3 | CS Disable Time | TCSD | 100 | -- | -- | ns | 1.8V-5.5V |
| 50 | -- | -- | ns | 2.7V - 5.5V | |||
| 4 | Data Setup Time | TSU | 20 | -- | -- | ns | 1.8V-5.5V |
| 10 | -- | -- | ns | 2.7V - 5.5V | |||
| 5 | Data Hold Time | THD | 20 | -- | -- | ns | 1.8V-5.5V |
| 10 | -- | -- | ns | 2.7V -5.5V | |||
| 6 | CLK Rise Time | TR | -- | -- | 2 | μs | Note 1 |
| 7 | CLK Fall Time | TF | -- | -- | 2 | μs | Note 1 |
| 8 | Clock High Time | THI | 90 | -- | -- | ns | 1.8V-5.5V |
| 45 | -- | -- | ns | 2.7V - 5.5V | |||
| 9 | Clock Low Time | TLO | 90 | -- | -- | ns | 1.8V - 5.5V |
| 45 | -- | -- | ns | 2.7V - 5.5V | |||
| 10 | Clock Delay Time | TCLD | 50 | -- | -- | ns | -- |
| 11 | Clock Enable Time | TCLE | 50 | -- | -- | ns | -- |
| 12 | Output Valid from Clock Low | TV | -- | -- | 90 | ns | 1.8V-5.5V |
| -- | -- | 45 | ns | 2.7V -5.5V | |||
| 13 | Output Hold Time | THO | 0 | -- | -- | ns | -- |
| 14 | Output Disable Time | TDIS | -- | -- | 100 | ns | -- |
GPIO and INT Timing
Timing diagrams illustrate GPIO and INT pin behavior, including data capture for interrupts (INT Pin Active/Inactive) and register loading.
Pin Descriptions
The MCP23017 and MCP23S17 have 28 pins, offering bidirectional I/O, power, ground, address pins, reset, and interrupt outputs. The pin functions vary slightly based on package type (QFN, SOIC, SPDIP, SSOP).
| Pin Name | QFN | SOIC/SPDIP/SSOP | Pin Type | Function |
|---|---|---|---|---|
| GPB0-GPB7 | 25-28, 1-4 | 1-8 | I/O | Bidirectional I/O pin, configurable for interrupt-on-change and/or internal weak pull-up resistor. |
| VDD | 5 | 9 | P | Power |
| VSS | 6 | 10 | P | Ground |
| NC/CS | 7 | 11 | I | NC (MCP23017)/Chip Select (MCP23S17) |
| SCK | 8 | 12 | I | Serial clock input |
| SDA/SI | 9 | 13 | I/O | Serial data I/O (MCP23017)/Serial data input (MCP23S17) |
| NC/SO | 10 | 14 | O | NC (MCP23017)/Serial data out (MCP23S17) |
| A0, A1, A2 | 11-13 | 15-17 | I | Hardware address pins. Must be externally biased. |
| RESET | 14 | 18 | I | Hardware reset. Must be externally biased. |
| INTB | 15 | 19 | O | Interrupt output for PORTB. Configurable as active-high, active-low or open-drain. |
| INTA | 16 | 20 | O | Interrupt output for PORTA. Configurable as active-high, active-low or open-drain. |
| GPA0-GPA7 | 17-24 | 21-28 | I/O | Bidirectional I/O pin, configurable for interrupt-on-change and/or internal weak pull-up resistor. |
| EP | 29 | -- | -- | Exposed Thermal Pad. Connect to VSS or leave unconnected. |
Device Overview
The MCP23017/MCP23S17 (MCP23X17) family provides 16-bit parallel I/O expansion via I2C (MCP23017) or SPI (MCP23S17) interfaces. It features multiple 8-bit configuration registers for input/output direction, polarity, and interrupt control. The 16-bit I/O port is split into two 8-bit ports (PORTA and PORTB) and can operate in 8-bit or 16-bit modes. The device includes configurable interrupt pins (INTA, INTB) and supports interrupt-on-change functionality based on pin state changes or comparison with default values. Hardware address pins (A0-A2) allow up to eight devices on the bus.
Power-on Reset (POR)
An on-chip POR circuit holds the device in reset until VDD reaches a sufficient voltage level. Upon exiting POR, device parameters must meet operating conditions for proper function.
Serial Interface
This block manages the I2C (MCP23017) or SPI (MCP23S17) protocol. The MCP23X17 has 22 registers (11 pairs) accessible via the serial interface. The device supports Byte mode (disables address pointer increment) and Sequential mode (enables address pointer increment). Both I2C and SPI interfaces support sequential write/read operations.
| Register Name | Address (hex) IOCON.BANK = 1 | Address (hex) IOCON.BANK = 0 | Access to: |
|---|---|---|---|
| IODIRA | 00h | 00h | IODIRA |
| IODIRB | 10h | 01h | IODIRB |
| IPOLA | 01h | 02h | IPOLA |
| IPOLB | 11h | 03h | IPOLB |
| GPINTENA | 02h | 04h | GPINTENA |
| GPINTENB | 12h | 05h | GPINTENB |
| DEFVALA | 03h | 06h | DEFVALA |
| DEFVALB | 13h | 07h | DEFVALB |
| INTCONA | 04h | 08h | INTCONA |
| INTCONB | 14h | 09h | INTCONB |
| IOCON | 05h | 0Ah | IOCON |
| IOCON | 15h | 0Bh | IOCON |
| GPPUA | 06h | 0Ch | GPPUA |
| GPPUB | 16h | 0Dh | GPPUB |
| INTFA | 07h | 0Eh | INTFA |
| INTFB | 17h | 0Fh | INTFB |
| INTCAPA | 08h | 10h | INTCAPA |
| INTCAPB | 18h | 11h | INTCAPB |
| GPIOA | 09h | 12h | GPIOA |
| GPIOB | 19h | 13h | GPIOB |
| OLATA | 0Ah | 14h | OLATA |
| OLATB | 1Ah | 15h | OLATB |
Register Summary
The device features numerous registers for configuring I/O direction, polarity, interrupt behavior, pull-up resistors, and general device configuration. Key registers include IODIR (I/O Direction), IPOL (Input Polarity), GPINTEN (Interrupt Enable), DEFVAL (Default Value), INTCON (Interrupt Control), IOCON (Configuration), GPPU (Pull-up Resistor), INTF (Interrupt Flag), INTCAP (Interrupt Captured Value), GPIO (Port Register), and OLAT (Output Latch).
I/O Direction Register (IODIR)
Controls the direction of data I/O. A set bit configures the pin as an input; a clear bit configures it as an output.
Input Polarity Register (IPOL)
Allows configuration of polarity for GPIO port bits. A set bit reflects the inverted input pin state.
Interrupt-on-Change Control Register (GPINTEN)
Enables/disables interrupt-on-change for each pin. DEFVAL and INTCON registers must also be configured.
Default Value Register (DEFVAL)
Sets the compare value for pins configured for interrupt-on-change. An opposite pin level triggers an interrupt.
Interrupt Control Register (INTCON)
Controls how the pin value is compared for interrupt-on-change. A set bit compares against DEFVAL; a clear bit compares against the previous pin value.
Configuration Register (IOCON)
Contains bits for configuring the device, including BANK (register mapping), MIRROR (INT pin behavior), SEQOP (sequential operation mode), DISSLW (SDA slew rate), HAEN (hardware address enable for MCP23S17), ODR (INT pin open-drain), and INTPOL (INT pin polarity).
Pull-Up Resistor Configuration Register (GPPU)
Controls weak pull-up resistors on port pins. A set bit enables the pull-up for input pins.
Interrupt Flag Register (INTF)
Reflects interrupt conditions on pins enabled for interrupts. A set bit indicates the pin caused the interrupt. This register is read-only.
Interrupt Captured Register (INTCAP)
Captures the GPIO port value at the time of an interrupt. Read-only, updated only when an interrupt occurs.
Port Register (GPIO)
Reflects the logic level on the pins. Reading this register reads the port value. Writing modifies the Output Latch (OLAT).
Output Latch Register (OLAT)
Provides access to output latches. Writing modifies latches that drive pins configured as outputs.
Interrupt Logic
The MCP23X17 activates INTn interrupts when port pins change state or do not match a preconfigured default. Interrupts can be enabled via GPINTEN and configured via INTCON and DEFVAL. The IOCON.MIRROR bit controls whether INTA and INTB are mirrored. Interrupts can be triggered by pin changes or by mismatches with the DEFVAL register.
Interrupt Operation
INT pins can be configured as active-low, active-high, or open-drain. Only input pins with Interrupt-on-Change enabled can trigger an interrupt. Input activity captures the port value into INTCAP. The interrupt remains active until INTCAP or GPIO is read. The first interrupt event captures port contents; subsequent events are ignored until the interrupt is cleared.
Interrupt Conditions
Two primary interrupt conditions are supported:
- Interrupt-on-pin change: An interrupt occurs if a pin changes to the opposite state. The state is reset after the interrupt is cleared.
- Interrupt-on-change from register value: An interrupt occurs if an input pin differs from its corresponding register bit (DEFVAL). The condition persists until cleared by reading INTCAP or GPIO.
Packaging Information
The MCP23017/MCP23S17 are available in several package types:
- 28-Lead Plastic Quad Flat, No Lead Package (QFN): 6x6 mm body, 0.55 mm terminal length.
- 28-Lead Plastic Small Outline (SO) - Wide [SOIC]: 7.50 mm body.
- 28-Lead Skinny Plastic Dual In-Line (SPDIP): 300 mil body.
- 28-Lead Plastic Shrink Small Outline (SSOP): 5.30 mm body.
Package marking includes device number, temperature range, package type, and traceability codes. Specific dimensions and land patterns are provided for each package type.
Revision History
- Revision C (July 2016): Added ESD data, updated Table 2-1, updated package outline drawings, minor typographical errors.
- Revision B (February 2007): Changed Byte and Sequential Read in Figure 1-1 from "R" to "W", updated Table 2-4 parameters, added disclaimers, updated package drawings.
- Revision A (June 2005): Original release of this document.
Product Identification System
The part number structure indicates the device (MCP23017/MCP23S17), temperature range (E for extended), package type (ML, SO, SP, SS), and tape/reel option (T for Tape and Reel, Blank for Tube). For example, MCP23017-E/ML denotes an extended temperature MCP23017 in a QFN package.
Trademarks and Disclaimers
Microchip Technology Incorporated holds various registered trademarks and service marks, including Microchip, PIC, dsPIC, and others listed in the document. The company disclaims liability for information provided and advises users to ensure their applications meet specifications. Use in life support/safety applications is at the buyer's risk.
