Vishay IRFP460, SiHFP460 Power MOSFET

Vishay Siliconix

Product Summary

VDS (V)	500
RDS(on) (Ω)	0.27 (VGS = 10 V)
Qg (Max.) (nC)	210
Qgs (nC)	29
Qgd (nC)	110
Configuration	Single

Diagram: TO-247 package outline with N-Channel MOSFET symbol showing Drain (D), Gate (G), and Source (S) terminals.

Ordering Information

Package	Lead (Pb)-free	SnPb
TO-247	IRFP460PbF	IRFP460
	SiHFP460-E3	SiHFP460

Features

Dynamic dV/dt Rating
Repetitive Avalanche Rated
Isolated Central Mounting Hole
Fast Switching
Ease of Paralleling
Simple Drive Requirements
Lead (Pb)-free Available

Description

Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance, and cost-effectiveness. The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. The TO-247 is similar but superior to the earlier TO-218 package because of its isolated mounting hole. It also provides greater creepage distances between pins to meet the requirements of most safety specifications.

Absolute Maximum Ratings

(TC = 25 °C, unless otherwise noted)

Parameter	Symbol	Limit	Unit
Drain-Source Voltage	VDS	500	V
Gate-Source Voltage	VGS	± 20	V
Continuous Drain Current	ID	20 (VGS at 10 V, TC = 25 °C)	A
		13 (TC = 100 °C)	A
Pulsed Drain Current^a	IDM	80	A
Linear Derating Factor		2.2	W/°C
Single Pulse Avalanche Energy^b	EAS	960	mJ
Repetitive Avalanche Current^a	IAR	20	A
Repetitive Avalanche Energy^a	EAR	28	mJ
Maximum Power Dissipation	PD	280 (TC = 25 °C)	W
Peak Diode Recovery dV/dt^c	dV/dt	3.5	V/ns
Operating Junction and Storage Temperature Range	TJ, Tstg	-55 to +150	°C
Soldering Recommendations (Peak Temperature)		300^d (for 10 s)	°C
Mounting Torque		10 (6-32 or M3 screw)	lbf · in
		1.1 (6-32 or M3 screw)	N · m

Notes:
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 4.3 mH, RG = 25 Ω, IAS = 20 A (see fig. 12).
c. ISD ≤ 20 A, dI/dt ≤ 160 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply.

Thermal Resistance Ratings

Parameter	Symbol	Typ.	Max.	Unit
Maximum Junction-to-Ambient	RthJA	-	40	°C/W
Case-to-Sink, Flat, Greased Surface	RthCS	0.24	-	°C/W
Maximum Junction-to-Case (Drain)	RthJC	-	0.45	°C/W

Specifications

(TJ = 25 °C, unless otherwise noted)

Static

Parameter	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
Drain-Source Breakdown Voltage	VDS	VGS = 0 V, ID = 250 µA	500	-	-	V
VDS Temperature Coefficient	ΔVDS/TJ	Reference to 25 °C, ID = 1 mA	-	0.63	-	V/°C
Gate-Source Threshold Voltage	VGS(th)	VDS = VGS, ID = 250 µA	2.0	-	4.0	V
Gate-Source Leakage	IGSS	VGS = ± 20 V	-	-	± 100	nA
Zero Gate Voltage Drain Current	IDSS	VDS = 500 V, VGS = 0 V	-	-	25	µA
		VDS = 400 V, VGS = 0 V, TJ = 125 °C	-	-	250	µA
Drain-Source On-State Resistance	RDS(on)	VGS = 10 V, ID = 12 A^a	-	-	0.27	Ω
Forward Transconductance	gfs	VDS = 50 V, ID = 12 A^a	-	13	-	S

Dynamic

Parameter	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
Input Capacitance	Ciss	VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5	-	4200	-	pF
Output Capacitance	Coss		-	870	-
Reverse Transfer Capacitance	Crss		-	350	-
Total Gate Charge	Qg	VGS = 10 V, ID = 20 A, VDS = 400 V, see fig. 6 and 13^b	-	210	-	nC
Gate-Source Charge	Qgs		-	29	-
Gate-Drain Charge	Qgd		-	110	-
Turn-On Delay Time	td(on)	VDD = 250 V, ID = 20 A, RG = 4.3 Ω, RD = 13 Ω, see fig. 10^b	-	18	-	ns
Rise Time	tr		-	59	-
Turn-Off Delay Time	td(off)		-	110	-
Fall Time	tf		-	58	-
Internal Drain Inductance	LD	Between lead, 6 mm (0.25") from package and center of die contact	-	5.0	-	nH
Internal Source Inductance	LS	Between lead, 6 mm (0.25") from package and center of die contact	-	13	-	nH

Drain-Source Body Diode Characteristics

Parameter	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
Continuous Source-Drain Diode Current	IS	MOSFET symbol showing the integral reverse p-n junction diode	-	-	20	A
Pulsed Diode Forward Current^a	ISM	MOSFET symbol showing the integral reverse p-n junction diode	-	-	80	A
Body Diode Voltage	VSD	TJ = 25 °C, IS = 20 A, VGS = 0 V^b	-	1.8	-	V
Body Diode Reverse Recovery Time	trr	TJ = 25 °C, IF = 20A, dI/dt = 100 A/µs^b	-	570	860	ns
Body Diode Reverse Recovery Charge	Qrr	TJ = 25 °C, IF = 20A, dI/dt = 100 A/µs^b	-	5.7	8.6	µC
Forward Turn-On Time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)	-	-	-

Notes:
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2%.

Typical Characteristics

(25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Graph showing Drain Current (ID) vs. Drain-to-Source Voltage (VDS) for various Gate-Source Voltages (VGS) from 4.5V to 15V, measured with a 20 µs pulse width at TC = 25 °C.

Fig. 2 - Typical Output Characteristics, TC = 150 °C

Graph showing Drain Current (ID) vs. Drain-to-Source Voltage (VDS) for various Gate-Source Voltages (VGS) from 4.5V to 15V, measured with a 20 µs pulse width at TC = 150 °C.

Fig. 3 - Typical Transfer Characteristics

Graph showing Drain Current (ID) vs. Gate-to-Source Voltage (VGS) for VDS = 50 V, measured with a 20 µs pulse width at 25 °C and 150 °C.

Fig. 4 - Normalized On-Resistance vs. Temperature

Graph showing Normalized Drain-to-Source On-Resistance (RDS(on)) vs. Junction Temperature (TJ) for ID = 20 A and VGS = 10 V.

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Graph showing Capacitance (Ciss, Coss, Crss) in pF vs. Drain-to-Source Voltage (VDS) in Volts, measured at VGS = 0 V and f = 1 MHz.

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Graph showing Total Gate Charge (Qg) in nC vs. Gate-to-Source Voltage (VGS) in Volts, for ID = 20 A and VDS = 400 V, also showing Qgs and Qgd components. Test circuit shown in Figure 13.

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Graph showing Source-Drain Diode Forward Voltage (VSD) vs. Reverse Drain Current (ISD), measured at TJ = 25 °C, IS = 20 A, VGS = 0 V.

Fig. 8 - Maximum Safe Operating Area

Graph showing Drain Current (ID) vs. Drain-to-Source Voltage (VDS) for various pulse durations (10 µs, 100 µs, 1 ms, 10 ms, Single Pulse) and temperatures (25 °C, 150 °C), indicating the safe operating region limited by RDS(on).

Fig. 9 - Maximum Drain Current vs. Case Temperature

Graph showing Maximum Drain Current (ID) vs. Case Temperature (TC) in °C.

Fig. 10a - Switching Time Test Circuit

Circuit diagram for switching time measurements, showing VDS, VGS, RG, RD, DUT (Device Under Test), and VDD. Includes parameters like pulse width and duty factor.

Fig. 10b - Switching Time Waveforms

Waveforms illustrating switching times: VGS (90% to 10%) and VDS, showing Turn-On Delay Time (td(on)), Rise Time (tr), Turn-Off Delay Time (td(off)), and Fall Time (tf).

Fig. 11a - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Graph showing Thermal Response (ZthJC) vs. Rectangular Pulse Duration (t1), with notes on Duty Factor and Peak TJ calculation.

Fig. 12a - Unclamped Inductive Test Circuit

Circuit diagram for unclamped inductive load testing, showing VDS, VGS, RG, L, DUT, VDD, and IAS. Includes a note on varying tp to obtain required IAS.

Fig. 12b - Unclamped Inductive Waveforms

Waveforms illustrating unclamped inductive switching, showing VDS and IAS over time (tp).

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Graph showing EAS (Single Pulse Energy) in mJ vs. Starting TJ (Junction Temperature) in °C, for different Drain Currents (ID) and VDD = 50 V.

Fig. 13a - Basic Gate Charge Waveform

Diagram illustrating the gate charge process, showing VG, QGS, QGD, and Charge over time.

Fig. 13b - Gate Charge Test Circuit

Circuit diagram for gate charge testing, including a current regulator, capacitors, resistors, VGS, VDS, IG, and ID measurements.

Fig. 14 - For N-Channel Peak Diode Recovery dV/dt Test Circuit

Circuit diagram for Peak Diode Recovery dV/dt testing, showing test circuit considerations (stray inductance, ground plane, leakage inductance), driver type, and control parameters. Includes waveforms for driver gate drive, ISD, VDS, and inductor current.

Package Information

The following tables detail the package dimensions for the TO-247AC (High Voltage) package, with different facility codes.

Version 1: Facility Code = 9 (TO-247AC High Voltage)

Diagram: Shows the TO-247AC package outline with dimensions labeled A, A1, A2, b, b1, b2, b3, b4, b5, c, c1, D, D1, D2, E, E1, E2, e, L, L1, P, P1, Q, S. Includes sections for detailed views.

DIM.	MILLIMETERS		NOTES
	MIN.	MAX.
A	4.83	5.21
A1	2.29	2.55
A2	1.50	2.49
b	1.12	1.33
b1	1.12	1.28
b2	1.91	2.39	6
b3	1.91	2.34
b4	2.87	3.22	6, 8
b5	2.87	3.18
c	0.55	0.69	6
c1	0.55	0.65
D	20.40	20.70	4
D1	16.25	16.85	5
D2	0.56	0.76
E	15.50	15.87	4
E1	13.46	14.16	5
E2	4.52	5.49	3
e	5.44 BSC
L	14.90	15.40
L1	3.96	4.16	6
Ø P	3.56	3.65	7
Ø P1	7.19 ref.
Q	5.31	5.69
S	5.54	5.74

Notes: (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition

Version 2: Facility Code = Y

Diagram: Shows the TO-247 package outline with dimensions labeled A, A1, A2, b, b1, b2, b3, b4, b5, c, c1, D, D1, D2, E, E1, e, k, L, L1, P, P1, Q, R, S. Includes lead assignments and detailed views.

DIM.	MILLIMETERS
	MIN.	MAX.
A	4.58	5.31
A1	2.21	2.59
A2	1.17	2.49
b	0.99	1.40
b1	0.99	1.35
b2	1.53	2.39
b3	1.65	2.37
b4	2.42	3.43
b5	2.59	3.38
c	0.38	0.86
c1	0.38	0.76
D	19.71	20.82
D1	13.08	-
D2	0.51	1.30
E	15.29	15.87
E1	13.72	-
e	5.46 BSC
k	0.254
L	14.20	16.25
L1	3.71	4.29
Ø P	3.51	3.66
Ø P1	7.39
Q	5.31	5.69
R	4.52	5.49
S	5.51 BSC

Notes: (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c

Version 3: Facility Code = N

Diagram: Shows the TO-247 package outline with dimensions labeled A, A1, A2, b, b1, b2, b3, b4, b5, c, c1, D, D1, D2, E, E1, e, k, L, L1, N, P, P1, Q, R, S. Includes base metal and plating views.

DIM.	MILLIMETERS
	MIN.	MAX.
A	4.65	5.31
A1	2.21	2.59
A2	1.17	1.37
b	0.99	1.40
b1	0.99	1.35
b2	1.65	2.39
b3	1.65	2.34
b4	2.59	3.43
b5	2.59	3.38
c	0.38	0.89
c1	0.38	0.84
D	19.71	20.70
D1	13.08	-
D2	0.51	1.35
E	15.29	15.87
E1	13.46	-
e	5.46 BSC
k	0.254
L	14.20	16.10
L1	3.71	4.29
N	7.62 BSC
P	3.56	3.66
P1	7.39
Q	5.31	5.69
R	4.52	5.49
S	5.51 BSC

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Revision: 09-Jul-2021

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