Vishay IRFP27N60K Power MOSFET

Vishay Siliconix

Product Summary

Parameter	Value
VDS (V)	600
RDS(on) (Ω)	0.18 (VGS = 10 V)
Qg (max.) (nC)	180
Qgs (nC)	56
Qgd (nC)	86
Configuration	Single

Features

Low gate charge Qg results in simple drive requirement
Improved gate, avalanche and dynamic dV/dt ruggedness
Fully characterized capacitance and avalanche voltage and current
Enhanced body diode dV/dt capability
Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Applications

Hard switching primary or PFC switch
Switch mode power supply (SMPS)
Uninterruptible power supply
High speed power switching
Motor drive

Ordering Information

Package	Lead (Pb)-free
TO-247AC	IRFP27N60KPbF

Absolute Maximum Ratings

Parameter	Symbol	Limit	Unit
Drain-source voltage	VDS	600	V
Gate-source voltage	VGS	± 30	V
Continuous drain current	ID	27 (Tc = 25 °C), 18 (Tc = 100 °C)	A
Pulsed drain Current	IDM	110	A
Linear derating Factor		4.0	W/°C
Single pulse avalanche energy	EAS	530	mJ
Repetitive avalanche current	IAR	27	A
Repetitive avalanche energy	EAR	50	mJ
Maximum power dissipation	PD	500 (Tc = 25 °C)	W
Peak diode recovery dV/dt	dV/dt	13 (c)	V/ns
Operating junction and storage temperature range	TJ, Tstg	-55 to +150	°C
Soldering recommendations (peak temperature)		300d (for 10 s)
Mounting torque		1.1 (6-32 or M3 screw)	N·m

Thermal Resistance Ratings

Parameter	Symbol	Typ.	Max.	Unit
Maximum junction-to-ambient	RthJA	-	40	°C/W
Case-to-sink, flat, greased surface	RthCS	0.24	-	°C/W
Maximum junction-to-case (drain)	RthJC	-	0.29	°C/W

Specifications

Parameter	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
Static
Drain-source breakdown voltage	VDS	VGS = 0 V, ID = 250 μA	600	-	-	V
VDS temperature coefficient	AVDS/TJ	Reference to 25 °C, ID = 1 mA	-	640	-	mV/°C
Gate-source threshold voltage	VGS(th)	VDS = VGS, ID = 250 μA	3.0	-	5.0	V
Gate-source leakage	IGSS	VGS = ± 30 V	-	-	± 100	nA
Zero gate voltage drain current	IDSS	VDS = 600 V, VGS = 0 V	-	-	50	μA
		VDS = 480 V, VGS = 0 V, TJ = 125 °C	-	-	250	μA
Drain-source on-state resistance	RDS(on)	VGS = 10 V, ID = 16 A b	-	0.18	0.22	Ω
Forward transconductance	gfs	VDS = 50 V, ID = 16 A	14	-	-	S
Dynamic
Input capacitance	Ciss	VGS = 0 V	-	4660	-	pF
Output capacitance	Coss	VDS = 25 V	-	460	-	pF
Reverse transfer capacitance	Crss	f = 1.0 MHz, see fig. 5	-	41	-	pF
Output capacitance	Coss	VGS = 0 V, VDS = 1.0 V, f = 1.0 MHz	-	5490	-	pF
Effective output capacitance	Coss eff.	VGS = 0 V, VDS = 0 V to 480 V	-	120	-	pF
Total gate charge	Qg	VGS = 10 V, ID = 27 A, VDS = 480 V, see fig. 6 and 13 b	-	180	-	nC
Gate-source charge	Qgs		-	56	-	nC
Gate-drain charge	Qgd		-	86	-	nC
Turn-on delay time	td(on)	VDD = 300 V, ID = 27 A, Rg = 4.3 Ω, VGS = 10 V, see fig. 10 b	-	27	-	ns
Rise time	tr		-	110	-	ns
Turn-off delay time	td(off)		-	43	-	ns
Fall time	tf		-	38	-	ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current	Is		-	27	-	A
Pulsed diode forward current	ISM		-	110	-	A
Body diode voltage	VSD	TJ = 25 °C, Is = 27 A, VGS = 0 V b	-	1.5	-	V
Body diode reverse recovery time	trr		-	620	920	ns
Body diode reverse recovery charge	Qrr	TJ = 25 °C, IF = 27 A, dI/dt = 100 A/μs b	-	11	-	nC
Reverse recovery current	IRRM		-	36	53	A
Forward turn-on time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)	-	-	-

Typical Characteristics

The following figures illustrate typical performance characteristics of the IRFP27N60K MOSFET.

Figure 1: Typical Output Characteristics: Plots Drain-to-Source Current (ID) vs. Drain-to-Source Voltage (VDS) for various Gate-to-Source Voltages (VGS) at Tj = 25°C with a 20µs pulse width.
Figure 2: Typical Output Characteristics: Plots Drain-to-Source Current (ID) vs. Drain-to-Source Voltage (VDS) for various Gate-to-Source Voltages (VGS) at Tj = 150°C with a 20µs pulse width.
Figure 3: Typical Transfer Characteristics: Plots Drain-to-Source Current (ID) vs. Gate-to-Source Voltage (VGS) at VDS = 100V for Tj = 25°C and Tj = 150°C with a 20µs pulse width.
Figure 4: Normalized On-Resistance vs. Temperature: Plots Normalized Drain-to-Source On-Resistance (RDS(on)) vs. Junction Temperature (TJ) for specific conditions (VGS = 10V, ID = 28A).
Figure 5: Typical Capacitance vs. Drain-to-Source Voltage: Plots Capacitance (C) in pF vs. Drain-to-Source Voltage (VDS) for Ciss, Coss, and Crss, measured at f = 1 MHz with VGS = 0V.
Figure 6: Typical Gate Charge vs. Gate-to-Source Voltage: Plots Gate-to-Source Voltage (VGS) vs. Total Gate Charge (Qg) for different VDS and ID values.
Figure 7: Typical Source-Drain Diode Forward Voltage: Plots Source-Drain Diode Forward Current (ISD) vs. Source-to-Drain Voltage (VSD) for Tj = 25°C and Tj = 150°C with VGS = 0V.
Figure 8: Maximum Safe Operating Area: Plots Drain-to-Source Current (ID) vs. Drain-to-Source Voltage (VDS) for different pulse durations (100µs, 1msec, 10msec) and temperatures (Tc = 25°C, Tj = 150°C), indicating areas limited by RDS(on).
Figure 9: Maximum Drain Current vs. Case Temperature: Plots Drain Current (ID) vs. Case Temperature (TC).
Figure 10: Switching Time Test Circuit: A schematic diagram illustrating the test circuit for switching times, showing VDS, VGS, RG, RD, L, and the Device Under Test (D.U.T.).
Figure 11: Switching Time Waveforms: Diagrams illustrating the voltage and current waveforms during switching, showing turn-on delay (td(on)), rise time (tr), turn-off delay (td(off)), and fall time (tf).
Figure 12: Maximum Effective Transient Thermal Impedance, Junction-to-Case: Plots Thermal Response (ZthJC) vs. Rectangular Pulse Duration (t1) for various duty factors and single pulse conditions.
Figure 13: Unclamped Inductive Test Circuit: A schematic diagram illustrating the test circuit for unclamped inductive switching, showing VDD, L, RG, D.U.T., IAS, and VGS.
Figure 14: Unclamped Inductive Waveforms: Diagrams illustrating voltage and current waveforms during unclamped inductive switching.
Figure 15: Maximum Avalanche Energy vs. Drain Current: Plots Single Pulse Avalanche Energy (EAS) vs. Starting Junction Temperature (Tj) for different Drain Current (ID) values.
Figure 16: Basic Gate Charge Waveform: A conceptual diagram showing the charge components (Qgs, Qgd) during gate charge.
Figure 17: Gate Charge Test Circuit: A schematic diagram illustrating the test circuit for gate charge measurements.
Figure 18: For N-Channel: Illustrates the Peak Diode Recovery dV/dt Test Circuit and associated waveforms, including circuit layout considerations and driver gate drive signals.

Package Information

The IRFP27N60K is available in the TO-247AC package. Dimensions and lead assignments are provided for different facility codes (versions).

TO-247AC (High Voltage) - Version 1: Facility Code = 9

Diagram Description: A technical drawing of the TO-247AC package showing its outline, lead positions, and key dimensions. It includes views from different angles and cross-sections.

MILLIMETERS				MILLIMETERS
DIM.	MIN.	NOM.	MAX.	NOTES	DIM.	MIN.	NOM.	MAX.	NOTES
A	4.83	5.02	5.21		D1	16.46	16.76	17.06	5
A1	2.29	2.41	2.55		D2	0.56	0.66	0.76
A2	1.17	1.27	1.37		E	15.50	15.70	15.87	4
b	1.12	1.20	1.33		E1	13.46	14.02	14.16	5
b1	1.12	1.20	1.28		E2	4.52	4.91	5.49	3
b2	1.91	2.00	2.39	6	e		5.46 BSC
b3	1.91	2.00	2.34		L	14.90	15.15	15.40
b4	2.87	3.00	3.22	6, 8	L1	3.96	4.06	4.16	6
b5	2.87	3.00	3.18		Ø P	3.56	3.61	3.65	7
c	0.40	0.50	0.60	6	Ø P1		7.19 ref.
c1	0.40	0.50	0.56		Q	5.31	5.50	5.69
D	20.40	20.55	20.70	4	S		5.51 BSC

Notes: (1) Package reference: JEDEC® TO247, variation AC. (2) All dimensions are in mm. (3) Slot required, notch may be rounded. (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body. (5) Thermal pad contour optional with dimensions D1 and E1. (6) Lead finish uncontrolled in L1. (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm. (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition.

TO-247AC (High Voltage) - Version 2: Facility Code = Y

Diagram Description: A technical drawing of the TO-247AC package, similar to Version 1, showing outline, lead assignments, and dimensions. Includes views A-A, B, and cross-sections.

MILLIMETERS				MILLIMETERS
DIM.	MIN.	MAX.	NOTES	DIM.	MIN.	MAX.	NOTES
A	4.58	5.31		D2	0.51	1.30
A1	2.21	2.59		E	15.29	15.87
A2	1.17	2.49		E1	13.72	-
b	0.99	1.40		e		5.46 BSC
b1	0.99	1.35		Ø k		0.254
b2	1.53	2.39		L	14.20	16.25
b3	1.65	2.37		L1	3.71	4.29
b4	2.42	3.43		Ø P	3.51	3.66
b5	2.59	3.38		Ø P1	-	7.39
c	0.38	0.86		Q	5.31	5.69
c1	0.38	0.76		R	4.52	5.49
D	19.71	20.82		S		5.51 BSC
D1	13.08	-

Notes: (1) Dimensioning and tolerancing per ASME Y14.5M-1994. (2) Contour of slot optional. (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. (4) Thermal pad contour optional with dimensions D1 and E1. (5) Lead finish uncontrolled in L1. (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c.

TO-247AC (High Voltage) - Version 3: Facility Code = N

Diagram Description: A technical drawing of the TO-247AC package, similar to previous versions, showing outline, lead assignments, and dimensions. Includes views A-A, B, and cross-sections.

MILLIMETERS				MILLIMETERS
DIM.	MIN.	MAX.	NOTES	DIM.	MIN.	MAX.	NOTES
A	4.65	5.31		D2	0.51	1.35
A1	2.21	2.59		E	15.29	15.87
A2	1.17	1.37		E1	13.46	-
b	0.99	1.40		e		5.46 BSC
b1	0.99	1.35		k		0.254
b2	1.65	2.39		L	14.20	16.10
b3	1.65	2.34		L1	3.71	4.29
b4	2.59	3.43		N		7.62 BSC
b5	2.59	3.38		P	3.56	3.66
c	0.38	0.89		P1	-	7.39
c1	0.38	0.84		Q	5.31	5.69
D	19.71	20.70		R	4.52	5.49
D1	13.08	-		S		5.51 BSC

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