SiHF18N50D D Series Power MOSFET

Product Summary

VDS (V) at Tj max.: 550 V

RDS(on) max. (Ω) at 25 °C: 0.28 Ω (VGS = 10 V)

Qg max. (nC): 76 nC

Qgs (nC): 11 nC

Qgd (nC): 17 nC

Configuration: Single

Ordering Information

Package: TO-220 FULLPAK

Lead (Pb)-free: SiHF18N50D-E3

Features

• Optimal design: Low area specific on-resistance, Low input capacitance (Ciss), Reduced capacitive switching losses, High body diode ruggedness, Avalanche energy rated (UIS).
• Optimal efficiency and operation: Low cost, Simple gate drive circuitry, Low figure-of-merit (FOM): Ron x Qg, Fast switching.

Applications

• Consumer electronics (Displays: LCD or Plasma TV)
• Server and telecom power supplies (SMPS)
• Industrial (Welding, Induction heating, Motor drives)
• Battery chargers

Absolute Maximum Ratings

Notes:

• a. Repetitive rating; pulse width limited by maximum junction temperature.
• b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, RG = 25 Ω, IAS = 10 A.
• c. 1.6 mm from case.
• d. ISD ≤ ID, starting TJ = 25 °C.
• e. Limited by maximum junction temperature.

Thermal Resistance Ratings

Specifications (TJ = 25 °C, unless otherwise noted)

Static

Dynamic

Drain-Source Body Diode Characteristics

Notes:

• a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0% to 80% VDSS.
• b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0% to 80% VDSS.

Typical Characteristics (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics: Graphs illustrating Drain-to-Source Current (ID) versus Drain-to-Source Voltage (VDS) for various fixed Gate-to-Source Voltages (VGS) at Tj = 25 °C.

Fig. 2 - Typical Output Characteristics: Graphs illustrating Drain-to-Source Current (ID) versus Drain-to-Source Voltage (VDS) for various fixed Gate-to-Source Voltages (VGS) at Tj = 150 °C.

Fig. 3 - Typical Transfer Characteristics: Graph showing Drain-to-Source Current (ID) versus Gate-to-Source Voltage (VGS) at Tj = 150 °C and Tj = 25 °C.

Fig. 4 - Normalized On-Resistance vs. Temperature: Graph displaying the normalized Drain-to-Source On-Resistance (RDS(on)) as a function of Junction Temperature (TJ), for specific ID and VGS conditions.

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage: Graphs showing various capacitances (Ciss, Coss, Crss) in picofarads (pF) plotted against Drain-to-Source Voltage (VDS) at VGS = 0 V and f = 1.0 MHz.

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage: Graph illustrating Total Gate Charge (Qg) in nanocoulombs (nC) versus Gate-to-Source Voltage (VGS) for specific VDS and ID conditions, with breakdown for different VDS values.

Fig. 7 - Typical Source-Drain Diode Forward Voltage: Graph showing Reverse Drain Current (ISD) versus Source-Drain Voltage (VSD) for the internal body diode at different junction temperatures (Tj = 25°C and Tj = 150°C).

Fig. 8 - Maximum Safe Operating Area: A chart defining the safe operating area (SOA) for the MOSFET, plotting Drain Current (ID) against Drain-to-Source Voltage (VDS) under various conditions such as continuous operation, pulsed operation, and thermal limits.

Fig. 9 - Maximum Drain Current vs. Case Temperature: Graph showing the maximum continuous Drain Current (ID) that can be handled versus Case Temperature (TJ).

Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature: Graph illustrating the typical Drain-to-Source Breakdown Voltage (VDS) as a function of Junction Temperature (TJ).

Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case: Graph showing the normalized junction-to-case thermal transient impedance as a function of pulse time, for various duty cycles and single pulse conditions.

Test Circuits and Waveforms

Fig. 12 - Switching Time Test Circuit: Schematic of a test circuit used to measure switching times, including components like VGS pulse generator, RG, RD, and the Device Under Test (DUT).

Fig. 13 - Switching Time Waveforms: Diagram illustrating voltage and current waveforms during switching, showing key timing parameters: turn-on delay (td(on)), rise time (tr), turn-off delay (td(off)), and fall time (tf).

Fig. 14 - Unclamped Inductive Test Circuit: Schematic of a test circuit for evaluating performance under unclamped inductive load conditions, featuring a voltage source (VDD), DUT, inductor (L), and gate resistor (RG).

Fig. 15 - Unclamped Inductive Waveforms: Diagram showing voltage (VDS) and current (IAS) waveforms during unclamped inductive switching, illustrating the pulse duration (tp).

Fig. 16 - Basic Gate Charge Waveform: Simplified graph showing the relationship between Gate-Source Voltage (VGS) and charge, indicating the components of gate charge (QGS, QGD).

Fig. 17 - Gate Charge Test Circuit: Schematic of a test circuit designed to measure gate charge, incorporating a current regulator, DUT, and current sampling resistors.

Fig. 18 - For N-Channel Peak Diode Recovery dV/dt Test Circuit: Schematic of a test circuit for measuring peak diode recovery dV/dt, detailing circuit layout considerations and test parameters.

Waveforms for Fig. 18: Diagrams showing various waveforms during diode recovery testing: Driver gate drive (VGS), DUT ISD waveform (reverse recovery current, body diode forward current), and DUT VDS waveform (diode recovery dV/dt, re-applied voltage).

Package Information

TO-220 FULLPAK (High Voltage)

Option 1: Facility Code = 9

Diagram Description: Diagram showing the TO-220 FULLPAK package outline with dimensions labeled A, b, b1, b2, C, D, e (lead pitch), E, F, G, L, L1, Q, Q1, and ØR. It includes top, side, and bottom views, indicating features like mold flash bleeding and exposed copper.

Notes:

• 1. To be used only for process drawing.
• 2. These dimensions apply to all TO-220 FULLPAK leadframe versions (3 leads).
• 3. All critical dimensions should meet Cpk > 1.33.
• 4. All dimensions include burrs and plating thickness.
• 5. No chipping or package damage.
• 6. Facility code will be the 1st character located at the 2nd row of the unit marking.

Option 2: Facility Code = Y

Diagram Description: Diagram showing the TO-220 FULLPAK package outline with dimensions labeled A, A1, A2, b, b2, b3, c, D, d1, d3, E, e, L, L1, n, ØP, u, V. It includes top, side, and bottom views, indicating features like mold flash bleeding and exposed copper.

Notes:

• 1. To be used only for process drawing.
• 2. These dimensions apply to all TO-220 FULLPAK leadframe versions (3 leads).
• 3. All critical dimensions should meet Cpk > 1.33.
• 4. All dimensions include burrs and plating thickness.
• 5. No chipping or package damage.
• 6. Facility code will be the 1st character located at the 2nd row of the unit marking.

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