Netlist Viewer User Guide

Libero SoC v2024.2

Introduction

As Field Programmable Gate Array (FPGA) designs grow in size and complexity, it has become essential for FPGA designers to traverse the netlist to analyze their designs. The Microchip Netlist Viewer is a graphical representation of the design netlist that displays different views for the different stages of the design process.

1. Supported Families and Platforms

The Netlist Viewer supports SmartFusion® 2, IGLOO® 2, RTG4™, PolarFire®, and PolarFire SoC family devices and runs on Windows® and Linux® systems.

Important: Depending on the device selected, some user interface elements such as icons, options, tabs, and dialog boxes may vary slightly in appearance and/or content. Basic Netlist Viewer functionality remains the same, regardless of the device chosen. In this user guide, a PolarFire device is used in the example figures.

2. Views

The Netlist Viewer is a Graphical User Interface (GUI) that displays different views for the different stages of the design process:

Figure 2-1. Netlist Viewer—RTL View

Figure 2-2. Netlist Viewer—Hierarchical Post-Synthesis View

Figure 2-3. Netlist Viewer—Flat Post-Compile View

Important: A progress bar indicates that the flattened netlist is being loaded. For a large netlist, the loading may incur some runtime penalty. A Cancel button is available to cancel the loading.

Figure 2-4. Netlist Viewer—Flat Post-Compile Cone View

3. Invocation

The standalone Netlist Viewer is available for invocation in the Design Flow window. To open the standalone Netlist Viewer in the Flow window, perform one of the following steps:

Figure 3-1. Netlist Viewer Invocation—Design Flow Window

When Netlist Viewer opens, it makes available for loading and viewing the following views of the netlist:

4. Netlist Viewer Windows

4.1 Opening a View

Click any of the following views at the top-left corner to load the netlist into the Netlist Viewer for viewing:

Figure 4-1. Netlist Viewer on Start Up

Important: When you open netlist views for the first time in the Netlist Viewer, they load into system memory, where they remain until the Netlist Viewer exits. For very large designs, loading the netlist for the first time may take some time. A pop-up window reports the status of the loading process.

The Flat Post-Compile Cone view takes very little runtime because no netlist is drawn when this view is first loaded. This view does not display a netlist until instances from the design tree are selected and loaded.

Figure 4-2. Loading New View Popup Window

After the netlist views open for the first time, they load into system memory, making them available almost immediately in the Netlist Viewer.

4.1.1 Displaying the Flat Post-Compile Cone View

When the Flat Post-Compile Cone view has finished loading, unlike the other three views, nothing is drawn in the canvas.

Figure 4-3. Flat Post-Compile Cone View when Loaded—No Design Object Added

This view is useful when a small or critical part of a very large design needs to be examined. Design objects that can be selected for display in this view include:

To display design objects in the Flat Post-Compiled Cone view, right click the design object (Nets, Macro, Ports, or Component) in the Design Tree and select Load Selection. The design object is added to the view.

Opening a design in the Flat Post-Compile view may incur a runtime penalty. This cone view loads the same AFL netlist source file as the Flat Post-Compile view. However, this cone view, unlike the Flat Post-Compile view, draws nothing until you select a part of the design you want to display. This reduces the runtime penalty associated with drawing a large netlist for display.

Figure 4-4. Flat Post-Compile Cone View—Design Objects Added

4.1.1.1 Adding a Net

Right click a net in the Design Tree and select Load Selection to add a net to the view. Adding a net to the view adds a solid line net to the view (unless you cancel early), including all the instances and ports the net is connected to. The added net is selected in the view.

Nets that span multiple pages can be followed through the right click menu item Follow Net to Page# to go to different pages that the net is on.

Figure 4-5. Net Added to View Solid Line

4.1.1.2 Adding a Macro

A macro is a basic low-level design object from the Macro Library in the Catalog. Right click a macro in the Design Tree and select Load Selection to add a macro. Adding a macro adds the instance with its connected nets to the view. The connected nets are always dashed yellow lines, even if they are not connected to any logic outside the view. Double clicking the net adds connections (if any) and turns the net from a dashed line to a solid line. A solid line for a net indicates that it is a user-added net.

Figure 4-6. CFG4 Macro Added

4.1.1.3 Adding a Port

To add a port to the view, right click a port in the Design Tree and select Load Selection. Adding a port to the view is the same as adding a net connected to the port.

4.1.1.4 Adding a Component

Right click a component in the Design Tree and select Load Selection to add a component to the view. Adding a component to the view is the same as selecting all lower level macros and adding them to the view. The added macros are selected.

Important: To save runtime for very large components with many low level macros, the macros are added, but cannot be selected.

Figure 4-7. Component Added

4.1.1.5 Load/Driver Display

Design objects can also be added to the view through the right click menu to add load/driver. This action adds any instances at the different logical levels.

4.2 Closing a View

To close the opened view, click an opened view at the top of the Netlist Viewer. A closed view stays in system memory as long as the Netlist Viewer remains open. Opening the same netlist view at a later time does not incur runtime penalty, as no loading is required.

4.3 Netlist Viewer Windows

When the Netlist Viewer opens, it displays three windows by default.

Figure 4-8. Netlist Viewer Windows

4.4 Design Tree Window

The Design Tree window displays the design hierarchy from the top level. By default, when the Netlist Viewer opens, it displays the Design Tree window.

Important: The Design Tree window is displayed by default when the Netlist Viewer opens. Hiding the Design Tree view will leave more display area for the Canvas view. To get a bigger display area for the canvas view, hide the Design Tree window (Netlist Viewer > Windows > Uncheck Show Tree).

The Design Tree window displays:

The design tree is different with different netlist views. For the Flat Post-Compile view, the design tree displays a much larger number of nets than the RTL view or Hierarchical Post-Synthesis view, because the netlist is flattened in the Post-Compile view and all nets are counted. The nets in the Flat Post-Compile view, unlike the RTL view or the Hierarchical Post-Synthesis view, shows only one value for fanout (global fanout) because it is a flattened view (no hierarchy).

For nets that are part of a NetBundle, the NetBundle name is followed by a number in parentheses that indicates the total number of nets in the NetBundle.

Figure 4-9. Design Tree Window

4.4.1 Filter

The display of design objects in this view can be filtered based on:

Click the Filter button at the top-right corner of the Design view to filter design objects.

4.4.2 Interoperability Between Windows and Views

When a design object such as a net, an instance or a port is selected in the Design Tree window, the object is selected in the different netlist views. The reverse is also true. An object selected in one netlist view window is also selected in the Design Tree window and other netlist views.

Interoperability works only when the Toggle Cross-probing icon is enabled. ?

4.5 Canvas Window

The Canvas Window displays the:

When a view is opened, a view tab is added across the top of the Canvas window for ease of switching between views.

Important: To get a larger display area for the Canvas view, hide the Design Tree Window (Netlist Viewer > Windows > Uncheck Show Tree) and hide the Log window (Netlist Viewer > Windows > Uncheck > Show Log). Hiding the Log window and the Design Tree window leaves more display area for the Canvas window. Alternatively, press CTRL+W to maximize the work area.

Figure 4-10. Turn on/off Design Tree Window and Log Window

Icons in the Canvas window allow you to:

Figure 4-11. Canvas Window

4.6 Log Window

The Log window displays the following:

Important: The Log window displays by default when the Netlist Viewer opens. Hiding the Log window will leave more display area for the Canvas view. To get a larger display area for the Canvas view, hide the Log window (Netlist Viewer > Windows and uncheck (Show Log).

Figure 4-12. Log Window

4.6.1 Status Bar

The status bar at the bottom-right corner of the Netlist Viewer displays the following:

Figure 4-13. Status Bar

5. Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Revision Date Description
M 08/2024 This document is released with Libero SoC Design Suite v2024.2 without changes from v2024.1.
L 08/2023 Editorial updates only. No technical content updates.
K 08/2023 Editorial updates only. No technical content updates.
J 05/2023 Updated the document with the latest and better quality graphics.
H 04/2023 This document is released with Libero SoC Design Suite v2023.1 without changes from v2022.3.
G 12/2022 This document is released with Libero SoC Design Suite v2022.3 without changes from v2022.2.
F 08/2022 This document is released with Libero SoC Design Suite v2022.2 without changes from v2022.1.
E 04/2022 This document is released with Libero SoC Design Suite v2022.1 without changes from v2021.3.
D 12/2021 In section 1. Supported Families and Platforms, added PolarFire SoC to the list of supported devices.
C 08/2021 Updated the document with better quality graphics.
B 04/2021 This document is released with Libero SoC Design Suite v2021.2 without changes from v2021.1.
A 11/2020 Editorial updates only. No technical content updates.
4.0 12/2018 Document converted to Microchip template.
3.0 10/2017 Document template updates and minor text edits
2.0 05/2017 Minor updates
1.0 12/2016 Initial Revision

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