ℹ️ Document Conversion Notice: This document has been converted from PDF and formatted to fit this screen. Diagrams and images may be available only in the original here.

Microchip SmartDebug User Guide

This document provides a detailed guide to Microchip's SmartDebug tool, an essential component of the FPGA design flow. SmartDebug enables efficient verification and troubleshooting of FPGA arrays and SerDes at the hardware level, directly through their Joint Test Action Group (JTAG) ports.

Key Features and Capabilities

SmartDebug offers several modes of operation, including Integrated Mode and Standalone Mode, catering to different user preferences and workflow requirements. The tool supports a wide range of Microchip device families, including PolarFire, RT PolarFire, PolarFire SoC, RT PolarFire SoC, SmartFusion 2, IGLOO 2, and RTG4.

Users can leverage SmartDebug to:

Debug FPGA arrays and SerDes without internal logic analyzers.
Capture FPGA device status, MSS register access, and memory content (Flash and DDR).
Utilize dedicated probe points for simplified and accelerated debugging.
Select and change probe points on-the-fly, reducing recompile times.

Getting Started with SmartDebug

The guide outlines the steps for setting up and using SmartDebug, including creating designs, configuring devices, and debugging devices connected in a JTAG chain. It also details how to use the SmartDebug user interface, including the Project menu, Log window, and various tools for programming connectivity.

For the latest version of this document and further details, please refer to the Libero SoC Design Suite Documentation.

Models: Libero SoC Design FPGA Design Suite, SoC Design FPGA Design Suite, Design FPGA Design Suite, FPGA Design Suite

File Info : application/pdf, 269 Pages, 11.69MB

smartdebug ug 2025 1

References

Antenna House PDF Output Library 7.4.1889

Related Documents

	Libero SoC Design Flow User Guide Comprehensive guide to Microchip's Libero SoC design suite, covering FPGA design flow, tools, constraints management, implementation, and debugging for devices like PolarFire, PolarFire SoC, SmartFusion 2, IGLOO 2, and RTG4.
	Microchip SmartPower User Guide for Libero SoC v2025.1 This user guide provides a comprehensive overview of Microchip's SmartPower tool, a power-analysis solution for visualizing and optimizing power consumption in Microchip SoC FPGAs. Learn how to analyze power by component, voltage rail, and clock domain, and utilize features like custom modes and scenario profiles for detailed power evaluation.
	Libero SoC v2025.1 Release Notes - Microchip Technology Detailed release notes for Microchip's Libero SoC Design Suite v2025.1, covering new features, enhancements, resolved issues, and known limitations for FPGA and SoC device design.
	Libero SoC Tcl Command Reference Guide Comprehensive guide to Tcl commands for the Microchip Libero System-on-Chip (SoC) design suite, covering device families, scripting, and various command categories for efficient FPGA and SoC FPGA design.
	SmartTime Static Timing Analyzer User Guide for Libero SoC v2025.1 This user guide provides comprehensive information on using the SmartTime Static Timing Analyzer within the Libero SoC Design Suite v2025.1. Learn how to perform static timing analysis, identify timing violations, manage timing constraints, and generate various timing reports for your FPGA designs.
	Microchip Encoder Interface v4.2 User Guide User guide for Microchip's Encoder Interface v4.2 IP core, detailing its functionality, features, implementation, and usage for generating relative angular position and speed from encoder inputs, essential for motor control applications like FOC.
	Microchip Netlist Viewer User Guide for Libero SoC v2024.2 This user guide provides comprehensive instructions on using the Microchip Netlist Viewer, a graphical tool for analyzing Field Programmable Gate Array (FPGA) designs. It covers various netlist views, invocation methods, window functionalities, and design object manipulation within the Libero SoC Design Suite.
	Secure IP Flow for IP Vendors and Libero SoC User Guide This user guide provides comprehensive instructions on implementing a secure IP flow for vendors and users of Libero SoC. It details the process of encrypting IP cores using the IEEE 1735-2014 standard, managing encryption envelopes, and running designs with encrypted IP within the Libero SoC environment. The document covers essential steps from obtaining public keys to simulating and generating final design files, ensuring IP security and interoperability across various EDA tools.