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Netlist Viewer User Interface User Guide

Libero SoC v2025.1

Introduction

The Netlist Viewer is a critical tool within the Libero SoC design suite, offering FPGA designers a graphical representation of their design's netlist. This guide details how to effectively use the Netlist Viewer to analyze designs at various stages, from RTL to post-synthesis and post-compile. It covers navigation techniques, understanding different views, and utilizing features like logical cones for in-depth debugging and path analysis.

Explore the capabilities of the Netlist Viewer to enhance your FPGA design workflow and ensure optimal performance.

For more information on Microchip FPGA products and support, visit Microchip Technology Inc.

Models: v2025.1, 12.0, Libero SoC Design Suite, SoC Design Suite, Design Suite, Suite

File Info : application/pdf, 28 Pages, 3.25MB

nlv interface ug 2025 1

References

Antenna House PDF Output Library 7.4.1889

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