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Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

This user guide provides comprehensive details on the integrated Network-on-Chip (NoC) subsystem within Intel Agilex® 7 M-Series FPGAs. The NoC is designed to facilitate high-bandwidth data movement between the FPGA core logic and critical memory resources, including High Bandwidth Memory (HBM2e) and external memories such as DDR5.

Explore the architecture, design considerations, and implementation flows using Intel Quartus® Prime Pro Edition software. This document covers the NoC's high-level architecture, segments, protocol support, design flow, IP references, simulation methodologies, and power estimation techniques. It is an essential resource for engineers and developers working with Intel Agilex 7 FPGAs to optimize performance for bandwidth-intensive applications.

Key Features Covered:

NoC Architecture and Applications
Hard Memory NoC Details
Design Flow and IP Integration
Simulation and Performance Analysis
Power Estimation

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