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Multi Channel DMA Intel FPGA IP for PCI Express: Design Example User Guide Comprehensive user guide for the Multi Channel DMA Intel FPGA IP for PCI Express, detailing design example generation, simulation, compilation, hardware testing, and driver configurations for Intel FPGA platforms. |
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Intel Embedded Peripherals IP User Guide for Quartus Prime Explore Intel's comprehensive Embedded Peripherals IP User Guide for the Quartus Prime Design Suite. This manual details various IP cores, including FIFO, SPI, UART, and DMA, providing functional descriptions, parameters, and programming models for FPGA development. |
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Intel AN 829: PCI Express Avalon-MM DMA Reference Design This document details the AN 829 reference design for PCI Express Avalon-MM DMA, demonstrating the performance of Intel Arria 10, Cyclone 10 GX, and Stratix 10 Hard IP for PCIe using an Avalon-MM interface and an embedded DMA controller. It covers hardware and software requirements, project hierarchy, parameter settings, DMA procedure steps, setup, and throughput analysis. |
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Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide This Intel user guide provides comprehensive details on the Avalon® Memory-Mapped (Avalon-MM) interface for Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs, facilitating integration with PCI Express* (PCIe) for high-performance applications. It covers essential topics such as parameter settings, register configurations, physical layout, and design examples for PCIe Gen1, Gen2, and Gen3. |
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Scalable Switch Intel FPGA IP for PCI Express User Guide | Intel User guide for Intel's Scalable Switch FPGA IP for PCI Express. Features include a configurable switch architecture, upstream and downstream port connectivity, Hot Plug support, and integration with Intel P-Tile Avalon Streaming IP for PCIe Gen3 x16. Compatible with Intel Stratix 10 DX and Agilex FPGAs. |
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R-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide User guide detailing Intel's R-Tile Avalon Streaming FPGA IP for PCI Express, covering PIO, SR-IOV, and Performance design examples. Provides setup, simulation, and hardware testing guidance for Intel Agilex 7 FPGAs using Quartus Prime. |
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Intel Arria 10 & Cyclone 10 GX Avalon-MM DMA for PCI Express User Guide Explore the Intel Arria 10 and Cyclone 10 GX Avalon-MM DMA Interface for PCI Express IP core with this comprehensive user guide. Learn about features, parameters, interfaces, and implementation details for FPGA development. |
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Intel FPGA P-Tile Avalon Streaming IP for PCI Express Design Example User Guide This user guide provides comprehensive instructions for using the Intel FPGA P-Tile Avalon Streaming IP for PCI Express design example. It covers both Programmed Input/Output (PIO) and Single Root I/O Virtualization (SR-IOV) configurations, detailing design generation, simulation, compilation, and hardware testing procedures. The guide also includes information on directory structure, Linux kernel driver installation, and document revision history. |