Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide

Overview

This document serves as a comprehensive user guide for the Network-on-Chip (NoC) subsystem integrated within the Intel Agilex 7 M-Series FPGAs. The NoC is a critical component designed to facilitate high-bandwidth data movement between the FPGA's core logic and its memory resources, including high-bandwidth memory (HBM2e) and external memories such as DDR5.

The guide details the architecture of the hard memory NoCs, which run horizontally along the top and bottom edges of the FPGA die, enabling efficient memory bandwidth utilization and reducing routing congestion. It also covers the fabric NoC, an optional feature for storing read data within the FPGA fabric.

Key Features and Applications

The Intel Agilex 7 M-Series FPGA's NoC subsystem is engineered for demanding applications requiring substantial data throughput. Key aspects covered include:

General NoC architecture and its components (initiators, targets, switches).
Specific NoC segments and their interfaces (UIB, GPIO-B, HPS).
Protocol support, primarily AMBA AXI4 and AXI4-Lite.
Design considerations, including latency, bandwidth, and physical placement.
The design flow using Intel Quartus Prime Pro Edition software.
Simulation and power estimation methodologies.

Applications benefiting from this technology include parallel computing, SmartNICs, real-time audio/video processing, and high-performance computing, where efficient and low-latency communication between processing elements and memory is paramount.

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Overview

Key Features and Applications

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