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Intel FPGA AI Suite Getting Started Guide | Accelerate AI Inference on FPGAs Learn how to accelerate Artificial Intelligence (AI) inference on Intel FPGAs with the Intel FPGA AI Suite. This guide provides installation instructions, prerequisites, and a quick start tutorial for using the suite with supported hardware like Intel Agilex and Arria 10 FPGAs. |
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Native Loopback Accelerator Functional Unit (AFU) User Guide This user guide provides detailed information on the Native Loopback Accelerator Functional Unit (AFU), including its overview, sample accelerator functions, control and status register descriptions, and test modes. It is updated for Intel Acceleration Stack for Intel Xeon CPU with FPGAs versions 1.2 and 2.0. |
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Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide This user guide provides a comprehensive overview of the Intel® SoC FPGA Embedded Development Suite (SoC EDS), a tool suite for embedded software development on Intel FPGA SoC devices. It covers installation, toolchains, development roles, bootloader management, hardware libraries, flash programming, compilers, and device tree generation, updated for Intel Quartus Prime Design Suite 20.1. |
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Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide Explore the Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) subsystem with this comprehensive user guide. Learn about its architecture, design flow, IP integration, simulation, and power estimation for high-bandwidth data movement between FPGA logic and memory resources like HBM2e and DDR5. |
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Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide User guide detailing the Network-on-Chip (NoC) subsystem for Intel Agilex 7 M-Series FPGAs, covering architecture, design flow, memory interfaces (HBM2e, DDR5), AXI4 protocol, simulation, and power estimation for high-bandwidth applications. |
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OCT Intel® FPGA IP User Guide This user guide provides detailed information on the OCT Intel FPGA IP, including its features, functional description, parameter settings, signals, and QSF assignments. It supports Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, offering dynamic on-chip termination for improved signal integrity. The guide also covers IP migration from older ALTOCT IP cores and design example generation. |
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Intel® FPGA Design Flow for Xilinx® Users: A Comprehensive Guide This application note guides Xilinx designers in migrating their FPGA designs to Intel® Quartus® Prime Pro Edition software, covering technology comparison, tool equivalencies, and detailed conversion steps for primitives, IP cores, and constraints. |
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Intel® FPGA Fronthaul Compression IP User Guide User guide for Intel® FPGA Fronthaul Compression IP, detailing features like μ-law/block floating-point compression, O-RAN compliance, installation, and parameterization for telecommunications applications. |