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Chapter 1. Introduction

The growing popularity of standard USB PD3.0 chargers for mobile phones and notebooks spurs the demand for leveraging these chargers to replace individual chargers for battery-powered electronic devices, thereby reducing e-waste.

The AP33771 Evaluation Board (EVB) is designed as an evaluation vehicle for charging applications between a Type-C Connector-equipped Device (TCD, Energy Sink) and a Type-C Connector-equipped PD Charger or Adaptor (PDC, Energy Source) using a Type-C-to-C cable.

Figure 1 illustrates a typical TCD embedded with the PD3.0 Sink controller IC (AP33771), physically connected to a PDC embedded with a USB PD3.0 decoder (e.g., AP43771) via a suitable Type-C-to-Type-C cable. Based on USB PD3.0 compliant firmware, the AP33771 and AP43771 can negotiate to establish a suitable PD3.0 charging state.

Figure 1 - A typical TCD with AP33771 PD3.0 Sink Controller to Request Input Voltage and Power from a USB PDC

Diagram Description: A diagram shows a "TCD Device" with a "USB Type-C® Connector" linked to an "AP33771 (PD Sink)" which is part of a "Power Converter Unit". This TCD is connected to a "USB PD Source" (AP43771) via a "Type C-to-C Cable". The illustration depicts the power flow from the source to the sink.

To enhance user experience with the AP33771 as a USB Sink controller in TCDs, the AP33771 includes built-in firmware for automatic cable voltage drop compensation and for charging via legacy Type-A chargers using a Type-A-to-C cable.

This AP33771 User's Guide for the Evaluation Board (EVB) details a simple resistor-setting arrangement to request desired input voltage and power for a typical TCD. The voltage and power granted by a PDC depend on its capability and may match the request exactly or provide the lowest sufficient voltage and power, especially considering the PDC's PPS (Programmable Power Supply) capability.

Chapter 2. AP33771 Sink Controller

2.1 Package Outline

Figure 2 shows the package outline of the AP33771 IC.

Figure 2 - Package Outline

Diagram Description: A top-down view of the AP33771 integrated circuit in a QFN-24 package, illustrating the pin layout and numbering from 1 to 24.

2.2 Pin Descriptions

Note: AHV - Analog High Voltage pin; AP - Power for Analog Circuit and Analog I/O pins, 5.0V operation; AI - Analog Input pin; DP - Power for Digital Circuit and I/O pins, 3.3V operation; AIO - Analog I/O pin; DIO - Digital I/O pin.

Chapter 3. EVB Hardware Details

3.1 EVB TOP View

Figure 3 displays the top view of the AP33771 evaluation board and its key components.

Figure 3 - AP33771 evaluation board top view and its key portions

Diagram Description: A photograph of the AP33771 Evaluation Board (EVB) with labels pointing to key components: VBUS Power LED, Charge/Fault LED, AP33771 Sink Controller, VOUT Enable MOS Switches, VOUT Load Connector, Type-C Connector, Power Capability Selector, and Voltage Selector.

3.2 EVB Block Diagram

Figure 4 presents the block diagram of the AP33771 evaluation board.

Figure 4 - Block diagram of the AP33771 evaluation board

Diagram Description: A block diagram illustrating the AP33771's function in a USB PD sink system. It shows the USB Type-C connector, CC1/CC2 pins with pull-down resistors (Rd), the AP33771 IC, connections to VBUS, PWR_EN, V5V, VSEL pins, and an NMOS switch controlling the Load output.

3.3 EVB Schematics

Figure 5 shows the schematics of the AP33771 Evaluation Board, including tables for PDO Selection and Power Capability.

Figure 5 - Schematics of the AP33771 Evaluation Board With Tables of PDO Selection and Power Capability

Diagram Description: A schematic diagram of the AP33771 Evaluation Board, detailing the USB Type-C receptacle, the AP33771 IC, power selection resistors (R20-R29), voltage selection jumpers (J4), LEDs (D1, D2), and power components (Q1, Q2). It also includes tables for Power Capability Selection and Voltage Selection.

3.4 EVB System BOM

Chapter 4. EVB Function Description

The AP33771 EVB offers users a simple resistor-setting method to enable USB-PD negotiation between the TCD device and an external PDC. If negotiation is successful, the PDC supplies the requested voltage and power to the TCD device via VBUS over the Type-C cable. If negotiation fails, the PDC defaults to 5V PDO, and the LED flickers with a "Mismatch" pattern.

4.1 Board Outline

Figure 6 shows the AP33771 EVB outline and floor plan, with connector and jumper locations detailed in Table 2.

Figure 6 - Connector and jumper locations

Diagram Description: A visual representation of the AP33771 EVB board layout, indicating the positions of connectors (J1, J3, J4) and jumper pins (VSEL2-0).

4.2 Voltage Selection

Users can select the appropriate voltage by configuring jumpers at J4, which connects to the VSEL2~VSEL0 pins of the AP33771. Table 3 maps these selections to target voltages.

The top four rows of Table 3 correspond to standard Fixed PDOs (5V, 9V, 15V, 20V). The bottom four rows select voltages (4.3V, 8.6V, 12.9V, 17.2V) suitable for typical Lithium-Ion battery applications (1, 2, 3, or 4 cells). Users select the desired voltage by setting the appropriate resistor configuration at J4.

Note: If VSEL2 is ON (VSEL2 = 1), only sources with PPS APDO are supported.

4.3 Power Capability Selection

The AP33771 requests the corresponding voltage from the external PD Charger's (PDC) PDO capability. During voltage selection, PPS Augmented PDO (APDO) has higher priority than Fixed PDO.

Required power capability can be selected via the J3 connector, which connects a resistor to the AP33771's PSEL pin. The AP33771's constant current source output (20µA±3.0%) at the PSEL pin, combined with an external resistor, creates a voltage that the internal ADC measures to select the corresponding power capability. Users can choose a resistor via a jumper to set the desired power capability, as detailed in Table 4.

The AP33771 also verifies if the source power is sufficient for the selected power level. If the source power is lower, negotiation fails with a power mismatch, the AP33771 disables the MOS switch, and the LED flickers with a "Mismatch" pattern.

For current capabilities exceeding 3A, an e-Marker Type-C cable is required to comply with USB PD specifications. The PD source adapter uses the e-Marker to report cable parameters.

Designers for TCDs are advised to use resistors with ±1% accuracy for connecting to the PSEL pin.

Chapter 5. Built-In Application Firmware Features

5.1 Firmware Overview and LED Indication

The AP33771 features built-in firmware that intelligently handles various usage scenarios. Figure 7 illustrates the state transition diagram.

Figure 7 - AP33771 state diagram

Diagram Description: A state transition diagram for the AP33771, showing states like INIT, CHARGING, LOW_CURR, LOW_VOLT, MISMATCH, FAULT, and the transitions between them based on events like VBUS power, PD/VSEL, VSEL/PSEL mismatch, OVP, and VOUT compensation.

The AP33771 uses GPIO4 to control LED lighting. Table 5 summarizes the transition conditions, LED indication, and VOUT status for each state.

5.2 PDO Selection Scheme

During PD negotiation, the AP33771 evaluates all PDOs from the PD Source's capability discovery to find a match with VSEL/PSEL, according to Table 6. If a match is found, the AP33771 enables the associated MOS switches, connecting VBUS to VOUT.

If multiple PDOs match, PPS PDOs take precedence over Fixed PDOs. If multiple PPS PDOs match, the lowest voltage PPS PDO is selected. If no PDO matches, the AP33771 requests the 1st PDO (5V) and enters MISMATCH state. If the source is not PD capable and VSEL is not 5V, MISMATCH state is entered (Refer to Section 5.5).

Note: VVSEL: Selected Voltage by VSEL; PPSEL: Selected Power by PSEL; VFIXED: Voltage of Fixed PDO; VPPSMIN: Minimum Voltage of PPS PDO; VPPSMAX: Maximum Voltage of PPS PDO; VPROG: Nominal Voltage of PPS; IMAX: Maximum Current of PDO/APDO.

Table 7 shows the minimum and maximum voltages for the Programmable Power Supply corresponding to the Nominal Voltage (Extract from USB-PD Specification).

5.3 Over Voltage Protection (OVP)

The AP33771 triggers OVP protection when the VBUS voltage exceeds the OVP threshold. Table 8 summarizes the correspondence between VSEL Pin combinations (VSEL2, VSEL1, VSEL0), the selected voltage (VVSEL), and the OVP Threshold Voltage.

The OVP de-bounce mechanism prevents false triggers. If VBUS voltage exceeds the OVP threshold after the 30ms de-bounce time, the AP33771 enters FAULT state, disabling output MOS switches and causing the LED to flicker with a "Fault" pattern.

5.4 Automatic Type C-to-C Cable Voltage Drop Compensation

After negotiation and MOS switch enablement, the AP33771 monitors the VOUT voltage. If VOUT is more than 6% below the selected VVSEL voltage, the AP33771 enables Automatic Type C Cable Voltage Drop Compensation for VSEL2 = 0 combinations. Table 9 details the compensation specifications.

Note:
⁽¹⁾ Allows PDO 5V to be raised to 9V to prevent damage to subsequent circuits; higher PDOs (15V, 20V) are not allowed.
⁽²⁾ Type C-to-C cables can have up to 250mΩ resistance. Max compensation is 1.3V (source to sink), within 1.25V for 5A current.
⁽³⁾ AP33771 enables Voltage Drop Compensation when VSEL2 is 0 (VVSEL=5V/9V/15V/20V) and VVOUT < VVSEL * (1 - 6%).

Table 10 shows how compensation criteria change with selected voltage.

Table 11 provides examples of Type C-to-C Cable Voltage Drop Compensation situations based on the source PDO.

Note:
⁽¹⁾ If cable voltage drop is 1.0V, Adjusted VARequest would be 9V and VVOUT would be 8V.
⁽²⁾ Adjusted VARequest would be 5.7V for VVOUT to reach 4.7V.

If Voltage Drop Compensation fails (no suitable PDO found or compensation exceeds limit), the AP33771 transitions to the LOW_VOLT state.

5.5 Legacy Type A Charger with Type A-to-C Cable

When the energy source is a legacy Type-A charger connected via a Type-A-to-C cable, the AP33771 enters Non-PD Mode after PD negotiation fails. Table 12 shows the Non-PD Mode states.

If VSEL is 5V and VOUT voltage is higher than 4.7V, AP33771 enters CHARGING state. If VSEL is 5V and VOUT voltage is lower than 4.7V, AP33771 enters LOW_VOLT state. If VSEL is not 5V, AP33771 enters MISMATCH state.

Chapter 6. USB Type C-to-C PD Sink-Source Application Examples

Cases 1 to 6 demonstrate various scenarios and procedures for requesting power profiles from a TCD and establishing charging states with a PDC's power source capability (Figure 8).

Figure 8 - Examples Based on a Typical TCD Application Scenario with an USB PDC

Diagram Description: A diagram illustrates a typical USB PD application scenario. It shows a "USB PD Source" (AP43771) connected via a "Type-C Cable" to a "TCD Device" which includes a "USB Type-C® Connector" and an "AP33771 (PD Sink)" connected to a "Power Converter Unit".

Case 1:

PDC=36W
PDO: 5V/3A, 9V/3A, 15V/2.4A
APDO: None
TCD = 15V and 36W
VSEL2 = 0, RPSEL= 56KΩ, VSEL1 = 1, VSEL0 = 0
VBUS = 15V, VOUT = 15V

A TCD requests 15V and 36W from a 36W PDC source with fixed PDOs (5V/3A, 9V/3A, 15V/2.4A).

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 56 kΩ ±1% resistor to the PSEL pin (Selection No. 6 in Table-4).
3. AP33771 initiates handshake upon Type-C cable connection.
4. VBUS becomes 15V as PDO 15V/2.4A matches.
5. VOUT becomes 15V as Power and Voltage match; MOS switches are enabled.

Case 2:

PDC=36W
PDO: 5V/3A, 9V/3A, 15V/2.4A
APDO: None
TCD = 15V and 45W
VSEL2 = 0, RPSEL= 65KΩ, VSEL1 = 1, VSEL0 = 0
VBUS = 15V, VOUT = 0V

A TCD requests 15V and 45W from a 36W PDC source with fixed PDOs (5V/3A, 9V/3A, 15V/2.4A).

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 65 kΩ ±1% resistor to the PSEL pin (Selection No. 7 in Table-4).
3. AP33771 initiates handshake upon Type-C cable connection.
4. VBUS becomes 15V as PDO 15V/2.4A matches.
5. VOUT remains 0V as Power and Voltage do not fully match; MOS switches are not enabled.

Case 3:

PDC=36W
PDO: 5V/3A, 9V/3A, 15V/2.4A
APDO: 5V Prog/3A, 9V Prog/3A, 15V Prog/2.4A
TCD = 15V and 36W
VSEL2 = 0, RPSEL= 56KΩ, VSEL1 = 1, VSEL0 = 0
VBUS = 15V, VOUT = 15V

A TCD requests 15V and 36W from a 36W PDC source with fixed PDOs and APDOs.

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 56 kΩ ±1% resistor to the PSEL pin (Selection No. 6 in Table-4).
3. AP33771 initiates handshake upon Type-C cable connection.
4. VBUS becomes 15V as APDO 15V Prog/2.4A matches (APDO has higher priority).
5. VOUT becomes 15V as Power and Voltage match; MOS switches are enabled.

Case 4:

PDC=36W
PDO: 5V/3A, 9V/3A, 15V/2.4A
APDO: 5V Prog/3A, 9V Prog/3A, 15V Prog/2.4A
TCD = 12.9V and 36W
VSEL2 = 1, RPSEL= 56KΩ, VSEL1 = 1, VSEL0 = 0
VBUS = 12.9V, VOUT = 12.9V

A TCD requests 12.9V and 36W from a 36W PDC source with fixed PDOs and APDOs.

1. Set SEL2~SEL0 to "110" for 12.9V (Selection No. 7 in Table-3).
2. Connect a 56 kΩ ±1% resistor to the PSEL pin (Selection No. 6 in Table-4).
3. AP33771 initiates handshake upon Type-C cable connection.
4. VBUS becomes 12.9V as APDO 15V Prog/2.4A matches (APDO has higher priority).
5. VOUT becomes 12.9V as Power and Voltage match; MOS switches are enabled.

Case 5:

PDC=36W
PDO: 5V/3A, 9V/3A, 15V/2.4A
APDO: 5V Prog/3A, 9V Prog/3A, 15V Prog/2.4A
TCD = 15V and 45W
VSEL2 = 0, RPSEL= 65KΩ, VSEL1 = 1, VSEL0 = 0
VBUS = 15V, VOUT = 0V

A TCD requests 15V and 45W from a 36W PDC source with fixed PDOs and APDOs.

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 65 kΩ ±1% resistor to the PSEL pin (Selection No. 7 in Table-4).
3. AP33771 initiates handshake upon Type-C cable connection.
4. VBUS becomes 15V as APDO 15V Prog/2.4A matches (APDO has higher priority).
5. VOUT remains 0V as Power and Voltage do not fully match; MOS switches are not enabled.

Case 6:

PDC=36W
PDO: 5V/3A, 9V/3A, 15V/2.4A
APDO: None
TCD = 12.9V and 36W
VSEL2 = 1, RPSEL= 56KΩ, VSEL1 = 1, VSEL0 = 0
VBUS = 5V, VOUT = 0V

A TCD requests 12.9V and 36W from a 36W PDC source with fixed PDOs (5V/3A, 9V/3A, 15V/2.4A).

1. Set SEL2~SEL0 to "110" for 12.9V (Selection No. 7 in Table-3).
2. Connect a 56 kΩ ±1% resistor to the PSEL pin (Selection No. 6 in Table-4).
3. AP33771 initiates handshake upon Type-C cable connection.
4. VBUS becomes 5V because no PDO matches 12.9V, and 5V is supported per PD rules.
5. VOUT remains 0V as Power and Voltage do not fully match; MOS switches are not enabled.

Chapter 7. Compliance test

The AP33771 EVB successfully passes all test items in the Ellisys USB-PD Compliance tester.

Figure 9 - Ellisys USB PD Test Environment and Test Item List

Diagram Description: A screenshot of the Ellisys USB Explorer 350 Examiner software displays a list of completed USB PD compliance tests. Below the screenshot, a diagram shows the test setup: a "Generator", "Analyzer", and "Device Under Test" connected to a "Control Computer" via an "Ellisys System".

Chapter 8. Design Considerations

8.1 Termination of CC1/CC2 channels

Since the AP33771 lacks internal Rd resistors, designers must install 5.1K ohm resistors on both CC1 and CC2 to GND. The absence of these resistors will cause the AP33771 to misinterpret the CC direction and prevent PD negotiation.

Figure 10 - Make sure the connection of external Rd resistors on CC1 and CC2

Diagram Description: A schematic shows the termination of CC1 and CC2 channels on the AP33771. It depicts the AP33771 IC (U2) with CC1 and CC2 pins connected to ground through 5.1K ohm resistors (R1 and R2).

8.2 ESD Considerations

The AP33771 EVB is designed for functional evaluation and does not include on-board ESD protection components. It should not be used for ESD testing. For manufacturing, users must incorporate suitable ESD protection devices or optimize their PCB design.

Chapter 9. Revision History

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