Diodes Incorporated APK43070

Description

The APK43070 is a single-chip synchronous buck controller (SBC) with a USB Type-C PD3.1 source controller. It supports standard power range (SPR)/programmable power supply (PPS) up to 21V, and extended power range (EPR)/adjustable voltage supply (AVS) up to 28V. It is designed for DC power providers and control of single-port or multiple-port charging applications.

The compact buck controller in APK43070 is a constant frequency synchronous step-down controller with high driving capability, optimized dead time, and high driving gate voltage, suitable for middle- and high-power charging. It includes integrated drivers for external N-MOSFETs. The VIN DC power pass-through mode is supported to enhance converter power efficiency.

The APK43070 integrates the SBC and PD3.1 decoder functions, resulting in a small footprint and reduced PCB size for high-power-density charging applications. By leveraging the MOS switches of the synchronous buck regulation, the PD output MOS switch for each port can be saved, reducing BOM cost.

To support higher power efficiency, extremely low standby power, and smart power sharing for multiple-port applications without an external MCU, the APK43070 integrates an I2C interface, master/slave addressing scheme, and interrupt/wake-up mechanism. Up to 8 port addresses are supported through resistor selection.

Due to its high-voltage process, the APK43070 offers VBUS short protection on CC1/CC2 pins up to 30V. The APK43070 provides comprehensive safety protection, including overvoltage protection (OVP), overcurrent protection (OCP), overtemperature protection (OTP), and moisture detection of the connector.

Features

• Extremely low standby power for multiple-port Type-C PD3.1 SPR and EPR chargers, adapters, power strips, or power hubs.
• Type-C PD3.1 SPR and EPR charging for high-voltage battery of portable outdoor generators.
• Type-C PD3.1 SPR and EPR chargers for general-purpose charging applications.

Pin Assignments (Top View)

Refer to the pin assignment diagram for details on VIN, CC1, CC2, DN, DP, TS, SDA, SCL, GPIO1, GPIO2, GPIO3, VFB, COMP, PGND, LG, SW, HG, BST, GATE, VDRV, V5V, GND, CSN, CSP.

Applications

• Single-Chip Buck Controller with Type-C PD3.1 Source Controller
• Support USB PD3.1 EPR/AVS up to 28V, SPR/PPS up to 21V.
• Operating Switching Frequency is 125kHz/250kHz/400kHz, configurable via GPIO3.
• Support Power Sharing Through I2C.
• Support High PWM Duty Cycle up to 95% @125kHz/90% @ 400kHz.
• Operating Input Voltage 4V to 36V.
• Support Bypass Mode to Enhance Output Power Efficiency.
• Frequency Dithering for EMI Restraining.
• Support Legacy BC1.2, and QC3.0/4/4+/5.0.
• Support External OTP by TS Pin.
• Support I2C-Based Topology Up to 8 Ports Without External MCU.
• Support I2C Addresses Up to 8 and Assigned by GPIO1.
• Support PDO Profiles Selected by GPIO2.
• Support Extremely Low Standby Power (< 120µA) with Wake-Up.
• Support Comprehensive Protection Schemes — OVP, UVP, OCP, OTP and Moisture Detection of the Connector with Autorecovery.
• VBUS Short Protection on CC1/CC2 and DP/DN Pins Up to 30V.
• Totally Lead-Free & Fully RoHS Compliant.
• Halogen and Antimony Free. "Green" Device.

Typical Applications Circuit

The APK43070, a high-integration synchronous buck controller with USB PD3.1 EPR decoder, supports single-port or multiple-port charging at optimal system BOM with extremely low standby power consumption. The buck controller is a constant frequency synchronous step-down controller with integrated low-side and high-side drivers for external N-channel MOSFETs. The internal regulator supplies bias rails and MOSFET gate drivers. PWM control is based on voltage-mode control, providing output current limiting by monitoring the voltage drop across the sense resistor between CSP and CSN pins. During normal operation, the output voltage is internally sensed through a resistive divider at the FB pin, and a capacitor connected between VFB and VBUS is needed. The amplifier output pin, COMP, connects to a compensation circuitry for loop stability. The VIN DC power pass-through is supported by a bypass mode from the GATE pin.

For multi-port PD3.1 charging applications, the APK43070 supports smart power sharing for up to 8 ports without an extra MCU. It uses an I2C interface, interrupt and wake-up mechanism, master/slave addressing scheme, and low standby power design to optimize system BOM cost and power efficiency.

All power sharing operations communicate via the I2C interface bus between the master and each slave port. Any attach/detach event initiates an interrupt signal to wake up the master stage for adjustment. The I2C master and slave addresses for all APK43070 are set by connecting a resistor value on the GPIO1 pin, supporting up to 8 addresses.

Similar to the one-port solution, the PD output VBUS MOS switch for each port can be saved by leveraging the MOS switches of the synchronous buck controller. The APK43070 has built-in source PDO power profiles, which can be selected by connecting a corresponding resistor to a pre-determined pin. If pin count is limited, the PDO can be pre-fixed through firmware code assignment.

APK43070 Multi-Port PD3.1 Solution Key Features:

• No additional MCU, up to 8 ports supported.
• No VBUS switch MOSFET to reduce total BOM.
• I2C address selected by resistor.
• Power sharing controlled through I2C bus.
• PDO power profile selected by resistor or pre-fixed.
• PD3.1 EPR/AVS up to 28V, SPR/PPS up to 21V.

Refer to Figure 1 for the APK43070 Circuit Topology Used for Multi-Port PD3.1 Charging Application.

Pin Descriptions

Table 1 provides a mapping of pin numbers to pin names and their functions:

Functional Block Diagram

Figure 2 illustrates the APK43070 Block Diagram, showing the interconnections of various functional blocks including HVLDO, VBUS, OVP, UVP, SCP, LDO5, Bootstrap, Bandgap, VREF, CC1/2, V5V, VCONN Switch, IRP, VBG, BMC, Digital Control Logic, QC4.0 & D+/D-, VIN, CSN, ADC, CC1/2, D+/D-, GPIO, GND, SDA, SCL, COMP, VPP, OTP, OSC, OS, SR Latch, CMP, CV_DAC, VOUT Discharge, CVGM, GPIOn, CSN, IFB, LS & AMP, CSP, CC DAC, and NG DRV.

Absolute Maximum Ratings

Table 6 lists the Absolute Maximum Ratings for the APK43070, including voltage ratings for VIN, GATE, SW, HG, BST, CSN/CSP, CC1/CC2, DP/DN, and other pins, as well as operating junction temperature, storage temperature, lead temperature, and ESD ratings (Human Body Model, Charged Device Model).

Note 4: Stresses beyond Absolute Maximum Ratings can cause permanent damage. Functional operation outside Recommended Operating Conditions is not implied. Extended exposure can affect reliability.

Note 5: For GPIO1-3, SDA, SCL, TS pins pulled high to a voltage source, a series resistor with a minimum 10kΩ is recommended.

Package Thermal Information

Table 7 provides Package Thermal Information, including Junction-to-Ambient Thermal Resistance (ROJA), Junction-to-Case (Top) Thermal Resistance (ReJC(top)), Junction-to-Board Thermal Resistance (ReJB), Junction-to-Top Characterization Parameter (ΨJT), Junction-to-Board Characterization Parameter (ΨJB), and Junction-to-Case (Bottom) Thermal Resistance (ReJC(bot)).

Note 6: Test condition: device mounted on FR-4 substrate PC board, 2oz copper, with the minimum footprint.

Recommended Operating Conditions

Table 8 specifies the Recommended Operating Conditions, including Supply Voltage (VIN), Output Voltage (VOUT), Operating Ambient Temperature (TA), and Operating Junction Temperature (TJ).

Note 7: Device function is not guaranteed outside recommended operating conditions.

Electrical Characteristics

The following tables detail the Electrical Characteristics of the APK43070:

VIN Pin & Internal Bias Section

V5V & CV Function

Current-Sense Function

CC1/CC2 Pin Section

DP/DN Pin Section

Note 8: Guaranteed by design.

Digital I/O Pin Section (GPIO1/2/3)

Protection

Note 9: Guaranteed by design.

GATE DRIVER

Operation Frequency

SPREAD SPECTRUM

ERROR AMPLIFIER

Note 8: Guaranteed by design.

Application Information

Function Description

The APK43070 integrates a synchronous buck controller with a USB Type-C PD3.1 source controller. It supports SPR/PPS up to 100W, and EPR/AVS up to 140W. The APK43070 is targeted for high-power-density charging products with high power efficiency and extremely low standby power, and can address multiple-port charging applications for up to 8 ports without an external MCU. It also supports BC1.2 and QC3.0/4/4+/5.0 protocols and provides comprehensive safety protection.

Synchronous Buck Controller in APK43070

The compact buck controller in APK43070 is a constant frequency synchronous step-down controller. It integrates drivers for external N-MOSFETs and is designed for higher power efficiency through high driving capability, optimized dead time, and high driving gate voltage for middle- and high-power charging.

Switching Frequency Setting (Dedicated Function in APK43070DKZ-13-FA01)

The APK43070 offers four switching frequency options: 125kHz, 250kHz, 350kHz, and 400kHz. The switching frequency is configured by placing a 1% precision resistor between PIN11 (GPIO3) and ground. Higher frequency reduces inductor size but lowers efficiency. For CISPR 25 EMI criteria in automotive applications, 400kHz is recommended. Table 2 shows the switching frequency settings.

Switching Frequency Dithering

To reduce EMI emissions, the APK43070 supports PWM frequency dithering with a triangle pattern (Figure 3). The modulation amplitude is +21% frequency boost (Fsw0 to Fsw+21%) with a modulation frequency of 4kHz typically.

Inductor Selection

The following equation can be used to calculate the inductor value for most system designs:

L = VOUT * (VIN – VOUT) / (VIN * ΔIL * fsw)

Where:

• ΔIL is the inductor current ripple.
• fsw is the buck converter switching frequency.

For APK43070 applications, ΔIL can be assumed as 30% to 40% of the maximum output current of 3A.

IPEAK = ILOAD + ΔIL / 2

The peak current determines the required saturation current rating, affecting inductor size. Inductor saturation reduces converter efficiency and increases power MOSFET temperature. Select an inductor with an appropriate saturation current rating. For most applications, an inductor of approximately 3.3μH to 22μH with a DC current rating at least 35% higher than the maximum load current is recommended. For maximum efficiency, the inductor's DC resistance should be as small as possible.

Input Capacitor Selection

The input capacitor reduces surge current from the input supply and switching noise. It must sustain the ripple current during the main switch's on-time and have a low ESR to minimize power dissipation from the RMS input current. The RMS current rating of the input capacitor must be higher than the RMS input current. A rule of thumb is to select an input capacitor with an RMS current rating greater than half of the maximum load current. Figure 4 shows the ratio of RMS current to load current versus duty cycle.

Due to large di/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR are preferred. If tantalum capacitors are used, surging protection should be provided to prevent failure.

Output Capacitor Selection

The output capacitor maintains a small output voltage ripple, ensures feedback loop stability, and reduces output voltage overshoots and undershoots during load transients. During an increasing load transient, the converter enters 100% duty cycle to supply more current, limited by the inductor. The output capacitor supplies the difference. During a decreasing load transient, the converter minimizes on-time to reduce current, limited by the inductor. The output capacitor absorbs inductor current ripples.

The effective requested output capacitance (COUT) can be calculated using the equations below, where the output capacitor's ESR dominates the output voltage ripple:

VOUT Ripple = ΔIL * (ESR + 1 / (8 * fsw * COUT))

Output capacitors with large capacitance and low ESR are best. For APK43070, a polymer capacitor of 100µF is recommended. To meet load transient requirements, the calculated COUT should satisfy the following inequality:

COUT > max(L * I_trans / (ΔV_overshoot * L_load), L * I_trans / (ΔV_undershoot * (VIN - VOUT)))

Where:

• I_trans is the load transient.
• ΔV_overshoot is the maximum output overshoot voltage.
• ΔV_undershoot is the maximum output undershoot voltage.

Soft-Start

The soft-start circuitry controls the output voltage slope to prevent excessive inrush current, maintain a controlled output voltage, and avoid unwanted voltage overshoots and drops during startup. The APK43070 ramps up its output voltage to 5V at 30ms with a controlled slew rate.

Compensator

The APK43070 uses an OTA error amplifier for output regulation. The COMP pin is the output of the error amplifier. A type-III compensator network is suggested (Figure 5). The type-III compensator produces two zeros and poles calculated by the equations provided.

The recommended type-III compensator values are: CC1 = 4.7nF, RC1 = 47kΩ, Cc2 = 22pF, CFF = 470pF, RFF = 0. The resulting zeros and poles are: fz1 = 720 Hz, fz2 = 3.76kHz, fp1 = 37.6kHz, fp2 = 154kHz.

Output Active Discharge

The APK43070 has built-in output discharge on the CSP pin. When the output voltage transitions from high to low, the CSP pin sinks 130mA to discharge the output capacitor.

PCB Layout Guide

PCB layout is critical for stable operation. Duplicating the EVB layout is highly recommended for optimum performance. Follow these guidelines for necessary changes:

• Keep switching current paths short and minimize loop areas formed by the input capacitor, high-side MOSFET, and low-side MOSFET.
• Place VCC bypass ceramic capacitors close to the VCC pin.
• Use a four-layer PCB with a ground plane on the mid-layer to shield radiated noises.
• Consider adding a snubber circuit across the high-side MOSFET (Drain-Source) to reduce SW spikes.
• Route CSN and CSP traces to the current sensing resistor close together as a differential pair, using a Kelvin connection to minimize line drop error.

I2C Interface and Address Setting

The APK43070 supports I2C communication between a master and each port via SDA and SCL pins. For extremely low standby power and smart power sharing in up to 8-port applications, it implements a wake-up and interrupt mechanism to improve I2C communication efficiency (Figure 6). To support the master/slave addressing scheme for up to 8 ports, addresses are set by connecting a 1% precision resistor between GPIO1 and ground. Table 3 shows the mapping of resistance values to I2C addresses and port numbers.

Power Sharing (Dedicated Configuration in APK43070DKZ-13-FA01)

The APK43070DKZ-13-FA01 includes a power sharing function. In multi-port applications, customers must set each APK43070's PDO to the system's maximum total power. If only one device is attached, it receives the maximum total power regardless of the port. If multiple devices are attached, the master port has priority over slave ports. Among slave ports, those with lower numbering have priority. For standard firmware in APK43070DKZ-13-FA01, port numbers are limited to 0, 1, 2, 3 as shown in Table 3.

Table 4 illustrates the power sharing principles for different total power configurations (140W, 100W, 65W) based on attached ports.

PDO Power Profile Selection (Dedicated Configuration in APK43070DKZ-13-FA01)

The APK43070 has built-in source PDO power profiles selectable via a 1% precision resistor connected to the GPIO2 pin. If pin count is limited, PDO tables can be pre-fixed via firmware code assignment. The APK43070's OTP memory stores 8 PDO power profiles (Table 5).

Table 5 details the PDO data supporting PD3.1 SPR/PPS and EPR/AVS up to 140W, listing power profiles, resistance values, SPR/PPS, and EPR/AVS configurations.

Safety Protections

Leveraging a high-voltage process, the APK43070 offers VBUS short protection on CC1/CC2 pins up to 30V. It also provides comprehensive safety protections including OVP, UVP, OCP, and OTP. Connector moisture detection between DP and DN pins is also supported. When safety protection is triggered (VBUS disconnected from VIN or ground by turning off high/low NMOS switches), a path is provided for VBUS to discharge to ground. The system recovers automatically after shutdown.

OCP

The APK43070 monitors output current via the 5mΩ current-sense resistor for OCP. If the load draws more current than the OCP threshold for longer than the debounce time, the APK43070 issues a Hard_Reset command, turns off VBUS, and provides a discharge path.

OVP and UVP

OVP threshold is set at 120% of the PDO voltage and is slightly adjustable. If VBUS voltage exceeds the OVP threshold for longer than the debounce time, the APK43070 turns off VBUS and provides a discharge path. A fast OVP is embedded by monitoring the VFB voltage; if it stays below a pre-determined threshold, VBUS overvoltage protection triggers immediately.

UVP is provided when VBUS voltage remains below 80% of the PDO voltage for longer than the debounce time. The APK43070 turns off VBUS and provides a discharge path.

Internal OTP

Internal OTP is supported via junction temperature detection with a default +145°C threshold and +30°C hysteresis. When the temperature exceeds the internal OTP threshold, VBUS is turned off, and a discharge path is provided. VOUT recovers automatically when the chip temperature drops 30°C below the threshold.

External OTP (Dedicated Configuration in APK43070DKZ-13-FA01)

External OTP can be supported with an NTC thermistor connected between the TS pin and ground. An internal 100μA current source from the TS pin provides an external OTP threshold set at 100mV. OTP triggers when the voltage on the TS pin is below 100mV and clears when it rises above 130mV.

Ordering Information

Note 9 provides details on ordering information. The part number structure is APK43070-X-X-EXXX. Key parameters include Product Name, Package (W-QFN4040-24 Type A1), Packing (13-inch Tape and Reel), Firmware Identification (F: Firmware Loaded, Blank: Without Firmware), Application Code (A-Z or 0-9), Firmware Code 1 (A-Z or 0-9), and Firmware Code 2 (A-Z or 0-9).

Orderable part numbers include APK43070DKZ-13-FA01 (Standard Firmware) and APK43070DKZ-13-FXXX (Customized Firmware). Packaging details are available on the Diodes Incorporated website.

Marking Information

The W-QFN4040-24 (Type A1) package marking includes an Identification Code (XX), Year (Y: 0-9), Week (W: A-Z for weeks 1-26, a-z for weeks 27-52, with 'z' representing weeks 52 and 53), and Internal Code (X).

Package Outline Dimensions

Please refer to the Diodes Incorporated website for the latest version of package outline dimensions for the W-QFN4040-24 (Type A1) package. The dimensions include A, A1, A3, b, D, D2, E, E2, e, k, and L, with values provided in mm.

Suggested Pad Layout

Please refer to the Diodes Incorporated website for the latest version of the suggested pad layout for the W-QFN4040-24 (Type A1) package. The layout includes dimensions for C, X, X1, X2, X3, Y, Y1, Y2, and Y3 in mm.

Mechanical Data

• Moisture Sensitivity: Level 1 per J-STD-020.
• Terminals: Finish – Matte Tin-Plated Leads, Solderable per J-STD-202 e3.
• Weight: 0.041 grams (Approximate).