Diodes AP33771 USB PD3.0 Sink Controller EVB User Guide

Chapter 1. Introduction

The growing popularity of standard USB PD3.0 chargers for mobile phones and notebook PCs drives the demand for leveraging these chargers to replace individual chargers for battery-powered electronic devices, thereby reducing E-Waste.

The AP33771 Evaluation Board (EVB) serves as an evaluation vehicle for charging applications between a Type C Connector-equipped Device (TCD, Energy Sink) and a Type C Connector-equipped PD Charger or Adaptor (PDC, Energy Source) via a Type C-to-C cable.

Figure 1 illustrates a typical TCD, embedded with the AP33771 PD3.0 Sink controller IC, physically connected to a PDC, which is embedded with a USB PD3.0 decoder (e.g., AP43771). Through a suitable Type C-to-Type C cable and based on USB PD3.0 compliant firmware, the AP33771 and AP43771 can undergo the USB PD3.0 standard negotiation phase to establish a suitable PD3.0 charging state.

Figure 1 - A typical TCD with AP33771 PD3.0 Sink Controller to Request Input Voltage and Power from a USB PDC

This diagram shows a TCD device, featuring a USB Type-C connector and the AP33771 (PD Sink) controller, connected via a USB Type-C cable to a USB PD Source (USB PDC) with an AP43771 decoder. The TCD is depicted requesting voltage and power from the PDC, which includes a Power Converter Unit.

To enhance user experience when adopting the AP33771 as a USB Sink controller in TCDs, the AP33771 includes built-in firmware for automatic cable voltage drop compensation and for charging via legacy Type A chargers using a Type A-to-C cable.

This AP33771 User's Guide for the Evaluation Board (EVB) explains a simple resistor-setting arrangement to request the desired input voltage and input power for a typical TCD. The voltage and power granted by the PDC for a successful match with the source's capability might be identical to the request or the lowest voltage and power sufficient to meet the request, depending on the PDC's PPS (Programmable Power Supply) capability.

Chapter 2. AP33771 Sink Controller

2.1 Package Outline

The AP33771 is available in a QFN-24 package. Figure 2 provides the package outline diagram.

Figure 2 - Package Outline

This diagram shows the physical layout of the AP33771 IC in a QFN-24 package, indicating pin numbers and their corresponding assignments.

2.2 Pin Descriptions

Table 1 details the pin numbers, names, types, and functions of the AP33771 IC.

Note:

• AHV: Analog High Voltage pin
• AP: Power for Analog Circuit and Analog I/O pins, 5.0V operation
• AI: Analog Input pin
• DP: Power for Digital Circuit and I/O pins, 3.3V operation
• AIO: Analog I/O pin.
• DIO: Digital I/O pin.

Chapter 3. EVB Hardware Details

3.1 EVB TOP View

Figure 3 presents a top view of the AP33771 evaluation board, highlighting its key components and connection points.

Figure 3 - AP33771 evaluation board top view and its key portions

This image shows the physical layout of the evaluation board. Key components identified include the Type-C Connector, VBUS Power LED, Charge/Fault LED, the AP33771 Sink Controller IC, VOUT Enable MOS Switches, VOUT Load Connector, and the jumpers for Power Capability Selector and Voltage Selector.

3.2 EVB Block Diagram

Figure 4 illustrates the block diagram of the AP33771 evaluation board, showing the functional interconnections.

Figure 4 - Block diagram of the AP33771 evaluation board

The diagram depicts the USB Type-C connector feeding into the AP33771 IC. The AP33771 manages VBUS, V5V, VSEL pins, and PSEL pin. It controls NMOS switches that connect to the Load. Pull-down resistors (Rd) are shown on the CC1 and CC2 lines, essential for USB Type-C communication.

3.3 EVB Schematics

Figure 5 displays the schematics of the AP33771 Evaluation Board, accompanied by tables detailing PDO Selection, Power Capability, and Voltage Selection.

Figure 5 - Schematics of the AP33771 Evaluation Board With Tables of PDO Selection and Power Capability

The schematic shows the USB Type-C receptacle, the AP33771 IC (U1), various passive components (resistors R1-R33, capacitors C1-C5), LEDs (D1, D2), MOSFETs (Q1, Q2), and jumpers (J1, J3, J4). The included tables specify:

• Power Cap. Selection: Lists resistor values (R20-R29) for selecting power capabilities from 12W to 100W.
• Voltage Selection: Shows jumper settings (VSEL2, VSEL1, VSELO) corresponding to target voltages from 5V to 17.2V, including grant voltages with and without PPS.

3.4 EVB System BOM

Table 3 lists the Bill of Materials (BOM) for the AP33771 Evaluation Board.

Chapter 4. EVB Function Description

The AP33771 EVB allows users to configure USB-PD negotiation between a TCD device and an external PDC using simple resistor settings. If negotiation is successful, the PDC supplies the requested voltage and power to the TCD via VBUS through the Type-C cable. If negotiation fails, the PDC defaults to 5V PDO, and the LED flickers with a "Mismatch" pattern.

4.1 Board Outline

Figure 6 shows the AP33771 EVB outline and floor plan, with connector and jumper locations detailed in Table 2.

Figure 6 - Connector and jumper locations

This image highlights the physical placement of connectors and jumpers on the evaluation board, labeled J1, J2, J3, and J4.

4.2 Voltage Selection

Users can select the desired voltage by configuring jumpers at J4, which connects to the VSEL2~VSEL0 pins of the AP33771. Table 3 lists the voltage selections.

The top four rows of Table 3 correspond to standard Fixed PDO voltages: 5V, 9V, 15V, and 20V. The bottom four rows enable selection of voltages like 4.3V, 8.6V, 12.9V, and 17.2V, suitable for multi-cell Lithium-Ion battery applications. Users can choose the appropriate resistor setting at J4 for their desired voltage.

Note: If VSEL2 is ON (VSEL2 = 1), only sources with PPS APDO are supported.

4.3 Power Capability Selection

The AP33771 requests the corresponding voltage from the external PD Charger's (PDC) PDO capabilities. During voltage selection, PPS Augmented PDO (APDO) has higher priority than Fixed PDO.

Required power capability is selected via the J3 connector, where a resistor connects to the PSEL pin of the AP33771. The AP33771 uses its constant current source output (20µA±3.0%) at the PSEL pin and the external resistor to determine voltage, which the internal ADC measures to select the corresponding power capability. Users can select an appropriate resistor via a jumper to achieve the desired power capability, as per Table 4.

The AP33771 also verifies if the source power is sufficient for the selected power level set by the J3 jumper. If the source power is lower than the selected power, negotiation results in a power mismatch, the AP33771 disables the MOS switch, and the LED flickers with a "Mismatch" pattern.

For current capabilities exceeding 3A, an e-Marker Type-C cable is required. According to the USB PD protocol, the PD source adapter checks the cable's power capability reported by the e-Marker.

Designers of TCDs are advised to use resistors with ±1% accuracy for the PSEL pin connection.

Chapter 5. Built-In Application Firmware Features

5.1 Firmware Overview and LED Indication

The AP33771 features built-in firmware capable of intelligently managing various usage scenarios. Figure 7 illustrates the state transition diagram.

Figure 7 - AP33771 state diagram

This diagram shows the operational states of the AP33771, including INIT, CHARGING, LOW_CURR, LOW_VOLT, MISMATCH, and FAULT, along with the conditions that trigger transitions between these states.

The AP33771 controls LED lighting via GPIO4. Table 5 summarizes the transition conditions, LED indications, and VOUT status for each state.

5.2 PDO Selection Scheme

During PD negotiation, the AP33771 evaluates all PDOs discovered from the PD Source's capability to find the best match with VSEL/PSEL settings, as outlined in Table 6. Subsequently, it enables the associated MOS switches, connecting VBUS to VOUT when both voltage and power selections match.

If multiple PDOs match, PPS PDOs take precedence over Fixed PDOs. If multiple PPS PDOs match, the lowest voltage PPS PDO is selected first. If no PDO matches, the AP33771 requests the 1st PDO (5V) and enters the MISMATCH state. If the source is not PD capable and VSEL is not set to 5V, the AP33771 enters the MISMATCH state (refer to Section 5.5).

Note:

• VVSEL: Selected Voltage by VSEL
• PPSEL: Selected Power by PSEL
• VFIXED: Voltage of Fixed PDO
• VPPSMIN: Minimum Voltage of PPS PDO
• VPPSMAX: Maximum Voltage of PPS PDO
• VPROG: Nominal Voltage of PPS
• IMAX: Maximum Current of PDO/APDO

Table 7 presents the minimum and maximum voltages for the Programmable Power Supply corresponding to the Nominal Voltage, extracted from the USB-PD Specification.

5.3 Over Voltage Protection (OVP)

The AP33771 triggers OVP protection when the VBUS voltage exceeds the OVP threshold voltage. Table 8 shows the correspondence between VSEL pin combinations (VSEL2, VSEL1, VSEL0), the selected voltage (VVSEL), and the OVP Threshold Voltage.

The OVP de-bounce time mechanism prevents false triggering from spurious noises and is set to 30ms by default. If the VBUS voltage remains above the OVP threshold after this time, the AP33771 enters the FAULT state, disabling the output enable MOS switches and causing the LED to flicker with a "Fault" pattern.

5.4 Automatic Type C-to-C Cable Voltage Drop Compensation

After negotiation completion and MOS switch enablement, the AP33771 monitors the VOUT voltage level (VVOUT), which is the voltage at the J1 Load Connector (Figure 6). If the VOUT voltage falls more than 6% below the VVSEL Selected Voltage, the AP33771 activates the Automatic Type C Cable Voltage Drop Compensation mechanism for cases where VSEL2 is 0. Table 9 specifies this compensation.

Notes:

• ⁽¹⁾ Allows PDO 5V to be raised to 9V only, preventing potential damage to the charging circuit by allowing higher PDOs (15V, 20V).
• ⁽²⁾ Type C-to-C cables have a typical end-to-end resistance of 250mΩ. The maximum allowed voltage drop compensation is 1.3V for a Type C-to-C cable, ensuring it stays within 1.25V for a maximum current of 5A.
• ⁽³⁾ AP33771 enables Voltage Drop Compensation when VSEL2 is 0 (VVSEL=5V/9V/15V/20V) and VVOUT < VVSEL * (1 - 6%).

The criteria for enabling Voltage Drop Compensation vary with the VVSEL Selected Voltage. Table 10 details the correspondence between Selected Voltage and Compensation Criteria.

Table 11 provides examples of Type C-to-C Cable Voltage Drop Compensation situations, based on the source PDO (Fixed or PPS) and the AP33771's chosen compensation method.

Notes:

• If the cable voltage drop from the source-end to the sink-end is 1.0V:
• ⁽¹⁾ Adjusted VARequest would be 9V and VVOUT would be 8V.
• ⁽²⁾ Adjusted VARequest would be 5.7V for VVOUT to reach 4.7V.

If Voltage Drop Compensation fails (no suitable PDO found or compensation exceeds the upper limit), the AP33771 transitions to the LOW_VOLT state.

5.5 Legacy Type A Charger with Type A-to-C Cable

When the energy source is a legacy Type A charger connected via a Type A-to-C cable, the AP33771 enters Non-PD Mode after PD negotiation fails. Table 12 shows the Non-PD Mode states of the AP33771 after PD negotiation and compensation.

If VSEL is 5V and VOUT voltage is higher than 4.7V, the AP33771 enters the CHARGING state. If VSEL is 5V and VOUT voltage is lower than 4.7V, it enters the LOW_VOLT state. If VSEL is not 5V, the AP33771 enters the MISMATCH state.

Chapter 6. USB Type C-to-C PD Sink-Source Application Examples

Cases 1 through 6 in this chapter demonstrate various scenarios and procedures for requesting power profiles from a TCD and matching them with a power source's (PDC) capability to establish charging states, as illustrated in Figure 8.

Figure 8 - Examples Based on a Typical TCD Application Scenario with an USB PDC

This diagram shows a TCD device connected to a USB PDC via a Type-C cable, representing a typical USB PD application setup.

Case 1: PDC=36W, TCD = 15V and 36W

PDC: 36W, PDO: 5V/3A, 9V/3A, 15V/2.4A, APDO: None

TCD Settings: VSEL2=0, VSEL1=1, VSEL0=0 (for 15V), RPSEL=56KΩ (for 36W)

A TCD requests 15V and 36W from a 36W PDC source with fixed PDOs (5V/3A, 9V/3A, 15V/2.4A).

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 56 KΩ ±1% resistor to PSEL (Selection No. 6 in Table-4).
3. The AP33771 initiates handshake with the powered PDC upon Type-C cable connection.
4. VBUS becomes 15V as the 15V/2.4A PDO is matched.
5. VOUT becomes 15V as Power and Voltage match, enabling the MOS switches.

Case 2: PDC=36W, TCD = 15V and 45W

PDC: 36W, PDO: 5V/3A, 9V/3A, 15V/2.4A, APDO: None

TCD Settings: VSEL2=0, VSEL1=1, VSEL0=0 (for 15V), RPSEL=65KΩ (for 45W)

A TCD requests 15V and 45W from a 36W PDC source with fixed PDOs (5V/3A, 9V/3A, 15V/2.4A).

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 65 KΩ ±1% resistor to PSEL (Selection No. 7 in Table-4).
3. The AP33771 initiates handshake with the powered PDC upon Type-C cable connection.
4. VBUS becomes 15V as the 15V/2.4A PDO is matched.
5. VOUT remains 0V because Power and Voltage do not fully match, preventing MOS switch enablement.

Case 3: PDC=36W, TCD = 15V and 36W

PDC: 36W, PDO: 5V/3A, 9V/3A, 15V/2.4A, APDO: 5V Prog/3A, 9V Prog/3A, 15V Prog/2.4A

TCD Settings: VSEL2=0, VSEL1=1, VSEL0=0 (for 15V), RPSEL=56KΩ (for 36W)

A TCD requests 15V and 36W from a 36W PDC source with fixed PDOs and APDOs.

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 56 KΩ ±1% resistor to PSEL (Selection No. 6 in Table-4).
3. The AP33771 initiates handshake with the powered PDC upon Type-C cable connection.
4. VBUS becomes 15V as the APDO 15V Prog/2.4A is matched (APDO has higher priority).
5. VOUT becomes 15V as Power and Voltage match, enabling the MOS switches.

Case 4: PDC=36W, TCD = 12.9V and 36W

PDC: 36W, PDO: 5V/3A, 9V/3A, 15V/2.4A, APDO: 5V Prog/3A, 9V Prog/3A, 15V Prog/2.4A

TCD Settings: VSEL2=1, VSEL1=1, VSEL0=0 (for 12.9V), RPSEL=56KΩ (for 36W)

A TCD requests 15V and 36W from a 36W PDC source with fixed PDOs and APDOs.

1. Set SEL2~SEL0 to "110" for 12.9V (Selection No. 7 in Table-3).
2. Connect a 56 KΩ ±1% resistor to PSEL (Selection No. 6 in Table-4).
3. The AP33771 initiates handshake with the powered PDC upon Type-C cable connection.
4. VBUS becomes 12.9V as the APDO 15V Prog/2.4A is matched (APDO has higher priority).
5. VOUT becomes 12.9V as Power and Voltage match, enabling the MOS switches.

Case 5: PDC=36W, TCD = 15V and 45W

PDC: 36W, PDO: 5V/3A, 9V/3A, 15V/2.4A, APDO: 5V Prog/3A, 9V Prog/3A, 15V Prog/2.4A

TCD Settings: VSEL2=0, VSEL1=1, VSEL0=0 (for 15V), RPSEL=65KΩ (for 45W)

A TCD requests 15V and 45W from a 36W PDC source with fixed PDOs and APDOs.

1. Set SEL2~SEL0 to "010" for 15V (Selection No. 3 in Table-3).
2. Connect a 65 KΩ ±1% resistor to PSEL (Selection No. 7 in Table-4).
3. The AP33771 initiates handshake with the powered PDC upon Type-C cable connection.
4. VBUS becomes 15V as the APDO 15V Prog/2.4A is matched (APDO has higher priority).
5. VOUT remains 0V because Power and Voltage do not fully match, preventing MOS switch enablement.

Case 6: PDC=36W, TCD = 12.9V and 36W

PDC: 36W, PDO: 5V/3A, 9V/3A, 15V/2.4A, APDO: None

TCD Settings: VSEL2=1, VSEL1=1, VSEL0=0 (for 12.9V), RPSEL=56KΩ (for 36W)

A TCD requests 12.9V and 36W from a 36W PDC source with fixed PDOs (5V/3A, 9V/3A, 15V/2.4A).

1. Set SEL2~SEL0 to "110" for 12.9V (Selection No. 7 in Table-3).
2. Connect a 56 KΩ ±1% resistor to PSEL (Selection No. 6 in Table-4).
3. The AP33771 initiates handshake with the powered PDC upon Type-C cable connection.
4. VBUS becomes 5V because no PDO matches the 12.9V request, and 5V is supported instead, per PD rules.
5. VOUT remains 0V because Power and Voltage do not fully match, preventing MOS switch enablement.

Chapter 7. Compliance test

The AP33771 EVB successfully passed all test items on the Ellisys USB-PD Compliance tester, as indicated below.

Figure 9 - Ellisys USB PD Test Environment and Test Item List

This image shows a screenshot of the Ellisys USB Explorer 350 Examiner software, listing various USB PD and USB Type-C compliance tests. The summary indicates 145 tests were run, with 0 failures and 0 tests not completed, confirming all tests were completed successfully. The test environment includes a Generator, Analyzer, Control Computer, and the Device Under Test, all part of the Ellisys System.

Chapter 8. Design Considerations

8.1 Termination of CC1/CC2 channels

The AP33771 lacks internal Rd resistors. Designers must install 5.1K ohm resistors on both CC1 and CC2 to GND. Without these resistors, the AP33771 may misinterpret the CC line direction, preventing PD negotiation.

Figure 10 - Make sure the connection of external Rd resistors on CC1 and CC2

This diagram shows the essential connection of external 5.1KΩ resistors (R1, R2) from CC1 and CC2 pins to GND, alongside a partial view of the AP33771 IC pinout.

8.2 ESD Considerations

The AP33771 EVB is designed for functional evaluation and does not include on-board ESD protection components. Do not use the AP33771 EVB for ESD testing. For manufacturing, users should incorporate suitable ESD protection devices or optimize their PCB design.

Chapter 9. Revision History

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