65W Dual Port PD3.0 GaN Base Adapter EVB4 User Guide

Chapter 1: Summary

The 65W 70CC Dual Type C Ports PD3.0 PPS Evaluation Board (EVB4) integrates four main controllers: Diodes™ AP33510, Diodes™ APR349, Diodes™ AP43771V, and Canyon Semiconductor's CY6572. The AP33510 is a Quasi-Resonant (QR) controller with direct E-GaN driver integration, designed for ultra-low standby power and high power density (HPD) chargers. The APR349 is a secondary side Synchronous Rectification (SR) Controller for efficiency optimization. The AP43771V is a PD3.0 PPS protocol controller that manages the PD3.0 PPS attachment process and regulates voltage and current requirements from the connected device. The CY6572 is a synchronous buck controller. This board enables smart power sharing between two ports when both are inserted. Utilizing E-GaN FETs, the EVB4 exemplifies high power density charger design with an optimized Bill of Materials (BOM) to meet market trends.

1.1 General Description

The evaluation board is designed for high-power density charger applications, supporting USB PD3.0 PPS with dual Type-C ports.

1.2 Key Features

1.2.1 System Key Features

• Quasi-Resonant operation for Critical E-GaN switch.
• Operation and Efficiency Improvement Approaches.
• Cost-Effective Implementation for HPD Chargers.
• High-Voltage Startup with low standby power (<20mW).
• Meets DOE VI and COC Tier 2 Efficiency Requirements.
• USB Type-C Port: Supports maximum output of 65W PD3.0 PPS (3.3V to 21V at 20mV/step, 50mA/step).
• SSR Topology Implementation with an Opto-coupler for Accurate Step Voltage/Current Control.
• Low overall system BOM cost.

1.2.2 AP33510 Key Features

• QR Flyback Topology with Valley-on and Valley lock.
• High-Voltage Startup.
• Embedded VCC LDO for VCCIN pin to Guarantee Wide Range Output Voltage.
• Integration of Accurate E-GaN direct-driver.
• Low Constant Output Current for Output Short.
• Non-Audible-Noise QR Control.
• Frequency Fold Back for High Average Efficiency.
• Secondary Winding Short Protection with FOCP.
• Soft Start During Startup Process.
• Frequency Dithering for Reducing EMI.
• Integration of X-CAP Discharge Function.
• Useful Pin fault protection: SENSE Pin Floating Protection / FB/Opto-Coupler Open/Short Protection.
• Comprehensive System Protection Feature: VOVP/OLP/BNO/SOVP/SUVP.

1.2.3 APR349 Key Features

• SR Works with CCM / DCM / QR operation modes.
• Eliminate Resonant Ringing Interference.
• Fewest External Components used.

1.2.4 AP43771V Key Feature

• Support USB PD Rev 3.0 V1.2.
• USB-IF PD3.0/PPS Certified TID 4312.
• Qualcomm QC5 Certified: QC20201127203.
• MTP for System Configuration.
• OTP for Main Firmware.
• Operating Voltage Range: 3.3V to 21V.
• Built-In Regulator for CV and CC Control.
• Programmable OVP/UVP/OCP/OTP.
• Support Power Saving Mode.
• External N-MOSFET Control for VBUS Power Delivery.
• Support e-Marker Cable Detection.
• QFN-14 and QFN-24.

1.2.5 CY6572 Key Feature

• Wide Input Voltage from 4.5V to 40V.
• Adjustable Switching Frequency to get high Efficiency.
• High Duty-Cycle Up to 99%.
• CC/CV Control.
• Auto Recovery after Faults.
• Thermal Enhanced TSSOP-14 Package.

1.3 Applications

Quick Charger with full power range of PD3.0 PPS.

1.4 Main Power Specifications

1.5 Evaluation Board Pictures

Visual representations of the evaluation board from various angles.

Chapter 2: Power Supply Specification

2.1 Specification and Test Results

2.2 Compliance

Chapter 3: Schematic

3.1 Board Schematic

Schematic diagram of the 65W PD3.0 PPS Adapter EVB3.

3.2 Bill of Material (BOM)

Main board BOM and Master/Slave daughter board BOM are listed with component designators, comments, footprints, and quantities.

3.3 Transformer Design

Details the transformer's schematic, structure, winding specifications, and pin definitions. Includes a diagram of the bobbin and its pin layout, along with primary inductance test conditions and ratings.

3.4 Schematics Description

3.4.1 AC Input Circuit & Differential Filter

The AC input circuit includes a fuse (F1) for overcurrent protection, common mode chokes (NF1, NF2) for noise suppression, and a bridge rectifier (BD1) to convert AC to DC. A Pi filter (CE1-CE3, L1, CE4, CE5) is used for filtering differential switching noise.

3.4.2 AP33510 PWM Controller

The AP33510 is a highly integrated Quasi Resonant Flyback (QR) controller with high-voltage start-up and X-Cap discharging functions. It features an integrated VCC LDO for stable voltage regulation and an embedded E-GaN driver for precise gate control of the Q1 GaN FET. It enters burst mode at no or light load to minimize standby power.

3.4.3 APR349 Synchronous Rectification (SR) MOSFET Driver

The APR349 is a secondary side SR controller designed to reduce rectifier power dissipation in QR/DCM/CCM operation.

3.4.4 AP43771V PD 3.0 Decoder Interface to CY6572 Sync Buck and Power Devices

Key pins of the AP43771V facilitate protocol decoding and regulation:

• CC1 & CC2 (Pins 11, 10): Provide channel communication link as per USB Type-C specification.
• Constant Voltage (CV): Senses VFB (pin 8) and compares with internal reference for CV compensation via OCDRV pin (pin 5). Firmware controls output voltage via CC1/CC2 communication.
• Constant Current (CC): Senses current via a sense resistor and compares with an internal reference voltage. Firmware controls output current via CC1/CC2 communication.
• OCDRV (Pin 5) to CY6572 COMP (Pin 4): Interface link from AP43771V's CC/CV loop to Sync Buck COMP pin for output CC/CV control, enabling desired Vbus voltage and current.
• PWR_EN (Pin 2) to N-MOSFET Gate: Turns on/off N-MOSFET (Q9) to enable/disable voltage output to Vbus.

3.4.5 Interface between Master and Slave Board

The master and slave boards communicate via I2C using AP43771V SDA & SDL pins (16, 17) for plug-in/out status and power sharing information.

Chapter 4: The Evaluation Board (EVB) Connections

4.1 EVB PCB Layout

PCB layout diagrams for the Main Board and Daughter Board/Master, including top, bottom, and mid views.

4.2 Quick Start Guide before Connection

Before testing the 65W EVB, prepare the following tools, software, and manuals. Consult USBCEE sales for details on the USBCEE PD3.0 Test Kit: USBCEE Power Adapter Tester (https://www.usbcee.com/product-details/4).

Required Items:

• USBCEE PAT Tester
• GUI Display (e.g., 04.75V)
• USB-A to Micro-B Cable
• Type-C Cable

Connection Steps:

1. Prepare a certified three-foot Type-C cable and a Standard-A to Micro-B Cable.
2. Connect the AC inputs (L & N wires) of the EVB to the AC power supply output.
3. Ensure the AC source is switched OFF or disconnected before proceeding.
4. Use a Type-C cable to connect the EVB's Type-C receptacles to the test kit.
5. Connect the output of the Type-C port and USB A-port to the E-load's + and - terminals using cables.

A diagram illustrates the test kit input and output connections, including the Type-C input port and Mini USB port for computer connection.

4.3 Connection with E-Load

A diagram illustrates the connection setup for testing, showing the PC, USB, Quick Charge Test Kit, Type-C Cable, Travel Charger, and Power Meter & Electronic Load, categorized into Power part and Protocol part.

Chapter 5: Testing the Evaluation Board

5.1 Input & Output Characteristics

5.1.1 Input Standby Power

Table showing Input Standby Power measurements at various input voltages and frequencies.

5.1.2 Average Efficiency at Different Loading

Tables detailing average efficiency at different loading conditions for single port output (20V/3.25A) and dual port output (11V/4A + 9V/2.2A, 15V/3A + 9V/2.2A) across various input voltages.

5.2 Key Performance Waveforms

5.2.1 65W PD3.0 System Start-up Time

A waveform shows the system turn-on time is 402ms at Full Load @ 90Vac.

5.2.2 Q1 / Q2 MOSFET Voltage Stress at Full Load @264Vac

Waveforms display the voltage stress for the primary side MOSFET (Q1) and secondary side SR MOSFET (Q2). Tables provide Vds_Max_Spec and Ratio of voltage stress for Q1 and Q2.

5.2.3 System Output Ripple & Noise with the Cable

Waveforms illustrate system output ripple and noise with the cable connected, measured at various output voltages and input conditions. Delta V (ΔV) values are provided for each measurement.

5.2.4 Dynamic load ----0% Load~100% Load, T=20mS, Rate=15mA/µS (PCB End)

Waveforms show dynamic load testing results at different output voltages (5V, 9V, 15V, 20V) under various input conditions. Tables summarize Vo Undershoot(V) and Vo Overshoot(V) values.

5.2.5 Output Voltage Transition Time from Low to High

Waveforms illustrate output voltage transition times (rise times) for various voltage changes (5V→9V, 9V→15V, 15V→20V).

5.2.6 Output Voltage Transition Time from High to Low

Waveforms illustrate output voltage transition times (fall times) for various voltage changes (20V→15V, 15V→9V, 9V→5V, 20V→5V).

5.2.7 Thermal Testing

Thermal testing results for the evaluation board under output conditions of 20V/3.25A. Tables show component temperatures at different main voltages (90Vac/60Hz, 264Vac/60Hz). Infrared images (Figures 43-47) display the temperature distribution on the top and bottom surfaces of the board under full load conditions.

5.3 EMI (Conduction) Testing

EMI conduction testing results are presented for 115Vac and 230Vac input conditions at an output of 20V/3.25A. Graphs show the conducted emissions levels against frequency, with comparison to EN55022 standards (Class A and Class B). Tables provide detailed trace data including frequency, level, and delta limit.