Intel logoIntel® FPGA P-Tile Avalon ®
Streaming IP rau PCI Express *
Tsim Example User Guide
Hloov tshiab rau Intel®
Quartus® Prime Design Suite: 21.3
Tus IP Version: 6.0.0
Cov neeg siv phau ntawv qhia

Cov ntsiab lus zais
1 Tsim Examplus piav qhia
2 Phau Ntawv Qhia Pib Ceev
3 P-tile Avalon Streaming IP rau PCI Express Tsim
4 Cov ntaub ntawv kho dua tshiab rau Intel P-Tile Avalon
5 Cov ntaub ntawv / Cov ntaub ntawv
5.1 Cov ntaub ntawv
6 Related Posts

Tsim Examplus piav qhia

1.1. Functional Description for Programmed Input/Output (PIO) Design Example

PIO design example ua lub cim xeeb hloov los ntawm tus tswv processor mus rau lub hom phiaj ntaus ntawv. Hauv no example, tus tswv tsev processor thov ib leeg-dword MemRd thiab emWr
TLPs.
PIO design example yeej tsim cov files tsim nyog los simulate thiab sau ua ke hauv Intel Prime software. Design example npog ntau qhov kev txwv. Txawm li cas los xij, nws tsis npog tag nrho cov kev ua tau zoo ntawm P-Tile Hard IP rau PCIe.
Qhov no tsim example suav nrog cov hauv qab no:

  • Lub generated P-Tile Avalon Streaming Hard IP Endpoint variant (DUT) nrog rau qhov koj teev. Cov khoom no tsav TLP cov ntaub ntawv tau txais mus rau PIO daim ntawv thov
  • PIO Daim Ntawv Thov (APPS) tivthaiv, uas ua qhov tsim nyog txhais lus ntawm PCI Express TLPs thiab yooj yim Avalon-MM sau thiab nyeem rau onchip nco.
  • Ib qho ntawm lub cim xeeb ntawm lub cim xeeb (MEM). Rau 1 × 16 tsim example, on-chip nco muaj ib tug 16 KB nco thaiv. Rau 2 × 8 tsim example, lub cim xeeb on-chip muaj ob lub cim xeeb 16 KB.
  • Reset Release IP: Tus IP no tuav lub tswj Circuit Court nyob rau hauv reset kom txog thaum lub cuab yeej tau nkag mus rau cov neeg siv hom. FPGA lees paub qhov INIT_DONE tso zis los qhia tias lub cuab yeej nyob hauv hom neeg siv. Lub Reset Release IP generates ib inverted version ntawm lub sab hauv INIT_DONE teeb liab los tsim cov nINIT_DONE tso zis uas koj yuav siv tau rau koj tsim.Lub nINIT_DONE teeb liab siab mus txog rau thaum tag nrho cov ntaus ntawv nkag mus rau cov neeg siv hom. Tom qab nINIT_DONE asserts (qis), tag nrho cov logic nyob rau hauv cov neeg siv hom thiab ua hauj lwm ib txwm. Koj tuaj yeem siv nINIT_DONE teeb liab hauv ib txoj hauv qab no:
    • Mus rau rooj vag ib qho sab nraud lossis sab hauv pib dua.
    • Txhawm rau nkag mus rau qhov chaw nkag nkag mus rau lub transceiver thiab I / O PLLs.
    • Txhawm rau nkag mus rau kev sau ntawv ua haujlwm ntawm kev tsim cov blocks xws li embedded memory blocks, lub xeev tshuab, thiab hloov cov npe.
    • Txhawm rau synchronously tsav sau npe pib dua cov tswv yim ports hauv koj tus qauv tsim.

Lub simulation testbench instantiates PIO tsim example thiab lub hauv paus chaw nres nkoj BFM los cuam tshuam nrog lub hom phiaj Endpoint.
Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
Daim ntawv pov thawj ISO 9001: 2015
Daim duab 1. Block Diagram rau Platform Designer PIO 1 × 16 Tsim Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 5

Daim duab 2. Block Diagram rau Platform Designer PIO 2 × 8 Tsim Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 6

Qhov kev xeem ntawv sau rau thiab nyeem cov ntaub ntawv rov qab los ntawm tib qhov chaw hauv lub cim xeeb ntawm lub cim xeeb. Nws sib piv cov ntaub ntawv nyeem rau qhov xav tau. Cov ntawv xeem, "Simulation nres vim ua tiav" yog tias tsis muaj qhov yuam kev tshwm sim. Lub P-Tile Avalon
Streaming tsim example txhawb cov kev teeb tsa hauv qab no:

  • Gen4 x16 Endpoint
  • Gen3 x16 Endpoint
  • Gen4 x8x8 Endpoint
  • Gen3 x8x8 Endpoint

Nco tseg: Lub simulation testbench rau PCIe x8x8 PIO tsim example yog configured rau ib tug PCIe x8 txuas txawm hais tias qhov tseeb tsim siv ob PCIe x8 txuas.
Nco tseg: Qhov no tsim example tsuas yog txhawb nqa qhov chaw nyob hauv Parameter Editor ntawm P-tile Avalon Streaming IP rau PCI Express.
Daim duab 3. Platform Designer System Cov ntsiab lus rau P-Tile Avalon Streaming PCI Express 1 × 16 PIO Tsim Example
Lub Platform Designer tsim cov qauv no mus txog Gen4 x16 variants.

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 7

Daim duab 4. Platform Designer System Cov ntsiab lus rau P-Tile Avalon Streaming PCI Express 2 × 8 PIO Tsim Example
Lub Platform Designer tsim cov qauv no mus txog Gen4 x8x8 variants.

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 8

1.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
SR-IOV design example ua lub cim xeeb hloov los ntawm tus tswv processor mus rau lub hom phiaj ntaus ntawv. Nws txhawb nqa txog li ob PFs thiab 32 VFs ib PF.
SR-IOV design example yeej tsim cov files tsim nyog los simulate thiab sau ua ke hauv Intel Quartus Prime software. Koj muaj peev xwm download tau lub compiled tsim rau
Intel Stratix® 10 DX Development Kit lossis Intel Agilex™ Development Kit.
Qhov no tsim example suav nrog cov hauv qab no:

  • Lub generated P-Tile Avalon Streaming (Avalon-ST) IP Endpoint variant (DUT) nrog rau qhov koj teev. Cov khoom no tsav cov ntaub ntawv TLP tau txais mus rau SR-IOV daim ntawv thov.
  • SR-IOV Daim Ntawv Thov (APPS), uas ua qhov tsim nyog txhais lus ntawm PCI Express TLPs thiab yooj yim Avalon-ST sau thiab nyeem rau ntawm lub cim xeeb ntawm lub cim xeeb. Rau SR-IOV APPS tivthaiv, lub cim xeeb nyeem TLP yuav ua kom tiav nrog cov ntaub ntawv.
    • Rau SR-IOV tsim example nrog ob PFs thiab 32 VFs ib PF, muaj 66 qhov chaw nco uas tus tsim example nkag tau. Ob lub PF tuaj yeem nkag mus rau ob qhov chaw nco, thaum 64 VFs (2 x 32) tuaj yeem nkag mus rau 64 qhov chaw nco.
  • Ib Reset Release IP.
    Lub simulation testbench instantiates SR-IOV tsim example thiab lub hauv paus chaw nres nkoj BFM los cuam tshuam nrog lub hom phiaj Endpoint.

Daim duab 5. Block Diagram for the Platform Designer SR-IOV 1×16 Design Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 1

Daim duab 6. Block Diagram for the Platform Designer SR-IOV 2×8 Design Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 2

Qhov kev xeem ntawv sau rau thiab nyeem cov ntaub ntawv rov qab los ntawm tib qhov chaw hauv lub cim xeeb ntawm 2 PFs thiab 32 VFs ib PF. Nws piv cov ntaub ntawv nyeem rau qhov xav tau
tshwm sim. Cov ntawv xeem, "Simulation nres vim ua tiav" yog tias tsis muaj qhov yuam kev tshwm sim.
SR-IOV design example txhawb cov kev teeb tsa hauv qab no:

  • Gen4 x16 Endpoint
  • Gen3 x16 Endpoint
  • Gen4 x8x8 Endpoint
  • Gen3 x8x8 Endpoint

Daim duab 7. Platform Designer System Cov ntsiab lus rau P-Tile Avalon-ST nrog SR-IOV rau PCI Express 1 × 16 Tsim Example

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 3

Daim duab 8. Platform Designer System Cov ntsiab lus rau P-Tile Avalon-ST nrog SR-IOV rau PCI Express 2 × 8 Tsim Example

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 4

Phau Ntawv Qhia Pib Ceev

Siv Intel Quartus Prime software, koj tuaj yeem tsim qhov programmed I/O (PIO) tsim example rau Intel FPGA P-Tile Avalon-ST Hard IP rau PCI Express * IP core. Tus tsim tsim example qhia txog qhov uas koj tau teev tseg. PIB example hloov cov ntaub ntawv los ntawm tus tswv processor mus rau lub hom phiaj ntaus ntawv. Nws yog qhov tsim nyog rau kev siv lowbandwidth. Qhov no tsim example yeej tsim cov files tsim nyog los simulate thiab sau ua ke hauv Intel Quartus Prime software. Koj tuaj yeem rub tawm cov qauv tsim rau koj FPGA Development Board. Txhawm rau rub tawm mus rau kev cai kho vajtse, hloov kho Intel Quartus Prime Chaw File (.qsf) nrog rau qhov tseeb pin assignments . Daim duab 9. Cov kauj ruam txhim kho rau Kev Tsim Example

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 9

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
Daim ntawv pov thawj ISO 9001: 2015
2.1. Directory Structure
Daim duab 10. Directory Structure for the Generated Design Example

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 10

2.2. Tsim cov Design Example
Daim duab 11. Cov txheej txheem

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 11

  1. Hauv Intel Quartus Prime Pro Edition software, tsim ib qhov project tshiab (File ➤ New Project Wizard).
  2. Qhia meej txog Cov Ntawv Qhia, Lub Npe, thiab Sab saum toj-Level Entity.
  3. Rau hom phiaj xwm, lees txais tus nqi pib, Qhov project Empty. Nyem Next.
  4. Rau Ntxiv Files nias Next.
  5. Rau Tsev Neeg, Ntaus Ntawv & Pawg Thawj Coj Hauv Tsev, xaiv Intel Agilex lossis Intel Stratix 10.
  6. Yog tias koj xaiv Intel Stratix 10 hauv cov kauj ruam kawg, xaiv Stratix 10 DX hauv Cov Khoom Siv rub-down.
  7. Xaiv Lub Hom Phiaj Ntaus rau koj tus qauv tsim.
  8. Nyem Ua kom tiav.
  9. Hauv IP Catalog nrhiav thiab ntxiv Intel P-Tile Avalon-ST Hard IP rau PCI Express.
  10. Hauv New IP Variant dialog box, qhia lub npe rau koj tus IP. Nyem Tsim.
  11. Nyob rau sab saum toj-Level Chaw thiab PCIe * Chaw tabs, qhia qhov tsis haum rau koj qhov kev hloov pauv IP. Yog tias koj siv SR-IOV tsim example, ua cov kauj ruam hauv qab no kom pab SR-IOV:
    a. Ntawm PCIe * Ntaus tab nyob rau hauv PCIe * PCI Express / PCI Peev Xwm tab, kos lub thawv Pab kom muaj ntau lub cev ua haujlwm.
    b. Ntawm PCIe* Multifunction thiab SR-IOV System Settings tab, khij lub npov Pab txhawb SR-IOV thiab qhia cov naj npawb ntawm PFs thiab VFs. Rau x8 configurations, khij lub thawv Pab kom ntau lub cev ua haujlwm thiab Pab kom SR-IOV kev txhawb nqa rau PCIe0 thiab PCIe1 tabs.
    c. Ntawm PCIe * MSI-X tab nyob rau hauv PCIe * PCI Express / PCI Peev Xwm tab, pab kom MSI-X feature raws li xav tau.
    d. Ntawm PCIe* Base Address Registers tab, qhib BAR0 rau ob qho tib si PF thiab VF.
    e. Lwm qhov kev teeb tsa parameter tsis txaus siab rau qhov kev tsim no example.
  12. Hauv Example Designs tab, xaiv cov hauv qab no:
    ib. Rau Examptsim Files, qhib cov kev xaiv Simulation thiab Synthesis.
    Yog hais tias koj tsis xav tau cov simulation los yog synthesis files, tawm hauv cov kev xaiv coj (s) muab tua ho txo ​​tus examplub sij hawm tsim tsim.
    b. Rau Generated HDL Format, tsuas yog Verilog muaj nyob rau hauv qhov kev tso tawm tam sim no.
    c. Rau Lub Hom Phiaj Txhim Kho Cov Khoom Siv, xaiv Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit, Intel Stratix 10 DX P-Tile Production FPGA Development Kit lossis Intel Agilex F-Series P-Tile ES0 FPGA Development Kit.
    13. Xaiv Tsim Example Design los tsim ib tug tsim example uas koj tuaj yeem simulate thiab rub mus rau hardware. Yog tias koj xaiv ib qho ntawm P-Tile txhim kho pawg thawj coj saib, cov cuab yeej ntawm lub rooj tsav xwm ntawd sau cov cuab yeej yav dhau los xaiv hauv Intel Quartus Prime qhov project yog tias cov khoom siv sib txawv. Thaum cov lus nug kom koj qhia cov npe rau koj tus example tsim, koj tuaj yeem lees txais cov npe ua ntej, ./intel_pcie_ptile_ast_0_example_design, lossis xaiv lwm phau ntawv.
    Daim duab 12. Example Designs Tab
    intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 12
  13. Nyem Ua kom tiav. Koj yuav txuag tau koj .ip file thaum prompted, tab sis nws tsis tas yuav tsum tau siv tus example design.
  14. Qhib tus example design project.
  15. Compile tus example tsim qhov project los tsim cov .sof file rau tag nrho example design. Qhov no file yog qhov koj rub tawm mus rau lub rooj tsavxwm los ua qhov kev kuaj xyuas kho vajtse.
  16. Kaw koj tus example design project.
    Nco ntsoov tias koj tsis tuaj yeem hloov pauv PCIe tus pin faib hauv Intel Quartus Prime qhov project. Txawm li cas los xij, kom yooj yim PCB routing, koj tuaj yeem siv advantage ntawm txoj kab thim rov qab thiab polarity inversion nta txhawb los ntawm tus IP no.

2.3. Simulating Design Example
Kev teeb tsa simulation suav nrog kev siv lub hauv paus Chaw nres nkoj Bus Functional Model (BFM) los siv P-tile Avalon Streaming IP rau PCIe (DUT) raws li qhia hauv qab no
daim duab.
Daim duab 13. PIB Design Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 13

Yog xav paub ntxiv txog qhov testbench thiab cov qauv hauv nws, xa mus rau Testbench ntawm nplooj 15.
Daim duab ntws hauv qab no qhia cov kauj ruam los simulate tus tsim example:
Daim duab 14. Txheej txheem

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 14

  1.  Hloov mus rau testbench simulation directory, /pcie_ed_tb/pcie_ed_tb/sim/ / simulator.
  2. Khiav cov ntawv simulation rau lub simulator ntawm koj xaiv. Xa mus rau lub rooj hauv qab no.
  3. Txheeb xyuas cov txiaj ntsig.

Nco tseg: P-Tile tsis txhawb kev sib txuas PIPE simulations.
Table 1. Cov kauj ruam los khiav Simulation

Simulator Ua hauj lwm Directory Cov lus qhia
ModelSim* SE, Siemens* EDA QuestaSim*- Intel FPGA Edition <example_design>/pcie_ed_tb/ pcie_ed_tb/sim/mentor/ 1. Invoke vsim (los ntawm kev ntaus ntawv vsim, uas ua rau lub qhov rais console uas koj tuaj yeem khiav cov lus txib hauv qab no).
2. ua msim_setup.tcl
Nco tseg: Hloov pauv, tsis txhob ua Cov Kauj Ruam 1 thiab 2, koj tuaj yeem ntaus: vsim -c -do msim_setup.tcl.
3. ld_debug
4. khiav - tag nrho
5. Kev simulation ua tiav xaus nrog cov lus hauv qab no, "Simulation nres vim kev ua tiav tiav!"
VCS* <example_design>/pcie_ed_tb/ pcie_ed_tb/sim/synopsys/vcs 1. Hom sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS = "" USER_DEFINED_ELAB_OPTIONS = "-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS = ""
txuas ntxiv…
Simulator Ua hauj lwm Directory Cov lus qhia
    Lus Cim: Cov lus txib saum toj no yog ib kab lus txib.
2. Kev simulation ua tiav xaus nrog cov lus hauv qab no, "Simulation nres vim kev ua tiav tiav!"
Nco tseg: Txhawm rau khiav qhov simulation hauv kev sib tham sib, siv cov kauj ruam hauv qab no: (yog tias koj twb tsim simv ua tiav hauv hom tsis sib tham, rho tawm simv thiab simv.diadir)
1. Qhib vcs_setup.sh file thiab ntxiv qhov kev xaiv debug rau VCS hais kom ua: vcs -debug_access+r
2. Sau tus tsim example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS=”- xlrm\ uniq_prior_final” SKIP_SIM=1
3. Pib lub simulation hauv kev sib tham sib hom:
simv -gui &

Qhov no testbench simulates mus txog Gen4 x16 variant.
Cov ntawv qhia simulation, "Simulation nres vim ua tiav" yog tias tsis muaj qhov yuam kev tshwm sim.
2.3.1. Testbench
Lub testbench siv lub xeem tsav module, altpcietb_bfm_rp_gen4_x16.sv, los pib qhov kev teeb tsa thiab kev hloov pauv kev nco. Thaum pib, lub xeem tsav tsheb module qhia cov ntaub ntawv los ntawm lub hauv paus chaw nres nkoj thiab Endpoint Configuration Chaw sau npe, yog li ntawd koj muaj peev xwm correlated rau cov tsis koj teev siv lub Parameter Editor.
Cov example tsim thiab testbench yog dynamically generated raws li configuration uas koj xaiv rau P-Tile IP rau PCIe. Lub testbench siv cov kev txwv uas koj teev hauv Parameter Editor hauv Intel Quartus Prime. Qhov no testbench simulates mus txog ib tug × 16 PCI Express txuas siv lub serial PCI Express interface. Tus qauv tsim qauv tso cai rau ntau tshaj ib qho PCI Express txuas rau simulated ib zaug. Cov duab hauv qab no nthuav tawm qib siab view ntawm PIO design example.
Daim duab 15. PIB Design Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 15

Sab saum toj-theem ntawm testbench instantiates cov nram qab no lub ntsiab modules:

  • altpcietb_bfm_rp_gen4x16.sv —Qhov no yog lub hauv paus chaw nres nkoj PCIe BFM.
    //Directory path
    /intel_pcie_ptile_ast_0_example_design/pcie_ed_tb/ip/
    pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ptile_tbed_ /sim
  • pcie_ed_dut.ip: Qhov no yog qhov Endpoint tsim nrog cov kev txwv uas koj teev.
    //Directory path
    /intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
  • pcie_ed_pio0.ip: Cov qauv no yog lub hom phiaj thiab pib ua lag luam rau PIO tsim example.
    //Directory path
    /intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
  • pcie_ed_sriov0.ip: Cov qauv no yog lub hom phiaj thiab pib ua lag luam rau SR-IOV tsim example.
    //Directory path
    /intel_pcie_ptile_ast_0_example_design/ip/pcie_ed

Daim duab 16. SR-IOV Design Example Simulation Testbench

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 16

Tsis tas li ntawd, lub testbench muaj cov txheej txheem uas ua cov haujlwm hauv qab no:

  • Tsim lub moos siv rau Endpoint ntawm qhov xav tau ntau zaus.
  • Muab PCI Express rov pib dua thaum pib.

Yog xav paub ntxiv txog lub hauv paus chaw nres nkoj BFM, xa mus rau TestBench tshooj ntawm Intel FPGA P-Tile Avalon streaming IP rau PCI Express User Guide.
Cov ntaub ntawv ntsig txog
Intel FPGA P-Tile Avalon streaming IP rau PCI Express User Guide
2.3.1.1 ib. Test Tsav Module
Qhov kev xeem tsav tsheb module, intel_pcie_ptile_tbed_hwtcl.v, instantiates the toplevel BFM, altpcietb_bfm_top_rp.v.
BFM theem saum toj kawg nkaus ua tiav cov haujlwm hauv qab no:

  1. Instantiates tus tsav tsheb thiab saib xyuas.
  2. Instantiates lub hauv paus chaw nres nkoj BFM.
  3. Instantiates lub serial interface.

Lub configuration module, altpcietb_g3bfm_configure.v, ua cov haujlwm hauv qab no:

  1. Configures thiab muab cov BARs.
  2. Configures lub hauv paus chaw nres nkoj thiab Endpoint.
  3. Qhia qhov chaw Configuration Space, BAR, MSI, MSI-X, thiab AER nqis.

2.3.1.2. PIB Design Exampua Testbench

Daim duab hauv qab no qhia txog PIO tsim example simulation tsim hierarchy. Cov kev xeem rau PIO tsim example yog txhais nrog cov apps_type_hwtcl parameter teem rau
3. Cov kev xeem khiav raws li tus nqi parameter no tau txhais hauv ebfm_cfg_rp_ep_rootport, find_mem_bar thiab downstream_loop.
Daim duab 17. PIO Design Example Simulation Design Hierarchy

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 17

Lub testbench pib nrog kev cob qhia txuas thiab tom qab ntawd nkag mus rau qhov chaw teeb tsa ntawm IP rau kev suav sau. Ib txoj haujlwm hu ua downstream_loop (txhais tau nyob rau hauv qhov chaw nres nkoj hauv paus
PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) tom qab ntawd ua qhov kev sim PCIe txuas. Qhov kev xeem no muaj cov kauj ruam hauv qab no:

  1. Tshaj tawm lub cim xeeb sau cov lus txib kom sau ib lo lus ntawm cov ntaub ntawv rau hauv lub cim xeeb ntawm lub cim xeeb tom qab Endpoint.
  2. Tshaj tawm lub cim xeeb nyeem cov lus txib kom nyeem cov ntaub ntawv rov qab los ntawm lub cim xeeb ntawm lub cim xeeb.
  3. Sib piv cov ntawv nyeem nrog cov ntaub ntawv sau. Yog tias lawv phim, qhov kev xeem suav qhov no yog Pass.
  4. Rov ua kauj ruam 1, 2 thiab 3 rau 10 rov ua dua.

Thawj lub cim xeeb sau tau nyob ib ncig ntawm 219 peb. Nws yog ua raws li lub cim xeeb nyeem ntawm Avalon-ST RX interface ntawm P-tile Hard IP rau PCIe. Kev Ua tiav TLP tshwm sim sai tom qab lub cim xeeb nyeem ntawv thov ntawm Avalon-ST TX interface.
2.3.1.3. SR-IOV Design Exampua Testbench
Daim duab hauv qab no qhia txog SR-IOV tsim example simulation tsim hierarchy. Cov kev xeem rau SR-IOV tsim example tau ua los ntawm txoj haujlwm hu ua sriov_test,
uas yog txhais hauv altpcietb_bfm_cfbp.sv.
Daim duab 18. SR-IOV Design Example Simulation Design Hierarchy

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 18

Lub SR-IOV testbench txhawb nqa txog ob Lub Cev Muaj Zog (PFs) thiab 32 Virtual Functions (VFs) ib PF.
Lub testbench pib nrog kev cob qhia txuas thiab tom qab ntawd nkag mus rau qhov chaw teeb tsa ntawm IP rau kev suav sau. Tom qab ntawd, nws ua cov kauj ruam hauv qab no:

  1. Xa ib daim ntawv thov kev nco mus rau PF ua raws li lub cim xeeb nyeem thov kom nyeem rov qab cov ntaub ntawv qub rau kev sib piv. Yog hais tias cov ntaub ntawv nyeem sib phim cov ntaub ntawv sau, nws yog
    ib Pass. Qhov kev sim no yog ua los ntawm txoj haujlwm hu ua my_test (txhais hauv altpcietb_bfm_cfbp.v). Qhov kev sim no rov ua dua ob zaug rau txhua PF.
  2. Xa ib daim ntawv thov kev nco mus rau VF ua raws li lub cim xeeb nyeem thov kom nyeem rov qab cov ntaub ntawv qub rau kev sib piv. Yog hais tias cov ntaub ntawv nyeem sib phim cov ntaub ntawv sau, nws yog
    ib Pass. Qhov kev sim no yog ua los ntawm txoj haujlwm hu ua cfbp_target_test (txhais hauv altpcietb_bfm_cfbp.v). Qhov kev sim no rov ua dua rau txhua VF.

Thawj lub cim xeeb sau yuav tshwm sim nyob ib ncig ntawm 263 peb. Nws yog ua raws li lub cim xeeb nyeem ntawm Avalon-ST RX interface ntawm PF0 ntawm P-tile Hard IP rau PCIe. Kev Ua tiav TLP tshwm sim sai tom qab lub cim xeeb nyeem ntawv thov ntawm Avalon-ST TX interface.
2.4. Compiling tus Design Example

  1. Nkag mus rau /intel_pcie_ptile_ast_0_example_design/ thiab qhib pcie_ed.qpf.
  2. Yog tias koj xaiv ib qho ntawm ob qho khoom siv txhim kho hauv qab no, VID-txog kev teeb tsa muaj nyob hauv .qsf file ntawm generated tsim example, thiab koj tsis tas yuav ntxiv lawv manually. Nco ntsoov tias cov kev teeb tsa no yog lub rooj tsav xwm tshwj xeeb.
    • Intel Stratix 10 DX P-Tile ES1 FPGA cov khoom siv txhim kho
    • Intel Stratix 10 DX P-Tile Production FPGA cov khoom siv
    • Intel Agilex F-Series P-Tile ES0 FPGA cov khoom siv txhim kho
  3. Hauv cov ntawv qhia zaub mov, xaiv Start Compilation.

2.5. Txhim kho Linux Kernel Driver

Ua ntej koj tuaj yeem kuaj tus tsim example hauv hardware, koj yuav tsum nruab lub Linux ntsiav
tus tsav tsheb. Koj tuaj yeem siv tus tsav tsheb no los ua cov kev xeem hauv qab no:
• Kev xeem PCIe txuas uas ua tau 100 sau thiab nyeem
• Qhov chaw nco DWORD
nyeem thiab sau
• Configuration Space DWORD nyeem thiab sau
(1)
Tsis tas li ntawd, koj tuaj yeem siv tus tsav tsheb los hloov tus nqi ntawm cov kev txwv hauv qab no:
• Lub BAR tau siv
• Cov cuab yeej xaiv (los ntawm kev qhia lub tsheb npav, ntaus ntawv thiab ua haujlwm (BDF) tus lej rau
ntaus ntawv)
Ua kom tiav cov kauj ruam hauv qab no txhawm rau txhim kho kernel tsav tsheb:

  1. Mus rau ./software/kernel/linux hauv qab example design generation directory.
  2. Hloov cov kev tso cai ntawm kev teeb tsa, thauj khoom, thiab tshem tawm files:
    $ chmod 777 nruab load unload
  3. Nruab tus tsav tsheb:
    $ sudo ./install
  4. Txheeb xyuas tus tsav tsheb installation:
    $ lsmod | grep intel_fpga_pcie_drv
    Cov txiaj ntsig xav tau:
    intel_fpga_pcie_drv 17792 0
  5. Xyuas kom tseeb tias Linux paub txog PCIe tsim example:
    $ lspci -d 1172:000 -v | grep intel_fpga_pcie_drv
    Nco tseg: Yog tias koj tau hloov Tus Neeg Muag Khoom ID, hloov tus neeg muag khoom ID tshiab rau Intel's
    Tus neeg muag khoom ID hauv cov lus txib no.
    Cov txiaj ntsig xav tau:
    Kernel tsav tsheb siv: intel_fpga_pcie_drv

2.6. Khiav lub Design Example
Nov yog qhov kev sim ua haujlwm koj tuaj yeem ua ntawm P-Tile Avalon-ST PCIe tsim examples:

  1. Thoob plaws hauv phau ntawv qhia cov neeg siv no, cov ntsiab lus lo lus, DWORD thiab QWORD muaj tib lub ntsiab lus uas lawv muaj nyob rau hauv PCI Express Base Specification. Ib lo lus yog 16 ntsis, DWORD yog 32 ntsis, thiab QWORD yog 64 ntsis.

Table 2. Kev Xeem Ua Haujlwm Txhawb los ntawm P-Tile Avalon-ST PCIe Tsim Examples

 Kev ua haujlwm  Yuav tsum tau BAR Txhawb nqa los ntawm P-Tile Avalon-ST PCIe Tsim Example
0: Txuas xeem - 100 sau thiab nyeem 0 Yog lawm
1: Sau qhov chaw nco 0 Yog lawm
2: Nyeem qhov chaw nco 0 Yog lawm
3: Sau qhov chaw teeb tsa N/A Yog lawm
4: Nyeem qhov chaw teeb tsa N/A Yog lawm
5: Hloov BAR N/A Yog lawm
6: Hloov ntaus ntawv N/A Yog lawm
7: Qhib SR-IOV N/A Yog (*)
8: Ua qhov kev sim txuas rau txhua qhov kev ua haujlwm virtual uas muaj nyob rau ntawm lub cuab yeej tam sim no  N/A  Yog (*)
9: Ua DMA N/A Tsis muaj
10: Tawm program N/A Yog lawm

Nco tseg: (*) Cov kev sim no tsuas yog muaj thaum SR-IOV tsim example xaiv.
2.6.1. Khiav PIO Design Example

  1. Mus rau ./software/user/example sub design exampua directory.
  2. Compile tus tsim exampli kev thov:
    $ ua
  3. Khiav qhov kev xeem:
    $ sudo ./intel_fpga_pcie_link_test
    Koj tuaj yeem khiav Intel FPGA IP PCIe txuas kuaj hauv phau ntawv lossis hom tsis siv neeg. Xaiv los ntawm:
    • Hauv hom tsis siv neeg, daim ntawv thov cia li xaiv lub cuab yeej. Qhov kev sim xaiv Intel PCIe ntaus ntawv nrog BDF qis tshaj plaws los ntawm kev sib piv tus neeg muag khoom ID.
    Qhov kev xeem kuj xaiv qhov qis tshaj plaws muaj BAR.
    • Nyob rau hauv phau ntawv hom, qhov kev xeem queries koj rau lub tsheb npav, ntaus ntawv, thiab muaj nuj nqi thiab BAR.
    Rau Intel Stratix 10 DX lossis Intel Agilex Development Kit, koj tuaj yeem txiav txim siab qhov
    BDF los ntawm kev ntaus cov lus txib hauv qab no:
    $ lspci -d 1172:
    4. Ntawm no yog sample transcripts rau automatic thiab phau ntawv hom:
    Tsis siv neeg hom:

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 19intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 20

Kev ceev hom:

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 21

Cov ntaub ntawv ntsig txog
PCIe Link Inspector Tshajview
Siv PCIe Link Inspector los saib xyuas qhov txuas ntawm Lub Cev, Cov Ntaub Ntawv Txuas thiab Cov Txheej Txheem Kev Lag Luam.
2.6.2. Khiav SR-IOV Design Example

Nov yog cov kauj ruam los sim SR-IOV tsim exampntawm hardware:

  1. Khiav Intel FPGA IP PCIe txuas xeem los ntawm kev khiav lub sudo ./
    intel_fpga_pcie_link_test hais kom ua thiab xaiv qhov kev xaiv 1:
    manually xaiv ib lub cuab yeej.
  2. Nkag mus rau BDF ntawm lub cev muaj nuj nqi uas cov haujlwm virtual tau faib.
  3. Nkag mus rau BAR "0" mus rau cov ntawv qhia zaub mov.
  4. Nkag mus rau kev xaiv 7 kom pab SR-IOV rau lub cuab yeej tam sim no.
  5. Nkag mus rau tus naj npawb ntawm cov haujlwm virtual kom qhib rau lub cuab yeej tam sim no.
    intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 22
  6. Nkag mus rau qhov kev xaiv 8 los ua qhov kev sim txuas rau txhua qhov kev ua haujlwm virtual tau faib rau lub cev ua haujlwm. Daim ntawv thov txuas mus kuaj yuav ua 100 lub cim xeeb sau nrog ib tus dword ntawm cov ntaub ntawv txhua tus thiab tom qab ntawd nyeem cov ntaub ntawv rov qab los kuaj xyuas. Daim ntawv thov yuav luam tus naj npawb ntawm cov haujlwm virtual uas ua tsis tiav qhov kev sib txuas ntawm qhov kawg ntawm kev sim.
    intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 237. Hauv lub davhlau ya nyob twg tshiab, khiav lspci –d 1172: | grep -c "Altera" cov lus txib los txheeb xyuas qhov suav ntawm PFs thiab VFs. Cov txiaj ntsig xav tau yog cov lej ntawm cov lej ntawm lub cev ua haujlwm thiab tus lej ntawm cov haujlwm virtual.

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example- 24

P-tile Avalon Streaming IP rau PCI Express Tsim

Example User Guide Archives

Intel Quartus Prime Version Cov neeg siv phau ntawv qhia
21.2 P-tile Avalon Streaming IP rau PCI Express Design Example User Guide
20.3 P-tile Avalon Streaming IP rau PCI Express Design Example User Guide
20.2 P-tile Avalon Streaming IP rau PCI Express Design Example User Guide
20.1 P-tile Avalon Streaming IP rau PCI Express Design Example User Guide
19.4 P-tile Avalon Streaming IP rau PCI Express Design Example User Guide
19.1.1 P-tile Avalon Streaming IP rau PCI Express Design Example User Guide

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
ISO
9001:2015 ua
Sau npe

Cov ntaub ntawv kho dua tshiab rau Intel P-Tile Avalon

Streaming Hard IP rau PCIe Tsim Example User Guide

Cov ntaub ntawv Version Intel Quartus Prime Version IP Version Hloov
2021.10.04 21.3 6.0.0 Hloov cov kev txhawb nqa rau SR-IOV tsim example los ntawm Gen3 x16 EP thiab Gen4 x16 EP mus rau Gen3 x8 EP thiab Gen4 x8 EP nyob rau hauv Cov Lus Qhia Ua Haujlwm rau tib lub hauv paus I/O Virtualization (SR-IOV) Tsim Example ntu.
Ntxiv qhov kev txhawb nqa rau Intel Stratix 10 DX P-tile Ntau Lawm FPGA Kev Tsim Kho Cov Khoom Siv rau Kev Tsim Cov Qauv Example ntu.
2021.07.01 21.2 5.0.0 Tshem tawm cov simulation waveforms rau PIO thiab SR-IOV tsim examples los ntawm ntu Simulating Design Example.
Hloov kho cov lus txib kom tso saib BDF hauv ntu
Khiav PIO Design Example.
2020.10.05 20.3 3.1.0 Tshem tawm Cov Ntawv Sau Npe txij li Avalon Streaming tsim examples twb tsis muaj control register.
2020.07.10 20.2 3.0.0 Ntxiv simulation waveforms, kuaj cov ntaub ntawv piav qhia thiab kuaj cov txiaj ntsig piav qhia rau tus qauv tsim examples.
Ntxiv cov lus qhia simulation rau ModelSim simulator rau Simulating Tus Tsim Example ntu.
2020.05.07 20.1 2.0.0 Hloov kho cov ntaub ntawv npe rau Intel FPGA P-Tile Avalon streaming IP rau PCI Express Design Example Tus Neeg Siv Phau Ntawv Qhia kom ua tau raws li cov txheej txheem npe tshiab.
Hloov kho VCS sib tham sib hom simulation hais kom ua.
2019.12.16 19.4 1.1.0 Ntxiv SR-IOV tsim example piav.
2019.11.13 19.3 1.0.0 Ntxiv Gen4 x8 Endpoint thiab Gen3 x8 Endpoint rau cov npe ntawm kev txhawb nqa.
2019.05.03 19.1.1 1.0.0 Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
ISO
9001:2015 ua
Sau npe

Intel logoSYMBOL Online Version
intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Examplub icon Xa lus tawm tswv yim
PIB: 683038
UA-20234
Version: 2021.10.04

Cov ntaub ntawv / Cov ntaub ntawv

intel FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example [ua pdf] Cov neeg siv phau ntawv qhia
FPGA P-Tile, Avalon Streaming IP rau PCI Express Design Example, FPGA P-Tile Avalon Streaming IP rau PCI Express Design Example, FPGA P-Tile Avalon Streaming IP

Cov ntaub ntawv

Related Posts

Cia ib saib

Koj email chaw nyob yuav tsis raug luam tawm. Cov teb uas yuav tsum tau muaj yog cim *