Cov ntsiab lus zais
1 Intel F-Tile Interlaken FPGA IPDesign Example User Guide
2 1. Kev Qhia Tawm Pib Sai
3 2. Tsim Examplus piav qhia
4 3. F-Tile Interlaken Intel FPGA IP Tsim Example User Guide Archives
5 4. Cov ntaub ntawv kho dua tshiab rau F-Tile Interlaken Intel FPGA IP Tsim Example User Guide
6 Cov ntaub ntawv / Cov ntaub ntawv
6.1 Cov ntaub ntawv
7 Related Posts

Intel F-Tile Interlaken FPGA IPDesign Example User Guide

 

Hloov tshiab rau Intel® Quartus® Prime Design Suite: 21.4
Tus IP Version: 3.1.0

1. Kev Qhia Tawm Pib Sai

F-Tile Interlaken Intel® FPGA IP core muab lub simulation testbench thiab kho vajtse tsim example uas txhawb kev muab tso ua ke thiab kev sim kho vajtse. Thaum koj tsim tus tsim example, parameter editor cia li tsim cov files yuav tsum simulate, compile, thiab sim tus tsim.

The testbench thiab design example txhawb NRZ thiab PAM4 hom rau F-tile li.
F-Tile Interlaken Intel FPGA IP core tsim tsim examples rau cov nram qab no txhawb kev sib txuas ntawm cov kab thiab cov ntaub ntawv tus nqi.

Table 1. IP Txhawb Kev Sib Txuas ntawm Tus lej ntawm Txoj Kab thiab Cov Ntaub Ntawv Tus Nqi
Cov kev sib txuas hauv qab no tau txais kev txhawb nqa hauv Intel Quartus® Prime Pro Edition software version 21.4. Tag nrho
Lwm qhov kev sib txuas yuav tau txais kev txhawb nqa yav tom ntej ntawm Intel Quartus Prime Pro Edition.

FIG 1 IP txhawb nqa kev sib txuas ntawm cov kab thiab cov ntaub ntawv tus nqi

 

Daim duab 1. Kev Txhim Kho Cov kauj ruam rau tus tsim Example

FIG 2 Kev Txhim Kho Cov kauj ruam rau Kev Tsim Example

(1) Qhov kev hloov pauv no txhawb nqa Interlaken Look-aside Mode.
(2) Rau 10-txoj kab kev tsim qauv, F-cov nplais xav tau 12 txoj kab ntawm TX PMA txhawm rau ua kom muaj kev sib raug zoo transceiver clocking kom txo cov channel skew.

* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

F-Tile Interlaken Intel FPGA IP core tsim example txhawb cov yam ntxwv hauv qab no:

  • Internal TX to RX serial loopback mode
  • Tsis siv neeg tsim cov pob ntawv loj tas li
  • Basic packet checking peev xwm
  • Muaj peev xwm siv System Console los pib dua tus qauv tsim rau rov sim dua lub hom phiaj

Daim duab 2. High-level Block Diagram

FIG 3 High-level Block Diagram

Cov ntaub ntawv ntsig txog

  • F-Tile Interlaken Intel FPGA Tus Neeg Siv Phau Ntawv Qhia
  • F-Tile Interlaken Intel FPGA IP Tso Lus Sau

1.1. Hardware thiab Software Requirements
Mus kuaj tus example tsim, siv hardware thiab software hauv qab no:

  • Intel Quartus Prime Pro Edition software version 21.4
  • System console muaj nrog Intel Quartus Prime Pro Edition software
  • Ib qho kev txhawb nqa simulator:
    - Synopsys* VCS*
    - Synopsys VCS MX
    - Siemens* EDA ModelSim* SE or Questa*
    - Cadence * Xcelium *
  • Intel Agilex™ I-Series Transceiver-SoC Development Kit

1.2. Tsim tus Tsim
Daim duab 3. Cov txheej txheem

FIG 4 txheej txheem

Ua raws li cov kauj ruam no los tsim cov qauv tsim example and testbench:

  1. Hauv Intel Quartus Prime Pro Edition software, nyem File ➤ New Project Wizard los tsim ib txoj haujlwm tshiab Intel Quartus Prime, lossis nyem File ➤ Qhib Project qhib qhov project Intel Quartus Prime uas twb muaj lawm. Tus wizard qhia koj kom qhia meej lub cuab yeej.
  2. Qhia rau tsev neeg Agilex thiab xaiv cov cuab yeej nrog F-Tile rau koj tus qauv tsim.
  3. Hauv IP Catalog, nrhiav thiab nyem ob npaug rau F-Tile Interlaken Intel FPGA IP. Lub qhov rais tshiab IP Variant tshwm.
  4. Qhia lub npe saum toj kawg nkaus rau koj tus IP kev hloov pauv. Tus parameter editor txuag tus IP variation nqis hauv a file npe .ip ib.
  5. Nyem OK. Cov parameter editor tshwm.

Daim duab 4. Example Design Tab

Fig 5 Example Design Tab

6. Ntawm tus IP tab, qhia qhov tsis muaj rau koj qhov kev hloov pauv ntawm tus IP tseem ceeb.
7. Example Tsim tab, xaiv qhov kev xaiv Simulation los tsim cov testbench. Xaiv qhov kev xaiv Synthesis los tsim kho vajtse tsim example. Koj yuav tsum xaiv yam tsawg kawg ib qho ntawm Simulation thiab Synthesis kev xaiv los tsim cov qauv tsim example.
8. Rau Generated HDL hom, ob qho tib si Verilog thiab VHDL kev xaiv muaj.
9. Rau Lub Hom Phiaj Txhim Kho Cov Khoom Siv, xaiv Agilex I-Series Transceiver-SOC Development Kit.

Nco tseg: Thaum koj xaiv qhov Kev Xaiv Cov Khoom Siv Tsim Kho, cov haujlwm tus pin tau teeb tsa raws li Intel Agilex I-Series Transceiver-SoC Development Kit ntaus tus lej (AGIB027R31B1E2VR0) thiab yuav txawv ntawm koj lub cuab yeej xaiv. Yog tias koj npaj siab yuav sim tus qauv tsim ntawm cov khoom siv sib txawv ntawm PCB, xaiv Tsis muaj cov khoom siv txhim kho thiab ua tus pin tsim nyog hauv .qsf file
10. Nyem Tsim Example Design. Xaiv Example Design Directory window tshwm.
11. Yog tias koj xav hloov kho tus tsim example directory path or name from the defaults displayed (ilk_f_0_example_design), xauj rau txoj hauv kev tshiab thiab ntaus tus qauv tshiab exampnpe directory.
12. Nyem OK.

Nco tseg: Hauv F-Tile Interlaken Intel FPGA IP tsim example, SystemPLL yog instantiated tau, thiab txuas nrog F-Tile Interlaken Intel FPGA IP core. SystemPLL hierarchy txoj hauv kev tsim example yog:

example_design.test_env_inst.test_dut.dut.pl

SystemPLL hauv tus tsim example qhia tib yam 156.26 MHz siv moos raws li Transceiver.

1.3. Directory Structure
F-Tile Interlaken Intel FPGA IP core tsim cov hauv qab no files rau tus tsim
example:
Daim duab 5. Daim Ntawv Teev Npe

FIG 6 Directory Structure

Table 2. Hardware Design Example File Cov lus piav qhia
Cov no files yog inample_installation_dir>/ilk_f_0_example_design directory.

FIG 7 Hardware Design Example File Cov lus piav qhia

Rooj 3. Testbench File Kev piav qhia
Qhov no file yog nyob rau hauvample_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.

FIG 8 Testbench File Kev piav qhia

Table 4. Testbench Scripts
Cov no files yog inample_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.

FIG 9 Testbench Scripts

1.4. Simulating Design Exampua Testbench
Daim duab 6. Cov txheej txheem

FIG 10 Simulating Design Exampua Testbench

Ua raws li cov kauj ruam no los simulate lub testbench:

  1. Ntawm qhov hais kom ua, hloov mus rau testbench simulation directory. Txoj kev directory yogample_installation_dir>/example_design/testbench.
  2. Khiav cov ntawv simulation rau qhov kev txhawb nqa simulator ntawm koj xaiv. Cov ntawv sau ua ke thiab khiav lub testbench hauv lub simulator. Koj tsab ntawv yuav tsum kuaj xyuas tias SOP thiab EOP suav qhov sib tw tom qab simulation tiav.

Rooj 5. Cov kauj ruam los khiav Simulation

FIG 11 Cov kauj ruam los khiav Simulation

3. Txheeb xyuas cov txiaj ntsig. Kev simulation ua tiav xa thiab tau txais pob ntawv, thiab qhia tias "Test PASSED".
Testbench rau tus tsim example ua tiav cov haujlwm hauv qab no:

  • Instantiates F-Tile Interlaken Intel FPGA IP core.
  • Luam tawm PHY xwm txheej.
  • Tshawb xyuas metaframe synchronization (SYNC_LOCK) thiab lo lus (block) ciam teb
    (WORD_LOCK).
  • Tos rau tus kheej txoj kab yuav raug kaw thiab ua kom haum.
  • Pib kis pob ntawv.
  • Tshawb xyuas pob ntawv txheeb cais:
    - CRC24 yuam kev
    -SOPs
    — EOPs

Cov nram qab no sample cov zis qhia txog kev ua tiav simulation kev xeem khiav:

FIG 12 Cov kauj ruam los khiav Simulation

Nco tseg: Interlaken tsim example simulation testbench xa 100 pob ntawv thiab tau txais 100 pob ntawv.

Cov nram qab no sample cov zis qhia txog qhov kev simulation ua tau zoo khiav rau Interlaken Look-aside hom:

FIG 13 Cov kauj ruam los khiav Simulation

FIG 14 Cov kauj ruam los khiav Simulation

1.5. Compiling thiab Configuring Hardware Design Example

  1. Xyuas kom tus example tsim tiam ua tiav.
  2. Hauv Intel Quartus Prime Pro Edition software, qhib Intel Quartus Prime projectample_installation_dir>/example_design.qpf>.
  3. Nyob ntawm Kev ua haujlwm ntawv qhia zaub mov, nyem Pib Compilation.
  4. Tom qab kev ua tiav tiav, a .sof file muaj nyob rau hauv koj daim ntawv teev npe.
    Ua raws li cov kauj ruam no rau kev pab cuam hardware example tsim ntawm Intel Agilex ntaus ntawv nrog F-tile:
    ib. Txuas cov khoom siv txhim kho mus rau lub khoos phis tawm.
    b. Tua tawm daim ntawv thov Clock Control, uas yog ib feem ntawm cov khoom siv txhim kho. Teem tshiab zaus rau tus tsim exampli nram no:
    • Rau NRZ hom:
    - Si5391 (U18), OUT0: Teem rau tus nqi ntawm pll_ref_clk(3) ib qho koj xav tau tsim.
    • Rau hom PAM:
    - Si5391 (U45), OUT1: Teem rau tus nqi ntawm pll_ref_clk(3) ib qho koj xav tau tsim.
    - Si5391 (U19), OUT1: Teem rau tus nqi ntawm mac_pll_ref_clk(3) raws li koj xav tau tsim. c. Nyem Cov cuab yeej ➤ Programmer ➤ Hardware Setup.
    d. Xaiv ib lub programming ntaus ntawv. Ntxiv Intel Agilex I-Series Transceiver-SoC Development Kit.
    e. Xyuas kom meej tias Hom yog teem rau JTAG.
    f. Xaiv Intel Agilex I-Series ntaus ntawv thiab nyem Ntxiv Device. Tus programmer qhia ib daim duab ntawm kev sib txuas ntawm cov khoom siv ntawm koj lub rooj tsavxwm.
    g. Kos lub thawv rau lub .sof.
    h. Kos lub thawv hauv lub Program/Configure kem.
    i. Nyem Pib.

1.6. Testing Hardware Design Example
Tom qab koj suav nrog F-tile Interlaken Intel FPGA IP tsim example thiab teeb tsa koj lub cuab yeej, koj tuaj yeem siv System Console los ua qhov kev pab cuam IP core thiab nws cov npe.

Ua raws li cov kauj ruam no coj mus rau System Console thiab sim kho vajtse tsim example:

FIG 15 Testing the Hardware Design Example

FIG 16 Testing the Hardware Design Example

  • Tsis muaj qhov yuam kev rau CRC32, CRC24, thiab checker.
  • Kev xa tawm SOPs thiab EOPs yuav tsum sib phim nrog SOPs thiab EOPs tau txais.

Cov nram qab no sample cov zis qhia txog qhov kev sim ua tiav hauv Interlaken hom:

FIG 17 Testing the Hardware Design Example

Cov nram qab no sample cov zis qhia txog qhov kev sim ua tiav hauv Interlaken Lookaside hom:

FIG 18

 

2. Tsim Examplus piav qhia

Design example qhia txog kev ua haujlwm ntawm Interlaken IP core.

2.1. Tsim Exampcov Components
Cov example tsim txuas qhov system thiab PLL siv moos thiab cov khoom tsim tsim. Cov example tsim configures tus IP core nyob rau hauv internal loopback hom thiab generates packets ntawm tus IP core TX cov neeg siv cov ntaub ntawv hloov lwm lub tsev interface. IP tub ntxhais xa cov pob ntawv no rau ntawm txoj hauv kev rov qab los ntawm lub transceiver.

Tom qab tus IP tub ntxhais txais tau txais cov pob ntawv ntawm txoj kev rov qab, nws ua cov pob ntawv Interlaken thiab xa lawv ntawm RX cov neeg siv cov ntaub ntawv hloov chaw. Cov example tsim kuaj xyuas tias cov pob ntawv tau txais thiab kis sib tw.

F-Tile Interlaken Intel FPGA IP tsim example suav nrog cov hauv qab no:

  1. F-Tile Interlaken Intel FPGA IP tub ntxhais
  2. Packet Generator thiab Packet Checker
  3. F-Tile Reference thiab System PLL Clocks Intel FPGA IP core

2.2. Tsim Exampua Flow
F-Tile Interlaken Intel FPGA IP kho vajtse tsim example ua kom tiav cov kauj ruam hauv qab no:

  1. Rov pib dua F-tile Interlaken Intel FPGA IP thiab F-Tile.
  2. Tso rov pib dua ntawm Interlaken IP (system reset) thiab F-tile TX (tile_tx_rst_n).
  3. Configures F-tile Interlaken Intel FPGA IP nyob rau hauv hom rov qab sab hauv.
  4. Tso qhov rov pib dua ntawm F-tile RX (tile_rx_rst_n).
  5. Xa cov kwj ntawm Interlaken pob ntawv nrog cov ntaub ntawv teev tseg ua ntej hauv kev them nyiaj rau TX tus neeg siv cov ntaub ntawv hloov chaw ntawm IP core.
  6. Xyuas cov pob ntawv tau txais thiab qhia txog xwm txheej. Cov pob ntawv checker suav nrog hauv kev tsim kho vajtse example muab cov peev txheej hauv qab no kuaj pob ntawv:
    • Xyuas seb cov pob ntawv kis tau zoo li cas.
    • Tshawb xyuas tias cov ntaub ntawv tau txais yog sib npaug ntawm cov txiaj ntsig uas xav tau los ntawm kev ua kom ob qho tib si pib ntawm pob ntawv (SOP) thiab qhov kawg ntawm pob ntawv (EOP) suav nrog thaum cov ntaub ntawv raug xa mus thiab tau txais.

* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

2.3. Interface Signals
Table 6. Tsim Example Interface Signals

FIG 19 Design Example Interface Signals

2.4. Sau npe daim ntawv qhia

Nco tseg:

  • Tsim Example sau npe chaw nyob pib nrog 0x20** thaum Interlaken IP core register chaw nyob pib nrog 0x10**.
  • F-tile PHY sau npe chaw nyob pib nrog 0x30** thaum F-tile FEC sau npe chaw nyob pib nrog 0x40**. FEC sau npe tsuas yog muaj nyob rau hauv PAM4 hom.
  • Nkag mus rau code: RO—Nyeem nkaus xwb, thiab RW—Nyeem/Sau.
  • System console nyeem tus tsim example sau npe thiab tshaj tawm cov xwm txheej xeem ntawm qhov screen.

Table 7. Tsim Example Register Map

FIG 20 Design Example Register Map

FIG 21 Design Example Register Map

FIG 22 Design Example Register Map

Table 8. Tsim Example Register Map for Interlaken Look-aside Design Example
Siv daim ntawv teev npe no thaum koj tsim tus tsim example nrog Enable Interlaken Look-aside Mode parameter qhib.

FIG 24 Design Example Register Map for Interlaken Look-aside Design Example

FIG 25 Design Example Register Map for Interlaken Look-aside Design Example

FIG 26 Design Example Register Map for Interlaken Look-aside Design Example

2.5. Rov pib dua
Hauv F-Tile Interlaken Intel FPGA IP core, koj pib rov pib dua (reset_n=0) thiab tuav kom txog thaum tus tub ntxhais IP rov qab lees paub (reset_ack_n=0). Tom qab rov pib dua raug tshem tawm (reset_n=1), qhov rov qab lees paub rov qab mus rau nws lub xeev thawj (reset_ack_n=1). Hauv kev tsim example, tus sau npe rst_ack_sticky tuav qhov kev lees paub rov pib dua thiab tom qab ntawd ua rau kev tshem tawm ntawm qhov pib dua (reset_n=1). Koj tuaj yeem siv lwm txoj hauv kev uas haum rau koj cov kev xav tau tsim.

Tseem ceeb: Nyob rau hauv txhua qhov xwm txheej uas yuav tsum tau muaj nyob rau hauv serial loopback, koj yuav tsum tso TX thiab RX ntawm F-tile cais nyob rau hauv ib qho kev txiav txim. Xa mus rau qhov system console tsab ntawv yog xav paub ntxiv.

Daim duab 7. Reset Sequence hauv NRZ hom

FIG 27 Reset Sequence in NRZ Mode

Daim duab 8. Reset Sequence hauv PAM4 hom

FIG 28 Reset Sequence in NRZ Mode

 

3. F-Tile Interlaken Intel FPGA IP Tsim Example User Guide Archives

Yog tias tus IP core version tsis tau teev tseg, cov lus qhia siv rau tus IP core version dhau los siv.

FIG 29 Reset Sequence in NRZ Mode

 

4. Cov ntaub ntawv kho dua tshiab rau F-Tile Interlaken Intel FPGA IP Tsim Example User Guide

FIG 30 Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau F-Tile Interlaken Intel FPGA IP Tsim Example User Guide

 

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel tau lees paub qhov ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau tam sim no
specifications raws li Intel tus qauv warranty, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pab cuam txhua lub sij hawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.

 

Nyeem ntxiv Txog Phau Ntawv Qhia no & Download PDF:

Cov ntaub ntawv / Cov ntaub ntawv

Intel F-Tile Interlaken FPGA IPDesign Example [ua pdf] Cov neeg siv phau ntawv qhia
F-Tile Interlaken FPGA IPDesign Example

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