Low Lairi E-Tile 40G àjọlò Intel FPGA IP Design Eksample
Quick Bẹrẹ Itọsọna
Low Latency E-Tile 40G Ethernet Intel® FPGA IP mojuto n pese aaye idanwo kikopa ati apẹrẹ ohun elo kan tẹlẹ.ample ti o atilẹyin akopo ati hardware igbeyewo. Nigbati o ba ṣe ina apẹrẹ example, Intel Quartus® Prime IP paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware. Ni afikun, o le ṣe igbasilẹ apẹrẹ ohun elo ti a ṣakojọ si ohun elo idagbasoke kan pato ẹrọ Intel fun idanwo interoperative. Intel FPGA IP tun pẹlu akopọ-nikan example ise agbese ti o le lo lati ni kiakia siro IP mojuto agbegbe ati ìlà. Low Lairi E-Tile 40G Ethernet Intel FPGA IP ṣe atilẹyin apẹrẹ example iran pẹlu kan jakejado ibiti o ti sile. Sibẹsibẹ, apẹrẹ examples ko bo gbogbo awọn ti ṣee parameterizations ti Low Lairi E-Tile 40G àjọlò Intel FPGA IP mojuto.
Awọn Igbesẹ Idagbasoke fun Oniru Example
Alaye ti o jọmọ
- Low Lairi E-Tile 40G àjọlò Intel FPGA IP Itọsọna olumulo
Fun alaye alaye lori Low Latency E-Tile 40G Ethernet IP. - Low Lairi E-Tile 40G àjọlò Intel FPGA IP Awọn akọsilẹ Tu
Awọn akọsilẹ Itusilẹ IP ṣe atokọ awọn iyipada IP ni idasilẹ kan pato.
Ti o npese awọn Design Example
Ilana
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
Example Design Tab ni Low Lairi E-Tile 40G àjọlò Parameter Olootu
Yan Stratix 10 TX E-Tile Transceiver Signal Integrity Development Apo lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample fun Intel Stratix® 10 awọn ẹrọ. Yan Agilex F-jara Transceiver-SoC Development Kit lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample fun awọn ẹrọ Intel Agilex™.
Tẹle awọn igbesẹ wọnyi lati ṣe ina apẹrẹ hardware example ati testbench:
- Ninu sọfitiwia Intel Quartus Prime Pro Edition, tẹ File ➤ New Project oso
lati ṣẹda titun kan Intel Quartus Prime ise agbese, tabi File ➤ Ṣii Project lati ṣii iṣẹ sọfitiwia Intel Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati tokasi idile ati ẹrọ.
Akiyesi: Apẹrẹ example ìkọlélórí yiyan pẹlu awọn ẹrọ lori afojusun ọkọ. O pato awọn afojusun ọkọ lati awọn akojọ ti oniru example awọn aṣayan ninu awọn Example Design taabu (Igbese 8). - Ninu Katalogi IP, wa ko si yan Low Latency E-Tile 40G Ethernet Intel FPGA IP. Ferese Iyipada IP Tuntun yoo han.
- Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita IP Intel Quartus Prime IP fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
- Tẹ O DARA. Olootu paramita IP yoo han.
- Lori IP taabu, pato awọn paramita fun iyatọ ipilẹ IP rẹ.
Akiyesi: The Low Lairi E-Tile 40G àjọlò Intel FPGA IP design example ko ṣe adaṣe ni deede ati pe ko ṣiṣẹ ni deede ti o ba pato eyikeyi ninu awọn aye atẹle wọnyi:- Jeki Preamble kọja-nipasẹ titan
- Ti ṣeto idaduro idaduro si iye ti 3
- Muu TX CRC ṣiṣẹ ni pipa
- Lori Example Design taabu, labẹ Eksample Apẹrẹ Files, mu aṣayan Simulation ṣiṣẹ lati ṣe ina testbench, ki o yan aṣayan Synthesis lati ṣe agbekalẹ akojọpọ-nikan ati apẹrẹ ohun elo examples.
Akiyesi: Lori Eksamptaabu Oniru, labẹ Ti ipilẹṣẹ HDL kika, nikan Verilog HDL wa. Kokoro IP yii ko ṣe atilẹyin VHDL. - Labẹ Apo Idagbasoke Àkọlé yan Stratix 10 TX E-Tile Transceiver Signal Integrity Development Apo tabi Agilex F-jara Transceiver-SoC Development Apo.
Akiyesi: Ohun elo idagbasoke ti o yan ṣe atunkọ yiyan ẹrọ ni Igbesẹ- Intel Stratix 10 E-tile afojusun ẹrọ ni 1SG280LU3F50E3VGS1.
- Ifojusi ẹrọ Intel Agilex E-tile jẹ AGFB014R24A2E2VR0.
- Tẹ Ina Example Design bọtini. Awọn Yan Example Design Directory window han.
- Ti o ba fẹ yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (alt_e40c3_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example orukọ liana (ample_dir>).
- Tẹ O DARA.
Alaye ti o jọmọ
- IP mojuto paramita
Pese alaye diẹ sii nipa isọdi ipilẹ IP rẹ. - Intel Stratix 10 E-Tile TX Signal Integrity Development Apo
- Intel Agilex F-Series FPGA Development Kit
Apẹrẹ Example Parameters
Awọn paramita ni Example Design Tab
| Paramita | Apejuwe |
| Yan Oniru | Wa example awọn aṣa fun IP paramita eto. Nigbati o ba yan apẹrẹ kan lati ile-ikawe tito tẹlẹ, aaye yii fihan apẹrẹ ti o yan. |
| Example Apẹrẹ Files | Awọn files lati se ina fun awọn ti o yatọ idagbasoke alakoso.
• Afọwọṣe- ipilẹṣẹ ti o nilo files fun kikopa Mofiample apẹrẹ. • Akopọ- n ṣe iṣelọpọ files. Lo awọn wọnyi files lati ṣajọ apẹrẹ ni sọfitiwia Intel Quartus Prime Pro Edition fun idanwo ohun elo ati ṣe itupalẹ akoko aimi. |
| Ṣẹda File Ọna kika | Ọna kika RTL files fun kikopa-Verilog tabi VHDL. |
| Yan Board | Ohun elo atilẹyin fun imuse apẹrẹ. Nigbati o ba yan ohun Intel idagbasoke ọkọ, awọn Àkọlé Device jẹ ọkan ti o baamu ẹrọ lori Apo Idagbasoke.
Ti akojọ aṣayan yii ko ba wa, ko si igbimọ atilẹyin fun awọn aṣayan ti o yan. Agilex F-jara Transceiver-SoC Development Kit: Yi aṣayan faye gba o lati se idanwo awọn oniru example lori ohun elo idagbasoke Intel FPGA IP ti a yan. Yi aṣayan laifọwọyi yan awọn Àkọlé Device ti AGFB014R24A2E2VR0. Ti o ba ti rẹ ọkọ àtúnyẹwò ni o ni kan ti o yatọ ẹrọ ite, o le yi awọn afojusun ẹrọ. |
| tesiwaju… | |
| Paramita | Apejuwe |
| Stratix 10 TX E-Tile Transceiver Signal Integrity Development Apo: Yi aṣayan faye gba o lati se idanwo awọn oniru example lori ohun elo idagbasoke Intel FPGA IP ti a yan. Yi aṣayan laifọwọyi yan awọn Àkọlé Device ti 1ST280EY2F55E2VG. Ti o ba ti rẹ ọkọ àtúnyẹwò ni o ni kan ti o yatọ ẹrọ ite, o le yi awọn afojusun ẹrọ.
Ko si: Aṣayan yii yọkuro awọn aaye ohun elo fun apẹrẹ apẹẹrẹample. |
Ilana Ilana
The Low Lairi E-Tile 40G àjọlò IP mojuto oniru example file awọn ilana ni awọn wọnyi ti ipilẹṣẹ files fun apẹrẹ example.
Ilana Ilana fun Apẹrẹ Ti ipilẹṣẹ Eksample
- Simulation naa files (testbench fun kikopa nikan) wa ninuample_dir>/ apẹẹrẹample_testbench.
- Awọn akopo-nikan example oniru wa ni be niample_dir>/ compilation_test_design.
- Awọn hardware iṣeto ni ati igbeyewo files (apẹrẹ hardware example) wa ninuample_dir>/hardware_test_design
Liana ati File Awọn apejuwe
| File Awọn orukọ | Apejuwe |
| eth_ex_40g.qpf | Intel Quartus NOMBA ise agbese file. |
| eth_ex_40g.qsf | Intel Quartus NOMBA eto ise agbese file. |
| tesiwaju… | |
| File Awọn orukọ | Apejuwe |
| eth_ex_40g.sdc | Synopsys * Design inira file. O le daakọ ati tunṣe eyi file fun ara rẹ Low Lairi E-Tile 40G àjọlò Intel FPGA IP design. |
| eth_ex_40g.srf | Intel Quartus Prime ise agbese ifiranṣẹ bomole ofin file. |
| eth_ex_40g.v | Oke-ipele Verilog HDL oniru example file. |
| eth_ex_40g_clock.sdc | Synopsys Design inira file fun awọn aago. |
| wọpọ/ | Hardware oniru example ṣe atilẹyin files. |
| hwtest/main.tcl | Akọkọ file fun wiwọle System Console. |
Simulating awọn Oniru Example Testbench
O le ṣajọ ati ṣe afiwe apẹrẹ naa nipa ṣiṣe iwe afọwọkọ kikopa lati inu aṣẹ aṣẹ.
- Ni aṣẹ aṣẹ, yi itọsọna iṣẹ pada siample_dir>/ apẹẹrẹample_testbench.
- Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin iṣeṣiro ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo
Awọn ilana lati Simulate Testbench
| Simulator | Awọn ilana |
| AwoṣeSim* | Ninu laini aṣẹ, tẹ vsim -do run_vsim.do.
Ti o ba fẹ lati ṣe adaṣe lai mu ModelSim GUI soke, tẹ vsim -c -do run_vsim.do. Akiyesi: Awọn simulators ModelSim-AE ati ModelSim-ASE ko le ṣedasilẹ ipilẹ IP yii. O gbọdọ lo afọwọṣe ModelSim atilẹyin miiran gẹgẹbi ModelSim SE. |
| VCS* | Ninu laini aṣẹ, tẹ sh run_vcs.sh |
| VCS MX | Ninu laini aṣẹ, tẹ sh run_vcsmx.sh.
Lo iwe afọwọkọ yii nigbati apẹrẹ ni Verilog HDL ati System Verilog pẹlu VHDL. |
| NCSim | Ninu laini aṣẹ, tẹ sh run_ncsim.sh |
| Xcelium* | Ninu laini aṣẹ, tẹ sh run_xcelium.sh |
Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle: Simulation Ti kọja. tabi Testbench pari. Lẹhin ipari aṣeyọri, o le ṣe itupalẹ awọn abajade.
Iṣakojọpọ ati Ṣiṣeto Oniru Example ni Hardware
Olootu paramita ipilẹ Intel FPGA IP gba ọ laaye lati ṣajọ ati tunto apẹrẹ apẹẹrẹample lori ohun elo idagbasoke ibi-afẹde
Lati ṣajọ ati tunto apẹrẹ exampLe lori hardware, tẹle awọn igbesẹ wọnyi:
- Lọlẹ Intel Quartus Prime Pro Edition sọfitiwia ki o yan Ṣiṣẹpọ ➤ Bẹrẹ Iṣakojọpọ lati ṣajọ apẹrẹ naa.
- Lẹhin ti o ṣe ina ohun SRAM file .sof, tẹle awọn igbesẹ wọnyi lati ṣe eto apẹrẹ hardware example lori ẹrọ Intel:
- Yan Awọn Irinṣẹ ➤ Oluṣeto.
- Ni awọn Programmer, tẹ Hardware Setup.
- Yan ẹrọ siseto.
- Yan ki o ṣafikun igbimọ Intel TX si igba Intel Quartus Prime Pro Edition rẹ.
- Rii daju pe Ipo ti ṣeto si JTAG.
- Yan ẹrọ Intel ki o tẹ Fi ẹrọ kun. Awọn pirogirama ṣe afihan aworan atọka Àkọsílẹ ti awọn asopọ laarin awọn ẹrọ lori igbimọ rẹ.
- Ni ila pẹlu .sof rẹ, ṣayẹwo apoti fun .sof.
- Tan Eto/Aṣayan atunto fun .sof.
- Tẹ Bẹrẹ.
Alaye ti o jọmọ
- Akopọ Ipilẹṣẹ fun Iṣagbekalẹ ati Apẹrẹ Ipilẹ Ẹgbẹ
- Siseto Intel FPGA Devices
Ayipada Àkọlé Device ni Hardware Design Example
Ti o ba ti yan Stratix 10 TX E-Tile Transceiver Signal Integrity Development Apo bi ẹrọ ibi-afẹde rẹ, Low Latency E-Tile 40G Ethernet Intel FPGA IP mojuto ṣe ipilẹṣẹ ohun elo kan tẹlẹ.ample oniru fun afojusun ẹrọ 1ST280EY2F55E2VG. Ti o ba ti yan Agilex F-jara Transceiver-SoC Development Apo bi ẹrọ ibi-afẹde rẹ, Low Latency E-Tile 40G Ethernet Intel FPGA IP mojuto n ṣe ipilẹṣẹ ohun elo example oniru fun afojusun ẹrọ AGFB014R24A2E2VR0. Awọn pàtó afojusun ẹrọ le yato lati awọn ẹrọ lori rẹ idagbasoke kit. Lati yi awọn afojusun ẹrọ ninu rẹ hardware oniru example, tẹle awọn igbesẹ wọnyi:
- Lọlẹ Intel Quartus Prime Pro Edition sọfitiwia ati ṣii iṣẹ akanṣe idanwo ohun elo file /hardware_test_design/eth_ex_40g.qpf.
- Lori akojọ Awọn iṣẹ iyansilẹ, tẹ Ẹrọ. Apoti ibaraẹnisọrọ ẹrọ yoo han.
- Ninu apoti ibaraẹnisọrọ Ẹrọ, yan tabili ẹrọ ti o da lori E-tile ti o baamu nọmba apakan ẹrọ lori ohun elo idagbasoke rẹ. Tọkasi ọna asopọ ohun elo idagbasoke lori Intel webaaye fun alaye diẹ sii.
- Atọka yoo han nigbati o yan ẹrọ kan, bi o ṣe han ninu nọmba ni isalẹ. Yan Bẹẹkọ lati tọju awọn iṣẹ iyansilẹ pin ti ipilẹṣẹ ati awọn iṣẹ iyansilẹ I/O.
Intel Quartus Prime Tọ fun Aṣayan Ẹrọ
- Ṣe akojọpọ kikun ti apẹrẹ rẹ.
O le ṣe idanwo apẹrẹ lori ohun elo rẹ bayi.
Alaye ti o jọmọ
- Intel Stratix 10 E-Tile TX Signal Integrity Development Apo
- Intel Agilex F-Series FPGA Development Kit
Idanwo Low Lairi E-Tile 40G Ethernet Intel FPGA IP Design ni Hardware
Lẹhin ti o ṣe akopọ Low Latency E-Tile 40G Ethernet Intel FPGA IP core design exampati tunto rẹ lori ẹrọ Intel rẹ, o le lo Console System lati ṣe eto ipilẹ IP ati awọn iforukọsilẹ mojuto Native PHY IP ti o fi sii. Lati tan-an Console System ati idanwo apẹrẹ hardware example, tẹle awọn igbesẹ wọnyi:
- Ninu sọfitiwia Intel Quartus Prime Pro Edition, yan Awọn irinṣẹ ➤ Awọn irinṣẹ N ṣatunṣe aṣiṣe Eto ➤ Eto console lati ṣe ifilọlẹ console eto naa.
- Ninu PAN Tcl Console, tẹ cd hwtest lati yi itọsọna pada si /hardware_test_design/hwtest.
- Tẹ orisun main.tcl lati ṣii asopọ si JTAG oluwa.
Apẹrẹ afikun exampAwọn aṣẹ le wa lati ṣe eto ipilẹ IP:
- chkphy_ipo: Ṣe afihan awọn igbohunsafẹfẹ aago ati ipo titiipa PHY.
- chkmac_stats: Ṣe afihan awọn iye ninu awọn iṣiro iṣiro MAC.
- clear_all_stats: Pa awọn iṣiro iṣiro ipilẹ IP kuro.
- bẹrẹ_pkt_gen: Bẹrẹ awọn soso monomono.
- stop_pkt_gen: Da packet monomono.
- sys_reset_digital_analog: Eto titunto.
- loop_lori: Tan ti abẹnu ni tẹlentẹle loopback
- loop_off: Pa ti abẹnu ni tẹlentẹle loopback.
- reg_read : Pada iye iforukọsilẹ mojuto IP pada ni .
- reg_write : Kọ si iforukọsilẹ mojuto IP ni adirẹsi .
Tẹle ilana idanwo ni apakan Idanwo Hardware ti apẹrẹ example ṣe akiyesi awọn abajade idanwo ni Console System.
Alaye ti o jọmọ
Ṣiṣayẹwo ati Awọn apẹrẹ N ṣatunṣe aṣiṣe pẹlu Eto Console
Apẹrẹ Example Apejuwe
The E-tile orisun 40G àjọlò oniru example ṣe afihan awọn iṣẹ ti Low Latency E-Tile 40G Ethernet Intel FPGA IP mojuto, pẹlu E-tile orisun transceiver ni wiwo ibamu pẹlu IEEE 802.3ba boṣewa CAUI-4 sipesifikesonu. O le ṣe ina apẹrẹ lati Example Design taabu ni Low Lairi E-Tile 40G àjọlò Intel FPGA IP paramita olootu.
Lati ṣe ina apẹrẹ exampNitorina, o gbọdọ kọkọ ṣeto awọn iye paramita fun iyatọ ipilẹ IP ti o pinnu lati ṣe ina ni ọja ipari rẹ. Ti o npese awọn oniru example ṣẹda ẹda ti ipilẹ IP; testbench ati hardware design example lo iyatọ yii bi DUT. Ti o ko ba ṣeto awọn iye paramita fun DUT lati baamu awọn iye paramita ninu ọja ipari rẹ, apẹrẹ apẹẹrẹample o se ina ko idaraya IP mojuto iyatọ ti o pinnu.
Akiyesi:
Testbench ṣe afihan idanwo ipilẹ ti ipilẹ IP. Ko ṣe ipinnu lati jẹ aropo fun agbegbe ijẹrisi ni kikun. O gbọdọ ṣe ijerisi lọpọlọpọ diẹ sii ti Irẹwẹsi Kekere E-Tile 40G Ethernet Intel FPGA IP apẹrẹ ni kikopa ati ni ohun elo.
Awọn ẹya ara ẹrọ
- Ṣe atilẹyin 40G Ethernet MAC / PCS IP mojuto fun transceiver E-tile nipa lilo Intel Stratix 10 tabi ẹrọ Agilex Intel.
- Atilẹyin Preamble kọja-nipasẹ ati ikẹkọ ọna asopọ.
- Ṣe ipilẹṣẹ apẹrẹ example pẹlu Mac awọn iṣiro awọn iṣiro ẹya-ara.
- Pese testbench ati kikopa akosile.
Hardware ati Software Awọn ibeere
Lati ṣe idanwo exampFun apẹrẹ, lo hardware ati sọfitiwia atẹle:
- Intel Quartus NOMBA Pro Edition software
- Console System
- ModelSim, VCS, VCS MX, NCSim, tabi Xcelium Simulator
- Intel Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit tabi Intel Agilex F-jara Transceiver-SoC Development Kit
Apejuwe iṣẹ-ṣiṣe
Yi apakan apejuwe 40G àjọlò MAC/PCS IP mojuto lilo awọn Intel ẹrọ ni E-tile orisun transceiver. Ni itọsọna gbigbe, MAC gba awọn fireemu alabara ati fi sii aafo inter-packet (IPG), Preamble, ibẹrẹ ti apinpin fireemu (SFD), padding, ati awọn die-die CRC ṣaaju gbigbe wọn lọ si PHY. PHY ṣe koodu fireemu Mac bi o ṣe nilo fun gbigbe igbẹkẹle lori media si opin jijin. Ni itọsọna gbigba, PHY kọja awọn fireemu si MAC. MAC n gba awọn fireemu lati PHY, ṣe awọn sọwedowo, yọ kuro ni CRC, Preamble, ati SFD, o si fi iyoku fireemu ranṣẹ si alabara.
Afọwọṣe
Testbench firanṣẹ ijabọ nipasẹ mojuto IP, ṣiṣe adaṣe ẹgbẹ atagba ati gba ẹgbẹ ti mojuto IP.
Low Lairi E-Tile 40G àjọlò Design Eksample Àkọsílẹ aworan atọka
Apẹrẹ kikopa example oke-ipele igbeyewo file jẹ basic_avl_tb_top.sv. Eyi file n pese itọkasi aago clk_ref ti 156.25 Mhz si PHY. O pẹlu iṣẹ-ṣiṣe kan lati firanṣẹ ati gba awọn apo-iwe 10.
Low Lairi E-Tile 40G àjọlò mojuto Testbench File Awọn apejuwe
| File Awọn orukọ | Apejuwe |
| Testbench ati Simulation Files | |
| ipilẹ_avl_tb_top.sv | Igbeyewo ipele oke file. Testbench naa ṣe imudara DUT ati ṣiṣe awọn iṣẹ ṣiṣe Verilog HDL lati ṣe ina ati gba awọn apo-iwe. |
| ipilẹ_avl_tb_top_nc.sv | Igbeyewo ipele oke file ni ibamu pẹlu NCsim labeabo. |
| ipilẹ_avl_tb_top_msim.sv | Igbeyewo ipele oke file ni ibamu pẹlu simulator ModelSim. |
| Awọn iwe afọwọkọ Testbench | |
| run_vsim.do | Awọn Graphics Mentor * Iwe afọwọkọ ModelSim lati ṣiṣẹ ijoko idanwo naa. |
| run_vcs.sh | Awọn Synopsys VCS iwe afọwọkọ lati ṣiṣe awọn testbench. |
| tesiwaju… | |
| File Awọn orukọ | Apejuwe |
| run_vcsmx.sh | Awọn Synopsys VCS MX iwe afọwọkọ (ni idapo Verilog HDL ati System Verilog pẹlu VHDL) lati ṣiṣe awọn testbench. |
| run_ncsim.sh | Iwe afọwọkọ Cadence NCSim lati ṣiṣẹ testbench. |
| run_xcelium.sh | Iwe afọwọkọ Cadence Xcelium lati ṣiṣe testbench naa. |
Ṣiṣe idanwo aṣeyọri ṣe afihan iṣelọpọ ti o jẹrisi ihuwasi atẹle:
- Nduro fun aago RX lati yanju
- Titẹ sita ipo PHY
- Fifiranṣẹ awọn apo-iwe 10
- Gbigba awọn apo-iwe 10
- Ṣe afihan “Testbench ti pari.”
Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri kan:
- # Nduro fun titete RX
- #RX deskew titii pa
- # RX titete ọna titii pa
- #TX ṣiṣẹ
- #* Fifiranṣẹ Packet 1…
- #* Fifiranṣẹ Packet 2…
- #* Fifiranṣẹ Packet 3…
- #* Fifiranṣẹ Packet 4…
- #* Fifiranṣẹ Packet 5…
- #* Fifiranṣẹ Packet 6…
- #* Fifiranṣẹ Packet 7…
- #**Packet 1 ti o gba…
- #* Fifiranṣẹ Packet 8…
- #**Packet 2 ti o gba…
- #* Fifiranṣẹ Packet 9…
- #**Packet 3 ti o gba…
- #* Fifiranṣẹ Packet 10…
- #**Packet 4 ti o gba…
- #**Packet 5 ti o gba…
- #**Packet 6 ti o gba…
- #**Packet 7 ti o gba…
- #**Packet 8 ti o gba…
- #**Packet 9 ti o gba…
- #**Packet 10 ti o gba…
Alaye ti o jọmọ
Simulating awọn Oniru Example Testbench loju iwe 7
Hardware Igbeyewo
Ni hardware oniru exampLe, o le eto awọn IP mojuto ni ti abẹnu ni tẹlentẹle loopback mode ati ina ijabọ lori awọn atagba ẹgbẹ ti o losiwajulosehin pada nipasẹ awọn gba ẹgbẹ.
Low Lairi E-Tile 40G àjọlò IP Hardware Design Example High Ipele Block aworan atọka
The Low Lairi E-Tile 40G Ethernet hardware oniru example pẹlu awọn eroja wọnyi:
- Low Lairi E-Tile 40G àjọlò Intel FPGA IP mojuto.
- Onibara kannaa ti o ipoidojuko siseto ti IP mojuto, ati soso iran ati yiyewo.
- IOPLL lati ṣe agbejade aago 100 MHz lati aago titẹ sii 50 MHz si apẹrẹ ohun elo example.
- JTAG oludari ti o ibasọrọ pẹlu awọn Intel System Console. O ṣe ibasọrọ pẹlu ọgbọn alabara nipasẹ ẹrọ Console System.
Tẹle ilana naa ni ọna asopọ alaye ti o ni ibatan ti a pese lati ṣe idanwo apẹrẹ example ninu awọn ti o yan hardware.
Alaye ti o jọmọ
- Idanwo Low Latency E-Tile 40G Ethernet Intel FPGA IP Design ni Hardware loju iwe 9
- Ṣiṣayẹwo ati Awọn apẹrẹ N ṣatunṣe aṣiṣe pẹlu Eto Console
Ti abẹnu Loopback Idanwo
Ṣiṣe awọn igbesẹ wọnyi lati ṣe idanwo loopback inu:
- Tun eto.
sys_reset_digital_analog - Ṣe afihan igbohunsafẹfẹ aago ati ipo PHY.
chkphy_ipo - Tan idanwo loopback inu.
loop_lori - Ṣe afihan igbohunsafẹfẹ aago ati ipo PHY. Awọn rx_clk ti ṣeto si 312.5 MHz ati
rx_pcs_ready ti ṣeto si 1.
chkphy_ipo - Bẹrẹ awọn soso monomono.
bẹrẹ_pkt_gen - Da awọn soso monomono.
Duro_pkt_gen - Review awọn nọmba ti zqwq ati ki o gba awọn apo-iwe.
chkmac_stats - Tun pa ti abẹnu loopback igbeyewo.
loop_off
Idanwo Loopback ita
Ṣiṣe awọn igbesẹ wọnyi lati ṣe idanwo loopback ita:
- Tun eto.
sys_reset_digital_analog - Ṣe afihan igbohunsafẹfẹ aago ati ipo PHY. Awọn rx_clk ti ṣeto si 312.5 MHz ati
rx_pcs_ready ti ṣeto si 1. chkphy_status - Bẹrẹ awọn soso monomono.
bẹrẹ_pkt_gen - Da awọn soso monomono.
Duro_pkt_gen - Review awọn nọmba ti zqwq ati ki o gba awọn apo-iwe.
chkmac_stats
Low Lairi E-Tile 40G àjọlò Design Eksample Awọn iforukọsilẹ
Low Lairi E-Tile 40G àjọlò Hardware Design Example Forukọsilẹ Map
Awọn atokọ ti awọn sakani iforukọsilẹ ti o ya aworan iranti fun apẹrẹ hardware example. O wọle si awọn iforukọsilẹ wọnyi pẹlu awọn iṣẹ reg_read ati reg_write ninu Eto Console.
| Aiṣedeede Ọrọ | Forukọsilẹ Iru |
| 0x300-0x3FF | Awọn iforukọsilẹ PHY |
| 0x400-0x4FF | TX MAC forukọsilẹ |
| 0x500-0x5FF | RX MAC forukọsilẹ |
| 0x800-0x8FF | Awọn iforukọsilẹ Counter Statistics - itọsọna TX |
| 0x900-0x9FF | Statistics Counter forukọsilẹ - RX itọsọna |
| 0x1000-1016 | Packet Client forukọsilẹ |
Packet Client registers
O le ṣe adani Low Lairi E-Tile 40G Ethernet oniru hardware design example nipa siseto onibara forukọsilẹ.
| Addr | Oruko | Bit | Apejuwe | HW Tun iye | Wiwọle |
| 0x1008 | Iṣeto Iwọn Packet | [29:0] | Pato iwọn soso gbigbe ni awọn baiti. Awọn die-die wọnyi ni awọn igbẹkẹle si iforukọsilẹ PKT_GEN_TX_CTRL.
• Bit [29:16]: Pato opin oke ti iwọn apo ni awọn baiti. Eyi wulo nikan si ipo afikun. • Bit [13:0]: - Fun ipo ti o wa titi, awọn die-die wọnyi pato iwọn soso gbigbe ni awọn baiti. - Fun ipo afikun, awọn die-die wọnyi pato awọn baiti afikun fun soso kan. |
0x25800040 | RW |
| 0x1009 | Packet Number Iṣakoso | [31:0] | Pato awọn nọmba ti awọn apo-iwe lati atagba lati awọn soso monomono. | 0xA | RW |
| 0x1010 | PKT_GEN_TX_C TRL | [7:0] | • Bit [0]: Ni ipamọ.
• Bit [1]: Packet monomono mu bit. Ṣeto bit yii si iye ti 1 lati pa monomono apo, ki o tunto si iye ti 0 lati tan-an olupilẹṣẹ apo. • Bit [2]: Ni ipamọ. • Bit [3]: Ni iye ti 1 ti IP mojuto ba wa ni ipo loopback MAC; ni iye ti 0 ti alabara soso ba lo olupilẹṣẹ apo. |
0x6 | RW |
| tesiwaju… | |||||
| Addr | Oruko | Bit | Apejuwe | HW Tun iye | Wiwọle |
| • Bit [5:4]:
- 00: Ipo ID - 01: Ipo ti o wa titi - 10: Ipo afikun • Bit [6]: Ṣeto bit yii si 1 lati lo iforukọsilẹ 0x1009 lati pa monomono soso ti o da lori nọmba ti o wa titi ti awọn apo-iwe lati tan kaakiri. Bibẹẹkọ, bit [1] ti iforukọsilẹ PKT_GEN_TX_CTRL ni a lo lati paa monomono apo. • Bit [7]: - 1: Fun gbigbe laisi aafo laarin awọn apo-iwe. - 0: Fun gbigbe pẹlu aafo laileto laarin awọn apo-iwe. |
|||||
| 0x1011 | Adirẹsi opin si isalẹ 32 die-die | [31:0] | Àdírẹ́ẹ̀sì ọ̀nà (ìsàlẹ̀ 32 bits) | 0x56780ADD | RW |
| 0x1012 | Adirẹsi opin si oke 16 die-die | [15:0] | Adirẹsi opin si (oke 16 die-die) | 0x1234 | RW |
| 0x1013 | Adirẹsi orisun isalẹ 32 die-die | [31:0] | Adirẹsi orisun (awọn bit 32 isalẹ) | 0x43210ADD | RW |
| 0x1014 | Adirẹsi orisun oke 16 die-die | [15:0] | Adirẹsi orisun (awọn iwọn 16 oke) | 0x8765 | RW |
| 0x1016 | PKT_CL_LOOPB ACK_RESET | [0] | Mac loopback si ipilẹ. Ṣeto si iye ti 1 lati tun awọn oniru example MAC loopback. | 1'b0 | RW |
Alaye ti o jọmọ
Irẹwẹsi kekere E-Tile 40G Iṣakoso Ethernet ati Awọn apejuwe Iforukọsilẹ Ipo Ṣapejuwe awọn iforukọsilẹ Ipilẹ Ipilẹ Ipilẹ Irẹlẹ E-Tile 40G.
Apẹrẹ Example Interface Awọn ifihan agbara
Low Latency E-Tile 40G Ethernet testbench jẹ ti ara ẹni ati pe ko nilo ki o wakọ eyikeyi awọn ifihan agbara titẹ sii.
Low Lairi E-Tile 40G àjọlò Hardware Design Example Interface Awọn ifihan agbara
| Ifihan agbara | Itọsọna | Comments |
|
clk50 |
Iṣawọle |
Yi aago ti wa ni ìṣó nipasẹ awọn ọkọ oscillator.
• Wakọ ni 50 MHz on Intel Stratix 10 ọkọ. • Wakọ ni 100 MHz lori Intel Agilex ọkọ. Apẹrẹ hardware example ṣe ọna aago yii si titẹ sii ti IOPLL kan lori ẹrọ naa ati tunto IOPLL lati wakọ aago 100 MHz ni inu. |
| clk_ref | Iṣawọle | Wakọ ni 156.25 MHz. |
| tesiwaju… | ||
| Ifihan agbara | Itọsọna | Comments |
|
cpu_resetn |
Iṣawọle |
Tun IP mojuto. Ti nṣiṣe lọwọ kekere. Ṣe awakọ atunto lile agbaye csr_reset_n si ipilẹ IP. |
| tx_serial[3:0] | Abajade | Transceiver PHY o wu data ni tẹlentẹle. |
| rx_serial [3:0] | Iṣawọle | Transceiver PHY igbewọle data ni tẹlentẹle. |
|
olumulo_led[7:0] |
Abajade |
Awọn ifihan agbara ipo. Apẹrẹ hardware example so awọn die-die wọnyi pọ lati wakọ awọn LED lori igbimọ ibi-afẹde. Awọn die-die kọọkan ṣe afihan awọn iye ifihan agbara atẹle ati ihuwasi aago:
• [0]: Ifihan agbara atunto akọkọ si IP mojuto • [1]: Pipin version of clk_ref • [2]: Pipin version of clk50 • [3]: Pipin version of 100 MHz ipo aago • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready |
Alaye ti o jọmọ
Awọn atọkun ati Awọn Apejuwe ifihan agbara Pese awọn apejuwe alaye ti Low Latency E-Tile 40G Ethernet IP mojuto awọn ifihan agbara ati awọn atọkun si eyiti wọn jẹ.
Low Lairi E-Tile 40G àjọlò Intel FPGA IP Archives
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | IP Core Version | Itọsọna olumulo |
| 20.1 | 19.1.0 | Low Lairi E-Tile 40G àjọlò Design Eksample User Itọsọna |
Itan Atunyẹwo Iwe-ipamọ fun Irẹwẹsi E-tile 40G Ethernet Design Example User Itọsọna
| Ẹya Iwe aṣẹ | Intel Quartus NOMBA Version | Ẹya IP | Awọn iyipada |
| 2020.06.22 | 20.2 | 20.0.0 | Atilẹyin ẹrọ ti a ṣafikun fun awọn ẹrọ Intel Agilex. |
| 2020.04.13 | 20.1 | 19.1.0 | Itusilẹ akọkọ. |
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
Awọn iwe aṣẹ / Awọn orisun
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intel Low Lairi E-Tile 40G àjọlò Intel FPGA IP Design Eksample [pdf] Itọsọna olumulo Low Lairi E-Tile 40G àjọlò Intel FPGA IP Design Eksample, Low Lairi, E-Tile 40G àjọlò Intel FPGA IP Design Eksample, Intel FPGA IP Design Eksample, IP Design Example |
