Hardware Design with FPGA

1 Introduction

• 1.1 Circuit Design ...................................................................................................10
• 1.2 Structure of Field Programmable Gate Arrays........................................................11

2 Digital Systems

• 2.1 Flip-Flops and Registers ............................................................................................18
• 2.2 Memory Blocks.......................................................................................................22
• 2.3 Truth Tables...........................................................................................................23
• 2.4 Multiplexers.............................................................................................................25
• 2.5 Logic Blocks............................................................................................................26
• 2.6 Input/Output Blocks..............................................................................................27
• 2.7 Clock Generation and PLLs.......................................................................................29

3 Digital Circuit Technology

• 3.1 Combinational Circuits.............................................................................................31
• 3.2 Synchronous Circuits................................................................................................32
• 3.3 Asynchronous Circuits.............................................................................................33
• 3.4 Circuit Effects.........................................................................................................34
• 3.4.1 Metastabilities................................................................................................35
• 3.4.2 Signal Pulses and Delays...................................................................................36
• 3.4.3 Hold Time Violation.........................................................................................38
• 3.4.4 Switched Clock..................................................................................................40
• 3.4.5 Combinational Loops........................................................................................41
• 3.4.6 Race Condition in the Circuit............................................................................42
• 3.5 Simulation Effects....................................................................................................43
• 3.5.1 Race Condition in Simulation...........................................................................43
• 3.5.2 Signal Level......................................................................................................44
• 3.5.3 Clock Ratios.....................................................................................................44
• 3.5.4 Analog Circuit Components.............................................................................44
• 3.5.5 Memory Components.......................................................................................45
• 3.6 FPGA Circuit Design..................................................................................................45
• 3.6.1 Clock Domains and Transitions..........................................................................46
• 3.6.2 Handshake Signals............................................................................................50
• 3.6.3 Synchronization Stages.....................................................................................51
• 3.6.4 Data Exchange..................................................................................................53
• 3.6.5 Maximum Clock Frequency...............................................................................54
• 3.6.6 Circuit Reset.....................................................................................................56
• 3.6.7 Use of Latches..................................................................................................58
• 3.6.8 Internal Signal Buses........................................................................................59

4 Circuit Development

• 4.1 Development Steps..................................................................................................65
• 4.2 Specification and Circuit Documentation..................................................................68
• 4.3 HDL Description.....................................................................................................70
• 4.3.1 Behavioral Description...................................................................................71
• 4.3.2 Synthesis Description....................................................................................73
• 4.3.3 Differences from Software Programming.........................................................75
• 4.3.4 HDL Description Languages............................................................................76
• 4.3.4.1 VHDL Description..................................................................................77
• 4.3.4.1.1 VHDL Algorithms for Logic Elements...............................................81
• 4.3.4.1.2 VHDL Algorithms for Other Elements...............................................88
• 4.3.4.1.3 VHDL Coding Errors......................................................................96
• 4.3.4.2 Verilog Description.................................................................................97
• 4.3.4.2.1 Verilog Algorithms for Logic Elements............................................101
• 4.3.4.2.2 Verilog Algorithms for Other Elements............................................106
• 4.3.4.2.3 Verilog Coding Errors...................................................................111
• 4.3.4.3 SystemC and Other Description Languages..........................................113
• 4.3.5 Software Tools..............................................................................................115
• 4.4 Simulation and Verification.................................................................................118
• 4.4.1 Verification Plan............................................................................................121
• 4.4.2 Functional Verification................................................................................122
• 4.4.3 Regression Test...............................................................................................125
• 4.4.4 Test Environment................................................................................................125
• 4.4.5 Assertions................................................................................................................132
• 4.4.6 Transactions.................................................................................................141
• 4.4.7 Test Cases and Test Coverage..........................................................................141
• 4.4.8 Software Tools.........................................................................................................143
• 4.5 Synthesis and Implementation............................................................................146
• 4.5.1 Circuit Hierarchies.....................................................................................152
• 4.5.2 Clock Frequencies and Ranges........................................................................155
• 4.5.3 Pin Assignment..................................................................................................157
• 4.5.4 Timing Verification.......................................................................................158
• 4.5.5 Software Tools..................................................................................................159
• 4.6 Further Topics.......................................................................................................160

5 FPGA Building Blocks

• 5.1 Actel FPGAs........................................................................................................165
• 5.1.1 Libero IDE.....................................................................................................168
• 5.1.2 IGLOO-nano Evaluation Kit........................................................................170
• 5.2 Altera FPGAs.......................................................................................................172
• 5.2.1 Quartus-II Development Environment................................................................176
• 5.2.2 Cyclone-II Evaluation Kit............................................................................178
• 5.3 Xilinx FPGAs.......................................................................................................180
• 5.3.1 ISE Development Environment..........................................................................185
• 5.3.2 Spartan-3 Evaluation Kit..............................................................................188
• 5.4 Other FPGA Manufacturers.....................................................................................191
• 5.5 Differentiation from ASIC, ASSP, and Structured ASIC..............................................193

6 IP Core Components

• 6.1 FPGA Manufacturers...................................................................................................199
• 6.2 Third-Party Providers................................................................................................203
• 6.3 OpenCores............................................................................................................204
• 6.4 Processors..........................................................................................................205

7 Design Example: DDS Frequency Generator

• 7.1 MATLAB/Simulink Simulation...........................................................................212
• 7.2 Software Program for Processors....................................................................223
• 7.3 Circuit Design for FPGA...............................................................................230
• 7.4 Simulation and Test Environment.............................................................................237
• 7.5 Synthesis...............................................................................................................246
• 7.6 Implementation..................................................................................................247
• 7.7 Realization with Actel FPGA...............................................................................249
• 7.8 Summary................................................................................................................250

8 References and Links

9 Further Links

10 Glossary