Mastering FPGA Chip Design

For Speed, Area, Power, and Reliability

Academy Pro Title by Kevin Hubbard

Digital Logic Design
History of the Computer Chip
EDA Tool Flow
Structural Verilog (+VHDL)
RTL Verilog (+VHDL)
FPGA Look Up Tables
Verilog (+VHDL) Design Hierarchy
Finite State Machines
IO Banks
RAMs and ROMs
FIFOs
Clocking
Timing Closure
Placement and Floorplanning
Digital Logic Simulation
Test Benches
Python Software
Digital Arithmetic
Example Design - Blinky
Design for Speed
Example Design - UART Interfacing
Design for Area
Design for Power
Example Design - SUMP3 Logic Analyzer
Design for Reliability
Example Design - Video Graphics Controller
Design for Style

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All rights reserved. No part of this book may be reproduced in any material form, including photocopying, or storing in any medium by electronic means and whether or not transiently or incidentally to some other use of this publication, without the written permission of the copyright holder except in accordance with the provisions of the Copyright Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licencing Agency Ltd., 90 Tottenham Court Road, London, England W1P 9HE. Applications for the copyright holder's permission to reproduce any part of the publication should be addressed to the publishers.

The authors and publisher have used their best efforts in ensuring the correctness of the information contained in this book. They do not assume, and hereby disclaim, any liability to any party for any loss or damage caused by errors or omissions in this book, whether such errors or omissions result from negligence, accident or any other cause.

ISBN 978-3-89576-687-9 (Print)

ISBN 978-3-89576-686-2 (eBook)

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