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F-Tile Interlaken Intel FPGA IP User Guide This user guide provides comprehensive information on the F-Tile Interlaken Intel FPGA IP core, detailing its features, installation, parameterization, simulation, and compilation processes. It covers functional descriptions, interface signals, IP registers, and performance metrics for various configurations, including Interleaved Mode, Packet Mode, and Interlaken Look-aside Mode. The guide is updated for Intel Quartus Prime Design Suite 22.1 and IP Version 4.0.0. |
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Intel F-Tile JESD204C FPGA IP User Guide: Features, Design, and Implementation This comprehensive user guide from Intel details the F-Tile JESD204C FPGA IP, a high-speed serial interface for DAC and ADC integration with Intel Agilex 7 FPGAs. It covers essential information for designers, including features, architecture, design steps, parameterization, performance metrics, and resource utilization, supporting the JESD204C standard. |
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F-Tile CPRI PHY Intel FPGA IP Design Example User Guide User guide detailing the F-Tile CPRI PHY Intel FPGA IP design example, covering generation, simulation, compilation, and hardware testing for Intel Agilex devices. Includes hardware and software requirements, directory structure, simulation procedures, and register details. |
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Scalable Switch Intel FPGA IP for PCI Express User Guide | Intel User guide for Intel's Scalable Switch FPGA IP for PCI Express. Features include a configurable switch architecture, upstream and downstream port connectivity, Hot Plug support, and integration with Intel P-Tile Avalon Streaming IP for PCIe Gen3 x16. Compatible with Intel Stratix 10 DX and Agilex FPGAs. |
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5G Polar Intel FPGA IP User Guide | Intel FPGA Technology This user guide provides comprehensive technical details for the 5G Polar Intel® FPGA IP. It covers features, 3GPP 5G NR compliance, installation, design, simulation, and functional descriptions for wireless applications. |
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Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide User guide detailing the Network-on-Chip (NoC) subsystem for Intel Agilex 7 M-Series FPGAs, covering architecture, design flow, memory interfaces (HBM2e, DDR5), AXI4 protocol, simulation, and power estimation for high-bandwidth applications. |
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Multi Channel DMA Intel® FPGA IP for PCI Express User Guide This user guide provides comprehensive details on the Multi Channel DMA Intel® FPGA IP for PCI Express. It explains how to efficiently transfer data between host systems and FPGA devices using multiple DMA channels over the PCIe link. The document covers IP features, functional descriptions, interface specifications, parameters, and design examples for Intel Stratix 10 and Agilex 7 FPGA families. |
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F-Tile JESD204B Intel FPGA IP User Guide User guide for the F-Tile JESD204B Intel FPGA IP, detailing its features, configuration, and implementation for high-speed serial communication in FPGA designs. Covers JESD204B standards, datapath modes, performance, and debugging. |