ADRV9008-1/ADRV9008-2/ADRV9009 Profile Configuration Tool User Guide
Brand: Analog Devices
Product Type: Transceiver Configuration Software
Company Address: One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Contact: Tel: 781.329.4700, Fax: 781.461.3113, www.analog.com
Introduction
This user guide describes the installation and use of the Profile Configuration Tool used with the ADRV9008-1 receiver (Rx), ADRV9008-2 transmitter (Tx) and observation receiver (ORx), and the ADRV9009 transceiver. This tool has been referred to as Filter Wizard for previous products, as one of its primary functions is the creation of custom finite impulse response (FIR) filter coefficient files.
The ADRV9008-1, ADRV9008-2, and ADRV9009 Profile Configuration Tool (referred to as the "profile tool" or "tool") is used to design the receiver, transmitter, and observation receiver FIR filters for the ADRV9008-x and ADRV9009 wideband integrated transceivers. This tool creates filters that equalize the desired passband while compensating for the signal transfer functions through the entire analog and digital signal paths in the transceiver. The tool also generates ADC profiles and clock rates usable with the Transceiver Evaluation Software for system performance evaluation. Any custom configuration of sampling rates and bandwidths must use this tool to create a profile for use in a customer system or with the evaluation kit. The profile tool is available as MATLAB source code, a MATLAB app, and as a stand-alone executable. The tool can be used without hardware connected until the new profile is transferred to the TES GUI and loaded into the evaluation system or customer code and system.
With this tool, users can perform the following tasks:
- Design new profiles combining sampling rates and bandwidths that adhere to transceiver operating limits and the on-chip ARM algorithm processor requirements.
- Design programmable FIR filters for custom profiles, save filter coefficients to a file, and load them into a customer system or the Transceiver Evaluation System (TES) GUI.
- Use or bypass the AD9528 JESD204B Clock Generator included on the ADRV9008-x and ADRV9009 evaluation boards.
- Examine filter responses in each signal path (composite analog, composite digital, and aggregate).
- Perform "what if" experiments by adjusting filter weighting parameters to trade off passband ripple with stopband rejection.
Revision List, Change Log, and Known Limitations
The release notes document contains the historical list of changes and limitations of the tool. It is available at: Analog Devices Transceiver Evaluation Software.
Revision History: 1/2019 - Revision A: Preliminary Version
Profile Configuration Tool Options and Downloads
The tool is available in three forms for maximum flexibility: MATLAB source code, a MATLAB App, and a stand-alone executable.
Executable
The executable (.exe) allows the tool to run as a separate application without requiring MATLAB. It provides a GUI for defining input parameters, generating filters, viewing results, and saving output parameters for use in customer systems or the ADI EVB GUI software. The executable name is Talise_Configuration_wizard.exe.
The executable is available here: Analog Devices Transceiver Evaluation Software.
To run the executable as a standalone application, the MATLAB runtime engine must be installed. It is typically installed automatically with the executable. The runtime engine can also be downloaded separately from: MathWorks Compiler Runtime. The engine may take over a minute to start up on its first run. Version R2015B or later is required.
MATLAB App
The MATLAB App runs within MATLAB and requires a valid license for MATLAB and the Control System Toolbox. The GUI and flexibility are identical to the executable, but running as an app allows users to write additional code for post-processing data files.
More information on installing and running MATLAB apps is available at: MathWorks App Installation Guide.
The MATLAB App is available here: Analog Devices Transceiver Evaluation Software.
MATLAB Source Code
These are MATLAB functions that can be launched from the MATLAB command window by defining input parameters. This method offers users more control over the internal design process.
The MATLAB source code is available here: Analog Devices Transceiver Evaluation Software.
Using the MATLAB App and Executable
This section elaborates on the executable and the App, noting that their input and output functionality is identical.
A Quick Start Example
The following steps outline the process of creating, saving, and loading a simple profile into the TES GUI:
- Open the Profile Generation Tool and select the correct transceiver part number.
- Enter sample rate and bandwidth parameters for all enabled signal paths.
- Enable ORx stitching if the ORx bandwidth exceeds 200 MHz.
- Adjust AD9528 VCXO and refclk settings to generate a usable device clock for the entered sampling rates.
- Generate and save the profiles.
- Open the TES GUI and connect it to the hardware evaluation system using the desired refclk frequency.
- In the TES GUI, navigate to "File" > "Load Custom Profile" and select the saved configuration file.
- In the TES GUI, adjust JESD settings and other parameters as needed, program the evaluation system, and enable the desired signal paths for performance evaluation.
Using the Tool GUI to Create a New Profile
The initial screen displayed after starting the Tool features an instruction screen in the center with input parameters on the left. The tool's GUI includes tabs for different summaries (Tx, ORx, Rx, Loopback) and displays filter responses after profile generation.
While the transceiver has separate transmitter, receiver, and observation receiver signal paths, all digital filters and data converters share a common clocking system. User-configurable sampling rates for each section are subject to specific rules to ensure a valid transceiver configuration. Some limitations are obvious (e.g., maximum sampling rate), while others depend on additional parameters and are less intuitive. The Profile Generation Rules section details these constraints.
Key rules include:
- Tx Input Sample Rate must equal ORx Output Sample Rate for calibration purposes.
- ORx Output Sample Rate must be a power-of-two multiple of the Rx Output Rate to satisfy JESD204B requirements.
- Tx Total RF BW must be less than 92% or 81% of the Tx sample rate, depending on signal path configuration.
- ORx RF BW must be less than 92% or 82% of the ORx sample rate, depending on signal path configuration.
- Rx RF BW must be greater than 40% and less than 82% of the Rx sample rate.
Product Selection
Three ADRV900x family products are available, each with a main RF PLL and an auxiliary PLL for calibration.
- ADRV9008-1: A two-receiver-only device, suitable for receive-only use cases or FDD applications where Rx and Tx signal paths operate on different RF frequencies.
- ADRV9008-2: A two-transmitter plus observation receiver (ORx) device, intended for transmitter-only use cases or when monitoring power amplifier output (e.g., DPD applications). It can be paired with the ADRV9008-1 for FDD applications.
- ADRV9009: Combines the functionality of the ADRV9008-1 and ADRV9008-2, supporting two receivers, two transmitters, and an observation receiver. It is designed for Time Division Duplex (TDD) use cases where Rx and Tx operate at the same RF frequency. The Tx path can be ignored via a checkbox.
The tool creates profiles specific to the selected device. For the ADRV9008-1, only receive signal path parameters are generated, optimizing tool usage.
The first step in using the tool is selecting the proper device from the drop-down menu.
Entering the Transmit Signal Path Parameters
For ADRV9008-2 or ADRV9009, Tx parameters must be entered unless the "Disable Tx" checkbox is selected. This checkbox is useful when the ADRV9009 is the target product but the transmit signal path is not needed.
Tx Input Sample Rate (MHz): The data rate of "I" and "Q" samples from the baseband processor. This rate must be between 30.625 MSPS and 500 MSPS. The tool rounds rates to the nearest kHz.
Tx Primary Signal BW (MHz): The bandwidth of the desired signal, representing the large signal bandwidth (up to approximately -1 dBFS peak). It must be between 5 MHz and 200 MHz. Adjusting this parameter affects analog and digital filters.
Tx Total RF BW (MHz): Supports wider bandwidths (2.5x to 5x primary BW) for applications like Digital Predistortion (DPD) to linearize power amplifiers. The maximum signal level must be managed to avoid clipping, requiring 6-7 dB headroom. The Total BW must be between 10 MHz and 450 MHz.
Pass Band Weight and Stop Band Weight: These parameters control the compromise between passband ripple and stopband rejection. A ratio of 1:1 gives equal weighting. Increasing the stopband weight improves rejection at the cost of ripple, and vice versa. Values are real numbers; a ratio of 1:10 is equivalent to 0.1:1.
Entering the ORx Signal Path Parameters
The ORx signal path is used in DPD applications to receive the total transmitted signal after the power amplifier. For ADRV9008-2 or ADRV9009 with the Tx path enabled, the "ORx Output Sample Rate (MHz)" must match the "Tx Input Sample Rate (MHz)". The "ORx RF BW (MHz)" is typically the same as "Tx Total RF BW (MHz)" for DPD applications. The ORx sample rate range is 30.625 to 500 MSPS, and the ORx BW range is 5 MHz to 450 MHz.
For non-DPD applications or when the Tx path is disabled, ORx sample rate and bandwidth values are more flexible but still bound by rules.
ORx Stitching: If the ORx RF bandwidth exceeds 200 MHz, the ADRV900x devices require "stitching" (tying together two signal paths) to handle higher sampling rates and wider bandwidths. This checkbox must be manually enabled. It is recommended to leave it unchecked during initial Rx/Tx profile optimization for faster iteration, then check it for ORx profile optimization.
Entering the Rx Signal Path Parameters
For ADRV9008-1 and ADRV9009 devices, the "Rx Output Sample Rate (MHz)" is the data rate from the transceiver to the baseband processor, ranging from 25 MSPS to 370 MSPS. The sample rate is rounded to the nearest 1 kHz.
Rx RF BW (MHz): The desired signal bandwidth, affecting analog and digital filters. The valid range is from 10 MHz to 200 MHz.
Passband and stopband weighting values function similarly to the Tx Profile.
Entering the AD9528 Parameters
The AD9528 clock distribution chip requires a voltage-controlled crystal oscillator (VCXO) and a reference clock.
- "Write AD9528 settings to file" checkbox: If checked, output files include AD9528 clock distribution settings. If unchecked, the GUI assumes default settings (30.72 MHz reference clock, 122.88 MHz VCXO).
- "Bypass PLL1": Allows injecting an external, low phase noise frequency directly into the AD9528 when the available VCXOs cannot accommodate the required device clock.
- AD9528 VCXO Freq (MHz): The on-chip or externally provided VCXO frequency. Change this if the VCXO is changed or provided externally. If external, check "Bypass PLL1".
- AD9528 RefClk A Freq (MHz): The network reference frequency, which can synchronize the evaluation system to a master test equipment clock. It is a submultiple of the VCXO frequency. Change only if the external frequency differs from the default 30.72 MHz.
The AD9528 filters reference clock noise but not VCXO noise. The AD9528 can generate output frequencies not integer-related to the VCXO or refclkA. The transceiver also multiplies the device clock frequency to generate internal clocks.
The on-board VCXO may need to be changed if 122.88 MHz does not allow for proper clock frequencies for the desired profile. Alternatively, PLL1 can be bypassed to inject an external frequency.
To verify settings, press "Generate Profiles" and check "Write AD9528 settings to file". If an error occurs, adjust the VCXO frequency or bypass PLL1. If no error occurs, determine the desired device clock frequency by checking the "Device Clock (MHz)" field and its available dividers.
Saving Output Files
After profile generation, files can be imported into customer system software or the TES GUI. The tool generates files containing parameters, FIR filter coefficients, and ADC coefficients. Additional "stf" files may be generated for frequency response plots. AD9528 parameters, if written, will appear in an extra file.
Using a New Profile
To import a new profile into the GUI, connect to a booted evaluation system, select "File" > "Load Custom Profile", and browse to the saved file. "stf" and clock files will load automatically. Ensure AD9528 settings are adjusted in the GUI if VCXO/refclk frequencies have changed.
How to Apply the Tool Output to a Customer System
To use a new profile in a customer system, new initialization files must be generated. With the profile loaded in the GUI, go to TOOLS > Create Script > select the desired format (e.g., Init .c Files). The talise_config.c file contains custom profile settings. All generated files, including stream files, should be utilized to avoid conflicts.
Advanced Settings
Checking the "Advanced settings" checkbox opens a window for additional parameter adjustments.
Tx Advanced Settings
Allows adjustment of anti-imaging analog filters after the DAC. The tool optimizes these based on "Tx Total RF BW (MHz)" for a balance between image rejection and FIR filter gain. The "Tx Baseband filter" is 2nd order, and the "Real pole" is 1st order.
Rx Advanced Settings
Allows adjustment of the Trans-impedance amplifier (TIA) analog filter corner independently from "Rx RF BW (MHz)".
Unsupported Function: The tool normally selects an Rx FIR decimation factor for optimal clock rates and sampling rates. If a specific decimation rate is required, it can be forced (1, 2, or 4).
Decimating Filters: The tool selects optimal decimating filters near the ADC. If sampling rate-based spurs are present, checking the "Force" box fixes the "Decimation mode" to the best value.
"Real IF mode Enable": Configures the tool and transceiver for "I" signal path data transfer, aligning with some baseband processor interface protocols.
Dual Band Modes: The transceiver supports dual band modes, splitting a received spectrum into two halves for independent handling by separate signal paths, each with independent numerically controlled oscillators and filters. Advanced settings allow access to these parameters.
Manipulating the Interactive Plots
Plot Information
After profile generation, the tool displays frequency response plots for all enabled signal paths (including loopback). Plots show markers, response curves, and performance information:
- Composite Analog Response: Total response of all analog filters.
- Composite Digital Response: Total response of all digital filters, including programmable FIR filters.
- Composite Final Response: Overall magnitude response of the entire signal path.
- Passband Ripple: Indicated by limit lines and text values.
- Stopband Ripple: Shown by limit lines and text for different Nyquist bands.
The Zoom Feature
Zooming: Hold the left mouse button to draw a rectangle for detailed view. Releasing the button zooms into that area. Repeatedly drawing further magnifies. Clicking the left mouse button at a location performs a quick 2x zoom.
Returning to Previous Zoom: Right-click and select "Zoom Out" to return to the previous level, or "Return to Original View" to reset the plot.
Axis Limiting: By default, zoom affects both axes. To limit zoom to a single axis, right-click, select "Zoom Options", and choose the desired style.
Examples
Using Pass Band and Stop Band Weights to Optimize Performance
Fourth-generation (4G) communication systems often use large ratios of sampling rates to bandwidths. Ratios like 1.2288 allow on-chip FIR filters to optimize both passband ripple and stopband rejection. Some applications require bandwidths very close to the sampling rate, necessitating additional optimization for FIR filters.
Example Scenario (ADRV9008-2 Tx/ORx):
Input Parameters:
- Tx Input Sample Rate: 245.76 MSPS
- Tx Total RF BW: 226 MHz
- Tx Primary Signal BW: 100 MHz
- ORx Output Sample Rate: 245.76 MSPS
- ORx RF BW: 226 MHz
Output Requirements:
- Tx Ripple: < 0.25 dB
- Tx Stopband rejection: > 45 dB
- ORx Ripple: < 0.5 dB
- ORx Stopband rejection: > 45 dB
With default weight ratios (1:1 for Tx and ORx), the profile yields Tx ripple of 0.11 dB and stopband rejection of -46.8 dB at 132.7 MHz. The ORx signal path shows a passband ripple of 0.21 dB and stopband rejection of -37.4 dB at 132.7 MHz, indicating a need for more weight on stopband rejection.
Increasing the Stop Band Weight to 10 improves stopband rejection but results in unacceptably high ripple. A weight of 6 balances passband ripple and stopband rejection goals.
Adjusting the AD9528 Settings to Enable a Custom Profile
This example demonstrates creating a custom profile requiring AD9528 setting adjustments for clock rates.
Scenario (ADRV9009-based application):
- Tx Sample Rate = Orx Sample Rate = Rx Sample Rate: 100 MSPS
- Tx Total BW = Orx RF BW = Tx Primary BW = Rx RF BW: 50 MHz
When these parameters are entered, generating a profile and checking "Write AD9528 settings to file" may return an error indicating no possible device clocks can be generated with the default 122.88 MHz VCXO rate. This requires changing the VCXO or bypassing PLL1.
If the VCXO is changed to 50 MHz, an error may occur if the AD9528 reference clock (e.g., 30.72 MHz) is not compatible. Changing the reference clock (e.g., to 25 MHz) can then provide valid options for Device Clock and Device Clock Divider that meet all system requirements.
Profile Generation Rules
The following tables list the rules used by the tool to evaluate custom profile creation, aiding in reducing iteration counts.
Constraints for the Tx Signal Path
| Parameter | Constraint |
|---|---|
| Tx Input Sample Rate (MHz) | Minimum: 30.625, Maximum: 500 |
| Relationship to ORx Sample Rate | Must equal the ORx Output Sample Rate (MHz) |
| Tx Total RF BW (MHz) (Absolute Limits) | Minimum: 10, Maximum: 450 |
| Tx Total RF BW (MHz) [INT1,2,4, and 8 modes]* | ≤ 0.92*Tx input Sample Rate (MHz) |
| Tx Total RF BW (MHz) [INT5 mode]* | ≤ 0.81*Tx input Sample Rate (MHz) |
| Tx Primary Signal BW (MHz) (Absolute Limits) | Minimum: 5, Maximum: 200 |
| Tx Primary Signal BW (MHz) [INT1,2,4, and 8 modes]* | ≤ 0.41*Tx input Sample Rate (MHz) |
| Tx Primary Signal BW (MHz) [DEC5 mode]* | ≤ 0.55*Tx input Sample Rate (MHz) |
| DAC Clock Rate (MHz) | Minimum: 980, Maximum: 2000 |
| Total Signal Path Interpolation | Minimum: 2, Maximum: 32 |
| Maximum Programmable FIR Input Rate (MSPS) | 500 |
| Maximum Programmable FIR Output Rate (MSPS) | 500 |
| Tx Programmable FIR Sample Processing Clock (DP_CLK) | (N * Tx Input Sample Rate) where N = 1, 2, 4 or 8 AND (N x Tx Input Sample Rate) ≤ 500 MHz |
| Tx Programmable FIR Taps | ((20*DP_CLK)/Tx Input Sample Rate (MHz)) with possible values of 20, 40, 60 or 80 |
*The transmit signal path final (closest to DAC) half-band filter stages can interpolate by x1, x2, x4, x8, and x5. Rx or ORx paths use decimation by 4 or 5. If Rx/ORx use x5 decimation, Tx must use interpolate-by-5 (INT5), which imposes tighter bandwidth-to-sampling rate ratio restrictions.
Constraints for the ORx Signal Path
| Parameter | Constraint |
|---|---|
| ORx Output Sample Rate (MHz) | Minimum: 30.625, Maximum: 500 |
| Relationship to Tx Sample Rate | Must equal the Tx Input Sample Rate (MHz) |
| Relationship to Rx Sample Rate | Must be a power-of-two multiple of Rx Output Sample Rate (MHz) |
| ORx RF BW (MHz) (Absolute Limits) | Minimum: 5, Maximum: 450 |
| Orx RF BW (MHz) [DEC4 mode]** | Minimum: ≥ 0.4*Orx Output Sample Rate (MHz) |
| Maximum Orx RF BW (MHz) [DEC5 mode]** | ≤ 0.92*Orx Output Sample Rate (MHz) |
| Orx TIA BW (MHz) (Advanced Settings) | Minimum: 0.4*Orx Output Sample Rate (MHz), Maximum: 0.82*Orx Output Sample Rate (MHz) |
| ADC Clock Rate (MHz) | Minimum: 980, Maximum: 2000 |
| Relationship to Rx ADC Rate | Must equal Rx ADC Clock Rate for ADRV9009 |
| Maximum Programmable FIR Input Rate (From HB1) (MSPS) | 500 |
| Maximum Half-Band 1 (HB1) Input Rate (MSPS) | 500 |
| Total Signal Path Interpolation | Minimum: 4, Maximum (DEC4 Mode)**: 32, Maximum (DEC5 Mode)**: 20 |
| Orx Programmable FIR Decimation | 1, 2, 4 |
| Orx Programmable FIR Sample Processing Clock (DP_CLK) | (N * Orx Output Sample Rate) where N = 1, 2, 4 or 8 AND (N x Orx Output Sample Rate) ≤ 500 MHz |
| Orx Programmable FIR Taps | ((24*DP_CLK)/Orx Output Sample Rate (MHz)) with possible values of 24, 48 and 72 |
**The first (closest to ADC) half-band stages in the Orx signal path can be configured to decimate by 4 or by 5, with different RF BW and total decimation limits.
Constraints for the Rx Signal Path
| Parameter | Constraint |
|---|---|
| Rx Output Sample Rate (MSPS) | Minimum: 25, Maximum: 370 |
| Relationship to ORx Sample Rate | ORx Output Sample Rate (MHz) must be a power-of-two multiple of the Rx Output Sample Rate (MHz) |
| RX RF BW (MHz) (Absolute Limits) | Minimum: 5, Maximum: 200 |
| RX RF BW (MHz) (Complex Mode) | Minimum: ≥ 0.4*ORx Output Sample Rate (MHz), Maximum: ≤ 0.82*ORx Output Sample Rate (MHz) |
| RX RF BW (MHz) (Real IF Mode) | Maximum: ≤ 0.41*ORx Output Sample Rate (MHz) |
| Signal Position in Rx Spectrum | Final output spectrum must have entire BW on one side of LO (DC) |
| ORx TIA BW (MHz) (Advanced Settings) | Minimum: 40, Maximum: 225 |
| ADC Clock Rate (MHz) | Minimum: 980, Maximum: 2000 |
| Relationship to ORx ADC Rate | Must equal ORx ADC Clock Rate for ADRV9009 |
| Maximum Programmable FIR Input Rate (From HB1) (MSPS) | 500 |
| Maximum Half-Band 1 (HB1) Input Rate (MSPS) | 500 |
| Total Signal Path Decimation (Not Including Dual Band Digital Downconverter (DDC) DC Half-Band) | Minimum: 4, Maximum (DEC4 Mode)***: 32, Maximum (DEC5 Mode)***: 20 |
| Rx Programmable FIR Decimation | 1, 2, 4 |
| Rx Programmable FIR Sample Processing Clock (DP_CLK) | (N * Rx Output Sample Rate) where N = 1, 2, 4 or 8 AND (N x Rx Output Sample Rate) ≤ 500 MHz |
| Rx Programmable FIR Taps | ((24*DP_CLK)/Rx Output Sample Rate (MHz)) with possible values of 24, 48 and 72 |
| DDC Mode | 370 |
| Maximum Output Rate with Filter Enabled (MSPS) | 0.4*DDC Half-Band Input Rate |
| Maximum BW (of One Band) | BW of the other band should be > (checking w/Aakash on greater than vs. less than) 0.6*DDC Half-Band Input Rate |
Constraints for the Loopback Rx Signal Path
| Parameter | Constraint |
|---|---|
| Loopback (LPBK) Rate at Programmable FIR output (MSPS) | Minimum: 20, Maximum: 500 |
| Relationship to ORx Signal Path | Must be same as ORx Output Sample Rate (MHz) |
| LPBK RF Signal BW (MHz) | Minimum: 5, Maximum: 200 |
| Relationship to Tx Signal Path | Must be same as Tx Input Sample Rate (MHz) |
| LPBK TIA BW (MHz) | 225 |
| LPBK ADC Clock Rate | Minimum: 980, Maximum: 2000 |
| Relationship to ORx Signal Path | Must be same as ORx ADC Rate |
| LPBK Programmable FIR Maximum Input Rate (MHz) | 500 |
| LPBK Half-Band 1 Maximum Input Rate (MHz) | 500 |
| LPBK Total Signal Path Decimation | Minimum: 4, Maximum (DEC4 Mode)***: 32, Maximum (DEC5 Mode)***: 20 |
| LPBK Programmable FIR Decimation | 1, 2, 4; same as on ORx |
| Available Options | 1, 2, or 4 |
| Relationship to ORx Signal Path | Must be same as ORx programmable FIR decimation |
| LPBK Programmable FIR Sample Processing Clock (DP_CLK) | (N * LPBK Output Sample Rate) where N = 1, 2, 4 or 8 AND (N x LPBK Output Sample Rate) ≤ 500 MHz |
| LPBK Programmable FIR Taps | ((24*DP_CLK)/Rx Output Sample Rate (MHz)) with possible values of 24, 48 and 72 |
| Options | ((24*DP_CLK)/Rx Output Sample Rate (MHz)) with possible values of 24, 48 and 72 |
| Relationship to ORx Signal Path | Must be same number of taps as ORx programmable FIR |
***The first (closest to ADC) half-band stages in the LPBK signal path can be configured to decimate by 4 or by 5, with different RF BW and total decimation limits.
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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Document identifier: UG16822-0-6/18(0)
