1 About This Guide

1.1 Purpose

The purpose of Gowin FP Comp IP User Guide is to help users learn the features and usage of Gowin FP Comp IP by providing descriptions of its functions, ports, timing, GUI, and reference design. Software screenshots and supported products listed in this manual are based on Gowin Software V1.9.9 Beta-3. As the software is subject to change without notice, some information may not remain relevant and may need to be adjusted according to the software in use.

1.2 Related Documents

The latest user guides are available on the GOWINSEMI website. Related documents can be found at www.gowinsemi.com:

• DS100, GW1N series of FPGA Products Data Sheet
• DS117, GW1NR series of FPGA Products Data Sheet
• DS821, GW1NS series of FPGA Products Data Sheet
• DS861, GW1NSR series of FPGA Products Data Sheet
• DS102, GW2A series of FPGA Products Data Sheet
• DS226, GW2AR series of FPGA Products Data Sheet
• DS971, GW2AN-18X & 9X Data Sheet
• DS976, GW2AN-55 Data Sheet
• SUG100, Gowin Software User Guide

1.3 Terminology and Abbreviations

The terminology and abbreviations used in this manual are shown in Table 1-1.

1.4 Support and Feedback

Gowin Semiconductor provides customers with comprehensive technical support. For any questions, comments, or suggestions, please feel free to contact Gowin Semiconductor directly using the information provided below.

Website: www.gowinsemi.com

E-mail: support@gowinsemi.com

2 Overview

Gowin FP Comp IP is designed to realize integer addition and division operations with less logic resources. Gowin FP Comp IP can compare two single-precision floating-point numbers. This IP supports optional output ports such as A=B, A!=B, A>B, A>=B, A<B, A<=B, and NaN (Not a Number).

Note: For the devices supported, you can click here to get the information.

2.1 Features

Supports optional output ports such as A=B, A!=B, A>B, A>=B, A<B, A<=B, and NaN (Not a Number).

2.2 Max. Frequency

The maximum frequency of Gowin FP Comp IP is mainly determined by the speed grade of the selected devices.

2.3 Latency

The latency of Gowin FP Comp IP is determined by the configuration parameters.

2.4 Resource Utilization

Gowin FP Comp IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Taking Gowin GW2A-55 series of FPGA as an instance, the resource utilization is shown in Table 2-2. For the resource utilization of other devices, please refer to later release information.

3 Functional Description

Gowin FP Comp IP can implement the comparison of two single-precision floating-point numbers. Users can configure parameters according to their requirements when generating this module.

4 Port List

The details of Gowin FP Comp IP IO ports are shown in Table 4-1, and the port diagram is shown in Figure 4-1.

Figure 4-1 Gowin FP Comp IP IO Port Diagram: A block diagram labeled 'FP_Comp' shows input signals: 'clk' (clock), 'rstn' (reset, active-low), 'ce' (clock enable, optional), 'data_a' (input a), and 'data_b' (input b). Output signals include 'aeb' (a=b, optional), 'aneb' (a!=b, optional), 'agb' (a>b, optional), 'ageb' (a>=b, optional), 'alb' (a<b, optional), 'aleb' (a<=b, optional), and 'unorder' (NaN, optional), plus a 'result' output.

5 Timing Description

This section describes the timing of Gowin FP Comp IP. The timing of Gowin FP Comp IP is shown in Figure 5-1.

Figure 5-1 Gowin FP Comp IP Signal Timing: A timing diagram illustrates signals over 10 clock cycles. It shows the 'clk' signal as a standard clock pulse train. 'rstn' is shown as active-low. 'data_a' and 'data_b' are input data signals. 'aeb' and 'aneb' represent output comparison results, appearing one clock cycle after the data inputs are stable.

6 GUI Configuration

6.1 IP Generation

Click "Tools > IP Core Generator > DSP and Mathematics" to call and configure FP Comp. A toolbar icon is also available to open the IP, as shown in Figure 6-1.

Figure 6-1 Open GUI Via Icon: This figure depicts the Gowin Software interface, highlighting the 'Tools' menu path: 'IP Core Generator' > 'DSP and Mathematics'. It also shows a toolbar icon that can be clicked to launch the FP Comp IP configuration.

6.2 Configuration Interface

Gowin FP Comp IP configuration interface is shown in Figure 6-2.

Figure 6-2 Gowin FP IP Configuration Interface: The Gowin FP IP Configuration Interface window is shown. It includes fields for 'Device' (e.g., GW2A-55), 'Part Number' (GW2A-LV55PG484C8/I7), 'Language' (Verilog), 'Module Name' (FP_Comp_Top), and 'File Name' (fp_comp). An 'Options' section allows selection of 'Optional Input Port' (Clock Enable) and 'Optional Output Port' (e.g., A equal B, A greater than B, A less than B, A not equal B, A greater than or equal B, A less than or equal B, Unorder). A 'Generation Config' section includes 'Create In' path and 'Disable I/O Insertion' checkbox. Buttons for '确定' (Confirm) and '取消' (Cancel) are present.

This manual takes the GW2A-55 chip and GW2A-LV55PG484C8/I7 part number as an example.

• Users can configure the path of the generated IP core folder in the "Create In" text box.
• Users can configure the generated IP file name in the "File Name" text box.
• Users can configure the generated IP module name in the "Module Name" text box.

7 Reference Design

Please see the Gowin FP Comp IP Reference Design for details at the Gowinsemi website.

8 File Delivery

8.1 Documentation

The delivery file of Gowin FP Comp IP includes documentation and reference design. The folder mainly contains the user guide in PDF version.

8.2 Reference Design

The Gowin FP Comp IP RefDesign folder contains the netlist file, user reference design, constraints file, top-level file, and project file, etc.