Gowin XCORR IP User Guide
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Disclaimer
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Version Information
| Date | Version | Description |
|---|---|---|
| 2019/02/08 | 1.0 | Initial version. |
| 2025/07/04 | 1.1 | - Updated 1.2 related documents; - Updated 3.3 Latency description; - Updated 3.4 Resource Utilization; - Updated Gowin XCORR IP port diagram, timing diagram, and interface screenshots. |
About This Manual
1.1 Manual Content
The Gowin XCORR IP User Guide primarily includes functional features, port descriptions, timing specifications, configuration and invocation, and reference designs. It aims to help users quickly understand the product features, characteristics, and usage methods of the Gowin XCORR IP. The software interface screenshots in this manual refer to version 1.9.11.02. Due to software version upgrades, some information may differ slightly; please refer to the information in your software version.
1.2 Related Documents
You can download and view the following related documents by logging into the Gowin Semiconductor website www.gowinsemi.com.cn:
- DS100, GW1N Series FPGA Product Datasheet
- DS117, GW1NR Series FPGA Product Datasheet
- DS821, GW1NS Series FPGA Product Datasheet
- DS861, GW1NSR Series FPGA Product Datasheet
- DS102, GW2A Series FPGA Product Datasheet
- DS226, GW2AR Series FPGA Product Datasheet
- DS976, GW2AN-55 Device Datasheet
- DS971, GW2AN-18X & 9X Device Datasheet
- DS961, GW2ANR Series FPGA Product Datasheet
- DS981, GW5AT Series FPGA Product Datasheet
- DS1103, GW5A Series FPGA Product Datasheet
- DS1239, GW5AST Series FPGA Product Datasheet
- DS1105, GW5AS Series FPGA Product Datasheet
- DS1108, GW5AR Series FPGA Product Datasheet
- DS1118, GW5ART Series FPGA Product Datasheet
- SUG100, Gowin Soft IP Core User Guide
1.3 Terms and Abbreviations
Table 1-1 lists the relevant terms, abbreviations, and their meanings used in this manual.
| Term/Abbreviation | Full Name | Meaning |
|---|---|---|
| ALU | Arithmetic Logic Unit | Arithmetic Logic Unit |
| BSRAM | Block Static Random Access Memory | Block Static Random Access Memory |
| DSP Macros | DSP Macros | DSP Macros |
| I/O Logic | Input/Output Logic | Input/Output Logic |
| LUT | Look-up Table | Look-up Table |
| REG | Register | Register |
1.4 Technical Support and Feedback
Gowin Semiconductor provides comprehensive technical support. If you have any questions or suggestions during use, please contact the company directly:
Website: www.gowinsemi.com.cn
E-mail: support@gowinsemi.com
Tel: +86 75582620391
Overview
2.1 Gowin XCORR IP Introduction
The Gowin XCORR IP is designed to perform cross-correlation operations.
| Gowin XCORR IP | |
|---|---|
| Logic Resources | See Table 3-1. |
| Delivered Files | |
| Design Files | Verilog |
| Reference Design | Verilog |
| TestBench | Verilog |
| Test Design Flow | |
| Synthesis Software | GowinSynthesis |
| Application Software | Gowin Software |
Note! You can log in to the Gowin Semiconductor website to view chip support information.
2.2 XCORR Introduction
Cross-correlation (XCORR) is an IP module designed to provide users with the functionality to compute the cross-correlation between two random input sequences. The Gowin XCORR IP can compute the cross-correlation between two random sequences and is a comprehensive cross-correlation operation IP. Its structural diagram is shown in Figure 2-1.
Figure 2-1 XCORR Structural Diagram
The diagram shows a block diagram illustrating the XCORR IP structure. Input sequences 'series_x' and 'series_y' are fed into memory blocks ('memx' and 'memy' respectively). The data then goes through a decision process based on 'lag'. Based on this, 'x_1' and 'y_1' are derived, multiplied, and accumulated to produce the 'result'.
Features and Performance
3.1 Main Features
- Can perform cross-correlation operations on random input sequences.
- Configurable input sequence length.
- Configurable data bit width.
- Configurable data delay.
3.2 Maximum Frequency
The maximum frequency of the Gowin XCORR IP is related to the configured input sequence length and data delay.
3.3 Latency
The output latency of the Gowin XCORR IP is the time corresponding to a configured delay.
3.4 Resource Utilization
The Gowin XCORR IP is implemented in Verilog. Performance and resource utilization may vary depending on the density, speed, and grade of the device used. Taking the Gowin GW5A-25 series FPGA as an example, the resource utilization of the Gowin XCORR IP is shown in Table 3-1. For application verification on other Gowin FPGAs, please refer to future releases.
| Device Series | Speed Grade | Device Name | Resource Utilization | Remarks |
|---|---|---|---|---|
| GW5A-25 | ES | Registers | 80 | Input Data Width = 17 Sequence Length = 1024 Data Delay = 3 |
| LUT | 246 | |||
| ALU | 24 | |||
| BSRAM | 2 | |||
| DSP | 1 |
Functional Description
4.1 XCORR Structure and Function
The Gowin XCORR IP can perform cross-correlation operations on two random sequences. Users can configure the sequence length, data bit width, and data delay as needed when generating the module. Its block diagram is shown in Figure 4-1.
Figure 4-1 Gowin XCORR IP Interface Implementation
The diagram shows the interface implementation of the Gowin XCORR IP. It includes input ports like 'clk', 'rstn', 'start', 'series_x', and 'series_y', and output ports like 'result', 'delay', 'complete', and 'in_ready'. The user inputs 'series_x' (sequence x) and 'series_y' (sequence y), and the IP calculates and outputs the 'result'.
4.2 Data Bit Width Setting
The data bit width can be configured through the GUI interface. This cross-correlation IP supports signed data, with the most significant bit as the sign bit. The maximum bit width is 18 bits, and the minimum is 16 bits.
4.3 Sequence Length Setting
The length of the input sequence can be configured through the GUI interface, with options including 256, 512, 1024, and 2048.
4.4 Data Delay Setting
The data delay can be configured through the GUI interface, with a selectable range from 1 to 16.
Port Description
Details of the Gowin XCORR IP IO ports are shown in Table 5-1.
| Signal | Direction | Description |
|---|---|---|
| series_x | input | Input random sequence series_x |
| series_y | input | Input random sequence series_y |
| clk | input | Clock signal |
| rstn | input | Reset signal (active low) |
| start | input | Start signal |
| result | output | Output result |
| delay | output | Delay signal (signed) |
| complete | output | Completion signal, result is valid when high |
| in_ready | output | Input ready signal |
The interface block diagram is shown in Figure 4-1.
Timing Description
This section describes the timing of the XCORR IP. The Gowin XCORR IP signal timing diagram is shown in Figure 6-1. Data input starts after the falling edge of the 'start' signal. After 'series_x' and 'series_y' are processed, the 'result' is output when the 'complete' signal arrives.
Figure 6-1 XCORR Signal Timing
The timing diagram illustrates the signal behavior over time. It shows the 'start' signal initiating the data input process for 'series_x' and 'series_y'. The 'complete' signal indicates when the 'result' is valid.
Invocation and Configuration
1. In the Gowin Semiconductor Gowin Synthesis software interface, under the 'Tools' menu, you can launch the IP Core Generator tool to invoke and configure the XCORR IP. After opening the IP Core Generator and creating a project, click 'IP Core Generator > Soft IP Core > DSP and Mathematics > XCORR' to open the XCORR IP, as shown in Figure 7-1.
Figure 7-1 Invoking XCORR
The image shows the IP Core Generator interface where the XCORR IP can be selected. The summary indicates that the Gowin XCORR IP can obtain all cross-correlation values of two random sequences within a maximum delay range, allowing users to understand the correlation between two sequences. Partial configuration, including data bit width, sequence length, and data delay, can be customized by the user.
2. The Gowin XCORR IP interface is shown in Figure 7-2. Users can configure the parameters in the figure according to their needs and click 'OK' to generate the XCORR IP.
Figure 7-2 XCORR Interface
The interface parameter configuration description is as follows:
- Input Data Width: Input data bit width selection (16-18);
- Output Data Width: Output bit width (read-only);
- Sequence Length: Input sequence length selection (256/512/1024/2048);
- Data Delay: Data delay (1-16).
Reference Design
Refer to the relevant test cases within 'ref_design'.
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