General Description
The EV-ADGS2414DSDZ is the evaluation board for the ADGS2414D, an octal SPST switch controlled by a serial peripheral interface (SPI). The SPI features robust error detection, including cyclic redundancy check (CRC), invalid read/write address detection, and SCLK count error detection. The ADGS2414D also supports burst mode for faster SPI command execution.
The evaluation board is controlled by the Analog Devices System Demonstration Platform (SDP) EVAL-SDP-CB1Z (SDP-B), which connects to a PC via USB. The board provides wire screw terminals for connecting to the source and drain pins of the ADGS2414D. Power is supplied via three screw terminals, and an optional digital logic supply can be provided via a fourth terminal or from the SDP-B. The EVAL-SDP-CB1Z (SDP-B) controller board is available from Analog Devices.
For detailed specifications of the ADGS2414D, consult the ADGS2414D data sheet in conjunction with this user guide.
Note: Please see the last page for important warnings and legal terms and conditions.
Features
- SPI with error detection (CRC, invalid addresses, SCLK count)
- Analog supply voltages: Dual supply (±4.5 V to ±16.5 V) or Single supply (5 V to 20 V)
- PC control via evaluation software and the EVAL-SDP-CB1Z (SDP-B) system demonstration platform
Evaluation Board Kit Contents
- EV-ADGS2414DSDZ evaluation board
Documents Needed
- ADGS2414D data sheet
Equipment Needed
- EVAL-SDP-CB1Z (SDP-B) controller board
- DC voltage source (±16.5 V for dual supply, 20 V for single supply)
- Optional 3.3 V digital logic supply
- Analog signal source
- Digital multimeter (DMM) or similar voltage measurement tool
Software Needed
- ACE software with EV-ADGS2414DSDZ plugin
Evaluation Board Photograph
Figure 1 shows a photograph of the EV-ADGS2414DSDZ evaluation board, displaying the ADGS2414D integrated circuit, along with various connectors (e.g., P1, P2, P3, P4, P5, P6, P7), screw terminals for power and signals, resistors (e.g., R1-R8, R10-R27), capacitors (C1-C4), jumpers (JP1, JP2), a push-button switch (SW1), and test points (TP17, TP18). The board also features silkscreen labels indicating component designators and pin functions.
Evaluation Board Hardware
Power Supplies
The P7 connector provides access to the ADGS2414D's supply pins (VDD, GND, VSS). The board supports dual-supply voltages from ±4.5 V to ±16.5 V. For single-supply operation, GND and VSS must be connected together, and the supply voltage can range from 5 V to 20 V. An optional 3.3 V digital logic supply is provided to the RESET/VL pins by the SDP-B controller board when JP1 is in Position B. If not using the SDP-B, a 2.7 V to 5.5 V supply can be connected to the RESET/VL pins via the EXT_VL screw terminal on P7, with JP1 set to Position A.
Input Signals
Screw connectors P1, P2, P5, and P6 are used to connect to the source and drain pins of the ADGS2414D. Additional subminiature version B (SMB) connector pads are available for extra connections. Each signal trace includes pads for 0603 components, allowing for the addition of a load to ground. A 0 Ω resistor is present in the signal path and can be replaced with a user-defined value to create a simple RC filter with the 0603 pads.
Link Options
Ensure link options on the EV-ADGS2414DSDZ are set correctly for the intended operating conditions. Table 1 lists the default link options for SDP-B control, and Table 2 describes their functions.
When using the SDP-B controller, set JP1 to Position B to prevent damage to the SDP-B.
Table 1. Link Options for SDP-B Control (Default)
| Link Number | Option |
|---|---|
| JP1 | B |
| JP2 | B |
Table 2. Link Functions
| Link Number | Function |
|---|---|
| JP1 | Selects the source of the VL voltage supplied to the ADGS2414D. Position A: EXT_VL from P7. Position B: 3.3 V from SDP-B controller. |
| JP2 | Selects the hardware reset method. Position A: SW1 push-button performs reset. Position B: SDP-B controller performs reset. |
Route Through Pins For Daisy Chains
Headers P3 and P4 provide access to pins for daisy-chaining multiple EV-ADGS2414DSDZ devices. To daisy-chain, connect CS_D, SCLK_D, and SDO_D from P4 of one board to CS, SCLK, and SDI on P3 of the next board, respectively. VL, GND, and VDD can also be shared via P3 and P4. VSS must be connected to each daisy-chained board separately from P7.
Evaluation Board Software
Installing the Software
The EV-ADGS2414DSDZ utilizes the Analog Devices Analysis, Control, Evaluation (ACE) software. ACE is a desktop application for evaluating and controlling multiple evaluation systems. The ACE installer includes necessary SDP drivers and .NET Framework 4. Install ACE before connecting the SDP-B controller board. Detailed installation and usage instructions are available on the Analog Devices website at www.analog.com/ace.
After ACE installation, the EV-ADGS2414DSDZ plugin appears when the application is opened.
Initial Set Up
To set up the EV-ADGS2414DSDZ:
- Connect the EV-ADGS2414DSDZ to the SDP-B controller board using the 120-pin connector.
- Connect the SDP-B controller board to the computer via its USB cable.
- Power the EV-ADGS2414DSDZ as described in the "Power Supplies" section.
- Launch the ACE application. The EV-ADGS2414DSDZ plugin will appear in the "Attached Hardware" section of the Start tab.
- Double-click the ADGS2414D Board plugin to open the ADGS2414D chip view, as shown in Figure 2.
Figure 2 displays the ADGS2414D chip view within the ACE software. It shows the eight switches (S1-S8) for configuring the device, status indicators for error flags (RW ERROR FLAG, SCLK ERROR FLAG, CRC ERROR FLAG), and control buttons for clearing flags, performing software reset (SW Reset), enabling burst mode, entering daisy chain mode, and performing hardware reset (HW Reset).
Block Diagram and Description
The ADGS2414D chip view in the ACE software is analogous to the functional block diagram found in the ADGS2414D data sheet. This allows for easy correlation between the evaluation board's functions and the data sheet descriptions. Refer to the ADGS2414D data sheet for a comprehensive explanation of each block, register, and setting.
Figure 3 presents the full-screen block diagram of the ADGS2414D chip view with labels. Table 3 details the functionality of each labeled block.
Figure 3 shows the ADGS2414D chip view with labeled blocks A through J. These labels correspond to interactive elements and status indicators within the ACE software interface for controlling and monitoring the ADGS2414D.
Table 3. Block Diagram Functions
| Label | Function |
|---|---|
| A | The eight switches (SW1 to SW8) configure the device as open or closed. Click a switch to configure it. |
| B | Check boxes for INVALID RW ENABLE, SCLK COUNT ENABLE, and CRC ENABLE. Select or clear these to enable or disable SPI error detection features. |
| C | Check box for BURST MODE ENABLE. Select or clear to enable or disable burst mode. |
| D | Indicators for RW ERROR FLAG, SCLK ERROR FLAG, and CRC ERROR FLAG. These illuminate red when error flags are asserted. |
| E | Clear Flags button to clear the error flags register. |
| F | Apply Changes button to apply all modified values to the devices. |
| G | Enter Daisy Chain Mode button to enable daisy-chain mode for connected evaluation boards. |
| H | SW Reset button to perform a software reset on the ADGS2414D. |
| I | HW Reset button to perform a hardware reset on the ADGS2414D. JP2 must be set to Position B. |
| J | Proceed to Memory Map button to access the ADGS2414D Memory Map view. |
Daisy-Chain Mode
Multiple ADGS2414D devices can be daisy-chained for configuration using minimal digital lines, increasing channel density. Integrated passive components reduce the need for external ones.
To enter daisy-chain mode, click "Enter Daisy Chain Mode" to open the view shown in Figure 4. Select the number of boards in the chain using the "Number of Devices in Daisy Chain" dropdown. Check the boxes for desired switch states and click "Apply Changes" to write values. To exit daisy-chain mode, perform a hardware reset by clicking the "HW Reset" button (JP2 must be set to Position B) or by pressing the physical hardware reset button on the evaluation board.
Figure 4 illustrates the Daisy Chain Mode view in the ACE software. It allows users to configure multiple daisy-chained devices, set the number of devices in the chain, and select individual switch states for each device.
Memory Map
All registers are accessible via the ADGS2414D Memory Map view. Click "Proceed to Memory Map" to access this view, which allows bit-level editing of registers. Shaded bits are read-only and cannot be accessed in ACE.
Modified bits or registers are shown in bold and have not yet been transferred to the evaluation board. Click "Apply Changes" to transfer these modifications. Changes in the Memory Map view correspond to the block diagram; enabling an internal register bit will reflect this on the block diagram.
Figure 5 shows the ADGS2414D Memory Map view with registers like SW_DATA, ERR_CONFIG, ERR_FLAGS, and BURST_EN, displaying their hexadecimal and binary data. Figure 6 shows the same view with unapplied changes to the SW_DATA register, indicated by bold text and modified binary values.
Evaluation Board Schematics and Artwork
This section provides detailed schematics and PCB layout views of the EV-ADGS2414DSDZ evaluation board.
Schematics
Figure 7 displays Schematic 1 of the EV-ADGS2414DSDZ, illustrating the main ADGS2414D chip connections, associated resistors, and screw terminals for signal and power routing.
Figure 8 presents Schematic 2, detailing connections to the J1 connector, an external EEPROM (U2), and other interface components.
Figure 9 shows Schematic 3, which depicts the power supply filtering, the reset circuit involving switch SW1 and jumper JP2, and an ADG819 multiplexer/switch (U3).
PCB Layout
Figure 10 shows the silkscreen layer of the EV-ADGS2414DSDZ PCB, indicating component placement and labels for easy identification.
Figures 11, 12, 13, and 14 provide views of the different layers of the EV-ADGS2414DSDZ PCB layout: Top Layer, Layer 2, Layer 3, and Bottom Layer, respectively. These diagrams illustrate the physical routing of traces and placement of components on the board.
Ordering Information
Bill of Materials
Table 4 lists the Bill of Materials for the EV-ADGS2414DSDZ, detailing the components used on the evaluation board.
| Reference Designator | Description |
|---|---|
| C1, C2 | 50 V tantalum capacitor, 10 µF, D size |
| C3, C4 | 50 V, X7R, multilayer ceramic capacitor, 0.1 µF, 0603 |
| D1 to D8 | Not placed |
| S1 to S8 | Not placed |
| T-D1 to T-D8, T-S1 to T-S8 | Red test point |
| TP17, TP18 | Black test point |
| P1, P2, P5 to P7 | 4-pin terminal block, 5 mm pitch |
| P3, P4 | Through hole, header, 4 × 2, 2.54 mm |
| J1 | 120-way connector, 0.6 mm pitch |
| JP1, JP2 | 3-pin single inline (SIL) header and shorting link |
| R1 to R8, R17 to R29, R32, R33, R35, R41 to R48, R55, R56, R59, R60 | Resistor, 0 Ω, 0603, 1% |
| R9 to R16, R30, R31, R34, R36 to R40, R50 to R53 | Resistor, 10 kΩ, 0.063 W, 1%, 0603 |
| R58 | Resistor, 1 MΩ, 0.25 W, 1%, 1206 |
| R49 | Resistor, 100 kΩ, 0.063 W, 1%, 0603 |
| R54, R57 | Resistor, 100 kΩ, 0.063 W, 1%, 0603 |
| SW1 | Surface-mount device (SMD) push-button switch |
| U1 | ADGS2414D, SPI controlled, octal SPST switch |
| U2 | 32 kΩ, I2C serial electronically erasable programmable read only memory (EEPROM) |
| U3 | ADG819, 1.8 V to 5.5 V, 2:1 multiplexer and SPDT switch |
Note: I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
Important Information
ESD Caution
This device is ESD (electrostatic discharge) sensitive. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
Use of the evaluation board is subject to the terms and conditions outlined in the Agreement. By using the board, the customer agrees to these terms. Analog Devices, Inc. (ADI) grants a limited, non-exclusive license for evaluation purposes only. The board is not sold, and all rights are reserved by ADI. The board and agreement are considered confidential. Customer agrees not to disassemble, decompile, or reverse engineer the board. ADI disclaims all warranties, express or implied, including merchantability and fitness for a particular purpose. ADI's total liability is limited to $100.00. Export of the board is subject to U.S. federal laws and regulations. The governing law is Massachusetts, and any legal actions will be heard in Suffolk County courts.
Mixed-signal and digital signal processing ICs | Analog Devices
