TPL5010 Nanopower System Timer with Watchdog
Manufacturer: TEXAS INSTRUMENTS
Document Revision: ZHCSEK6 – JANUARY 2015
1 Features
- Supply Voltage Range: 1.8V to 5.5V
- 2.5V Supply Current: 35nA (typical)
- Selectable Time Interval Range: 100ms to 7200s
- Timer Accuracy: 1% (typical)
- Time Interval Selectable via External Resistor
- Watchdog Timer Functionality
- Manual Reset
2 Applications
- Battery-Powered Systems
- Internet of Things (IoT)
- Intrusion Detection
- Tamper Detection
- Home Automation Sensors
- Temperature Monitoring Devices
- Consumer Electronics
- Remote Sensors
- White Goods
3 Description
The TPL5010 is a nanopower system timer with a watchdog feature, ideal for low-power applications and system wake-up in duty-cycled or battery-powered systems. While microcontrollers (µCs) can use their internal timers to wake the system, their typical sleep current can consume up to 60-80% of the total system current. The TPL5010's ultra-low 35nA current consumption allows the µC to remain in a lower power mode, significantly reducing battery size and extending life. It offers selectable time intervals from 100ms to 7200s, suitable for interrupt-driven applications. The watchdog function is crucial for safety-critical systems (e.g., EN50271 compliant) and is implemented with minimal power overhead. The TPL5010 is available in a 6-pin SOT23 package.
Component Information
| Device Model | Package | Package Size (Nominal) |
|---|---|---|
| TPL5010 | SOT23 (6) | 3.00mm x 3.00mm |
(1) For available packages, refer to the datasheet appendix.
4 Simplified Application Circuit Diagram
The diagram shows the TPL5010 connected to a power management block, a battery, and a microcontroller (µC). The TPL5010 has VDD, GND, DELAY/M_RST, RSTn, WAKE, and DONE pins. The power management block connects to VIN, VOUT, and GND, with a battery connected to VIN. The µC has VDD, GND, RSTn, and GPIO pins. An external resistor (REXT) is connected between the TPL5010's DELAY/M_RST pin and GND to set the time interval. A pull-up resistor (Rp) is shown connected to the µC's RSTn pin.
5 Revision History
| Date | Revision | Notes |
|---|---|---|
| January 2015 | * | First released. |
6 Pin Configuration and Functions
6-Lead SOT23 Top View
The TPL5010 is housed in a 6-lead SOT23 package. The pinout is as follows:
- Pin 1: VDD (Power Supply)
- Pin 2: GND (Ground)
- Pin 3: DELAY/M_RST (Time Interval Set and Manual Reset)
- Pin 4: DONE (Logic Input for watchdog functionality)
- Pin 5: WAKE (Timer output signal)
- Pin 6: RSTn (Reset Output)
Pin Functions
| PIN NO. | NAME | TYPE(1) | DESCRIPTION | APPLICATION INFORMATION |
|---|---|---|---|---|
| 1 | VDD | P | Supply voltage | |
| 2 | GND | G | Ground | |
| 3 | DELAY/ M_RST | I | Time Interval set and Manual Reset | Resistance between this pin and GND is used to select the time interval. The reset switch is also connected to this pin. |
| 4 | DONE | I | Logic Input for watchdog functionality | Digital signal driven by the µC to indicate successful processing of the WAKE signal. |
| 5 | WAKE | O | Timer output signal generated every tIP period. | Digital pulsed signal to wake up the µC at the end of the programmed time interval. |
| 6 | RSTn | O | Reset Output (open drain output) | Digital signal to RESET the µC, pull-up resistance is required |
(1) G= Ground, P= Power, O= Output, I= Input.
7 Specifications
7.1 Absolute Maximum Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | -0.3 | 6.0 | V |
| Input Voltage at any pin(2) | -0.3 | VDD + 0.3 | V |
| Input Current on any pin | -5 | +5 | mA |
| Storage Temperature, Tstg | -65 | 150 | °C |
| Junction Temperature, TJ(3) | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage between any two pins should not exceed 6V.
(3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
7.2 ESD Ratings
| V(ESD) | Electrostatic discharge | VALUE | UNIT |
|---|---|---|---|
| Human Body Model, per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V | |
| Charged-device model (CDM), per JEDEC specification JESD22-101(2) | ±250 | V |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | 1.8 | 5.5 | V |
| Temperature Range | -40 | 105 | °C |
7.4 Thermal Information
| THERMAL METRIC(1) | TPL5010 SOT23 6 PINS | UNIT |
|---|---|---|
| RθJA | 163 | °C/W |
| RθJC(top) | 26 | |
| RθJB | 57 | |
| ΨJT | 7.5 | |
| ΨJB | 57 | |
| RθJC(bot) | N/A |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
Specifications are for TA= 25°C, VDD-GND=2.5 V, unless otherwise stated.
| PARAMETER | TEST CONDITIONS | MIN(2) | TYP(3) | MAX(2) | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLY | ||||||
| IDD | Supply current(4) | Operation mode | 35 | 50 | nA | |
| Digital conversion of external resistance (Rext) | 200 | 400 | µA | |||
| TIMER | ||||||
| tIP | Time Interval Period | 1650 selectable Time Intervals | Min time interval | 100 | ms | |
| Max time interval | 7200 | s | ||||
| Time Interval Setting Accuracy(5) | Excluding the precision of Rext | ±0.6% | % | |||
| Time Interval Setting Accuracy over supply voltage | 1.8V ≤ VDD ≤ 5.5V | ±25 | ppm/V | |||
| tOSC | Oscillator Accuracy | -0.5% | 0.5% | % | ||
| Oscillator Accuracy over temperature(6) | -40°C ≤TA≤105°C | ±100 | ±400 | ppm/°C | ||
| Oscillator Accuracy over supply voltage | 1.8V ≤ VDD ≤ 5.5V | ±0.4 | %/V | |||
| Oscillator Accuracy over life time(7) | 0.24% | % | ||||
| tDONE | DONE Pulse width(6) | 100 | ns | |||
| tRSTn | RSTn Pulse width | 320 | ms | |||
| tWAKE | WAKE Pulse width | 20 | ms | |||
| t_Rext | Time to convert Rext | 100 | 120 | ms | ||
| DIGITAL LOGIC LEVELS | ||||||
| VIH | Logic High Threshold DONE pin | 0.7xVDD | V | |||
| VIL | Logic Low Threshold DONE pin | 0.3xVDD | V | |||
| VOH | Logic output High Level WAKE pin | Iout = 100 µA Iout = 1 mA | VDD-0.3 VDD-0.7 | V | ||
| VOL | Logic output Low Level WAKE pin | Iout = -100 µA Iout = -1 mA | 0.3 0.7 | V | ||
| VOLRSTn | RSTn Logic output Low Level | IOL= -1 mA | 0.3 | V | ||
| VIOHRSTn | RSTn High Level output current | VOHRSTn=VDD | 1 | nA | ||
| VIHM_RST | Logic High Threshold DELAY/M_RST pin | 1.5 | V | |||
(1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD.
(5) The accuracy for time interval settings below 1second is ±100ms.
(6) This parameter is specified by design and/or characterization and is not tested in production.
(7) Operational life time test procedure equivalent to 10 years.
7.6 Timing Requirements
| MIN(1) | NOM(2) | MAX(1) | UNIT | ||
|---|---|---|---|---|---|
| trRSTn | Rise Time RSTn(3) | Capacitive load 50 pF, Rpull-up 100kΩ | 11 | µs | |
| tfRSTn | Fall Time RSTn(3) | Capacitive load 50 pF, Rpull-up 100kΩ | 50 | ns | |
| trWAKE | Rise Time WAKE(3) | Capacitive load 50 pF | 50 | ns | |
| tfWAKE | Fall Time WAKE(3) | Capacitive load 50 pF | 50 | ns | |
| tDDONE | DONE to RSTn or WAKE to DONE delay | Min delay(4) Max delay(4) | 100 tIP-20ms | ns ms | |
| tM_RST | Valid Manual Reset | Observation time 30ms | 20 | ms | |
| tDB | De-bounce Manual Reset | 20 | ms |
(1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(3) This parameter is specified by design and/or characterization and is not tested in production.
(4) In case of RSTn from its falling edge, in case of WAKE, from its rising edge.
Figure 1. TPL5010 Timing Diagram: This diagram illustrates the timing relationships between VDD, WAKE, DONE, RSTn, and DELAY/M_RST signals. It shows pulse widths (tRSTn, tWAKE, tDONE), delays (tDDONE), manual reset timing (tM_RST, tDB), and the main time interval (tIP).
7.7 Typical Characteristics
Figure 2. IDD vs. VDD: Shows supply current (nA) versus supply voltage (V) for different ambient temperatures (-40°C, 25°C, 70°C, 105°C).
Figure 3. IDD vs. Temperature: Shows supply current (nA) versus temperature (°C) for different supply voltages (1.8V, 2.5V, 3.3V, 5.5V).
Figure 4. Oscillator Accuracy vs. VDD: Displays oscillator accuracy (%) versus supply voltage (V) for different ambient temperatures.
Figure 5. Oscillator Accuracy vs. Temperature: Displays oscillator accuracy (%) versus temperature (°C) for different supply voltages.
Figure 6. IDD vs. Time: A logarithmic plot showing supply current (µA) versus time (s), illustrating the power-on reset (POR) phase and the subsequent timer mode operation.
Figure 7. Time Interval Setting Accuracy: A histogram showing the frequency distribution of accuracy (%) for time intervals between 1s and 7200s, based on over 20,000 observations.
8 Detailed Description
8.1 Overview
The TPL5010 is a system wake-up timer with an integrated watchdog feature, designed for low-power applications. It is suitable for interrupt-driven applications and offers selectable timing intervals ranging from 100ms to 7200s.
8.2 Functional Block Diagram
The TPL5010 block diagram shows a Low Frequency Oscillator, a Frequency Divider, Logic Control, and a Decoder & Manual Reset Detector. These blocks are connected to VDD, GND, DELAY/M_RST, RSTn, WAKE, and DONE pins.
8.3 Feature Description
The watchdog function is implemented using the DONE, WAKE, and RSTn signals. The TPL5010 generates a periodic WAKE pulse to a µC in sleep or standby mode. The µC must respond by asserting a DONE signal at least 20ms before the next WAKE pulse. Failure to do so results in the TPL5010 asserting the RSTn signal to reset the µC. A manual reset can be triggered by momentarily pulling the DELAY/M_RST pin high (to VDD).
8.3.1 WAKE
The WAKE pulse is output by the TPL5010 when the programmed time interval begins. This signal is normally low.
8.3.2 DONE
The DONE pin is driven by the µC to signal successful processing of the WAKE signal. The TPL5010 recognizes a low-to-high transition on DONE as valid. If multiple DONE signals occur within an interval, only the first is processed. A DONE signal received while WAKE is high will cause WAKE to go low immediately.
8.3.3 RSTn
A pull-up resistor is required for the RSTn interface between the TPL5010 and the µC (100kΩ recommended). RSTn is asserted (LOW) during Power-On Reset (POR) and REXT reading. RSTn is asserted LOW under two conditions: 1. If the DELAY/M_RST pin is high for approximately 20ms (two oscillator cycles). 2. If the DONE signal is not received at least 20ms before the next WAKE rising edge.
8.4 Device Functional Modes
8.4.1 Startup
During startup, after POR, the TPL5010 measures the resistance connected to the DELAY/M_RST pin to determine the time interval for WAKE. This measurement takes tR_EXT, during which a constant current flows into REXT.
Figure 9. Startup Timing Diagram: Shows WAKE, DONE, RSTn, and DELAY/M_RST signals during startup, including the resistance reading phase.
8.4.2 Normal Operating Mode
In normal operation, the TPL5010 generates periodic WAKE pulses in response to valid DONE pulses from the µC. If a manual reset is applied (DELAY/M_RST high) or if the µC fails to provide a DONE pulse in time, the TPL5010 asserts RSTn and restarts its internal counters.
8.5 Programming
8.5.1 Configuring the WAKE Interval with the DELAY/M_RST Pin
The time interval (tIP) between WAKE pulses is set by an external resistance (REXT) connected between the DELAY/M_RST pin and GND. The REXT range is 500Ω to 170kΩ; a 1% precision resistor is recommended. The REXT value is converted once after POR.
The time between RESET signals or between a RESET and a WAKE pulse is the sum of the programmed time interval and the RSTn pulse width (tRSTn).
8.5.2 Manual Reset
Connecting VDD to the DELAY/M_RST pin initiates a manual reset. The time interval setting is bypassed. If manual reset occurs during POR or reading, these operations are aborted and restarted upon release. A valid manual reset pulse must last at least 20ms (observation time 30ms). A valid manual reset clears all counters; they restart after the high voltage on DELAY/M_RST is removed and tRSTn elapses.
Figure 10. Manual Reset Timing Diagram: Illustrates WAKE, DONE, RSTn, and DELAY/M_RST signals during a manual reset event, showing valid and invalid reset conditions.
8.5.2.1 DELAY/M_RST
An REXT between 500Ω and 170kΩ is required to select a time interval. Initially, DELAY/M_RST is connected to an analog chain for resistance reading, then switched to a digital circuit. The manual reset detection includes a de-bounce feature to ignore glitches. A valid manual reset asserts RSTn LOW after tM_RST, remaining LOW for tM_RST + tDB + tRSTn. The RSTn signal may have an uncertainty of ±5ms due to the asynchronous nature of the reset.
A valid manual reset sets output signals to their defaults: WAKE = LOW, RSTn = asserted LOW.
8.5.2.2 Circuitry
Manual reset can be implemented with a momentary mechanical switch. Two approaches are offered based on power consumption constraints.
8.5.3 Timer Interval Selection Using External Resistance
The time interval (T) is set using the external resistance REXT according to the formula:
REXT = ( -b + √(b² - 4a(c - 100T)) ) / 2a
Where:
- T is the desired time interval in seconds.
- REXT is the resistance value in Ω.
- a, b, c are coefficients dependent on the time interval range.
Table 1. Coefficients for Equation 1: Provides coefficients a, b, and c for different time interval ranges (1s to >1000s).
Example: For a required time interval of 8s, coefficient set 2 is used. The calculation yields REXT = 10.18 kΩ.
Table 2. First 9 Time Intervals: Lists example tIP values (100ms to 900ms) and corresponding REXT values, including parallel resistor combinations.
Table 3. Most Common Time Intervals Between 1s to 2h: Lists common tIP values (1s to 2h) and corresponding REXT values, including parallel resistor combinations.
8.5.4 Quantization Error
The TPL5010 offers 1650 discrete timer intervals. The first 9 are multiples of 100ms, and the remaining 1641 cover 1s to 7200s. Quantization error arises from these discrete steps. The error can be calculated using the provided formulae:
Err = 100 * (TDESIRED - TADC) / TDESIRED
TADC = INT[ (1/a) * (1 + (RD/100)2 + (RD/100) + c) ]
RD = INT[ REXT/100 ]
Where REXT is from Equation 1, and a, b, c are from Table 1.
8.5.5 Error Due to Real External Resistance
Theoretical REXT values may not be standard resistor values. Using parallel combinations of standard values can approximate the theoretical value but introduces tolerance errors. The accuracy can be evaluated by calculating REXT_MIN, REXT_MAX, then TADC_MIN, TADC_MAX, and finally the error using Equation 3.
Example: For Tdesired = 600s, REXT = 57.44kΩ. Using parallel 1% tolerance resistors (107kΩ || 124kΩ) results in an equivalent resistance uncertainty of 0.82%, leading to an error range of -1.88% / +2.19%.
9 Application and Implementation
NOTE: Information in this section is not part of the TI component specification and is provided for customer convenience. TI does not warrant accuracy or completeness.
9.1 Application Information
Low current consumption is a key constraint in battery-powered applications. The TPL5010 is ideal for monitoring environmental conditions at fixed intervals. It significantly improves power consumption by enabling µCs to remain in low-power modes, consuming only tens of nA.
9.2 Typical Application
The TPL5010 can be used with environment sensors to create low-power data loggers (e.g., air quality). In such applications, the µC and sensor front-end spend most time in idle state, waiting for logging intervals (hundreds of milliseconds). Figure 13 illustrates a data logging application using a µC and a gas sensor front-end (LMP91000).
Figure 13. Data-logger Block Diagram: Depicts a system with a Lithium-ion battery, Power Management, TPL5010, a µC (e.g., MSP430), and a gas sensor (LMP91000). The TPL5010's DELAY/M_RST pin is connected via REXT to GND. The µC's RSTn pin is pulled up by Rp. The system includes inputs for buttons (Keyboard) and a display.
9.2.1 Design Requirements
The primary design driver is low current consumption to maximize battery life. The TPL5010 facilitates this by allowing the µC to enter its lowest power mode, while the TPL5010 manages the watchdog and timing functions.
9.2.2 Detailed Design Procedure
Designing for battery life requires careful selection of low-power components (voltage reference, µC, display). Power consumption analysis for different operating modes is crucial. The TPL5010 aids in implementing watchdog and wake-up timing functions, especially for µCs like the MSP430 family. After power budget calculation, the appropriate time interval can be selected to meet application constraints and maximize battery life.
9.2.3 Application Curves
Figure 14. Effect of TPL5010 on Current Consumption: A graph comparing current consumption over time, showing a lower overall consumption profile when the TPL5010 is used compared to a system without it.
10 Power Supply Recommendations
The TPL5010 operates from a supply voltage between 1.8V and 5.5V. A 0.1µF multilayer ceramic bypass capacitor (X7R) between VDD and GND is recommended.
11 Layout
11.1 Layout Guidelines
The DELAY/M_RST pin is sensitive to parasitic capacitance. Traces connecting to this pin and its associated resistor to GND should be kept as short as possible. This minimizes capacitance, which can affect the initial time interval setup. Signal integrity on WAKE and RSTn pins is also improved by keeping trace lengths short between the TPL5010 and the µC.
11.2 Layout Example
Figure 15. Layout Example: Shows a PCB layout example for the TPL5010, including placement for a manual reset switch, C1 (bypass capacitor), REXT, and the TPL5010 itself, with connections to VDD, GND, RSTn, WAKE, DONE, and DELAY/M_RST. It also shows recommended placement for the µC and its associated components.
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 ESD Warning
These devices contain internal ESD protection. Handle with care to prevent damage from electrostatic discharge.
12.3 Glossary
Refer to SLYZ022 — TI Glossary for terms, acronyms, and definitions.
13 Mechanical, Packaging, and Ordering Information
This section provides mechanical dimensions, package information, and ordering details for the TPL5010. The information is subject to change without notice.
Packaging Information Summary
The TPL5010 is available in the SOT-23-THIN (DDC) package. Key details include:
- Orderable Devices: TPL5010DDCR, TPL5010DDCT
- Package Type: SOT-23-THIN (DDC)
- Pins: 6
- Eco Plan: Green (RoHS & no Sb/Br)
- MSL Peak Temp: Level-1-260C-UNLIM
- Op Temp: -40°C to 105°C
- Device Marking: ZAKX
(1) Marketing status definitions (ACTIVE, LIFEBUY, NRND, PREVIEW, OBSOLETE) are provided.
(2) Eco Plan details (Pb-Free, Green) are available via TI's website.
(3) MSL rating according to JEDEC standards.
Mechanical Data (SOT-23 Package)
The SOT-23 package is a small outline package with dimensions typically around 3mm x 3mm. Detailed linear dimensions and tolerances are provided in millimeters.
Land Pattern Data
Recommended land pattern and stencil openings for the SOT-23 package are provided for PCB assembly, based on standard stencil thickness.
Important Notice and Disclaimer
Texas Instruments (TI) and its subsidiaries reserve the right to make corrections, enhancements, modifications, and improvements to their products and services, and to discontinue products and services. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants the performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing of all parameters is not necessarily performed on each device. TI does not assume any liability for applications assistance or the design of the customer's products. Customers are responsible for their applications' design and for ensuring compliance with applicable laws and regulations. TI does not grant any license, whether express, implied, by estoppel or otherwise, under any patent, copyright, mask work right, or other intellectual property right of TI covering or relating to its products or services. Information provided by TI is believed to be accurate and reliable, but TI does not warrant its accuracy or completeness. TI's products are not authorized for use in life-critical applications (such as medical devices or safety systems) unless an explicit, written agreement has been executed between TI and the customer. Customers are solely responsible for the design and implementation of safety-critical applications and for ensuring compliance with all applicable laws, regulations, and safety standards.
