TPL5010 Nano-Power System Timer With Watchdog Function
1 Features
- Supply Voltage From 1.8 V to 5.5 V
- Current Consumption at 2.5 V and 35 nA (Typical)
- Selectable Time Intervals: 100 ms to 7200 s
- Timer Accuracy: 1% (Typical)
- Resistor Selectable Time Interval
- Watchdog Functionality
- Manual Reset
2 Applications
- Battery-Powered Systems
- Internet of Things (IoT)
- Intruder Detection
- Tamper Detection
- Home Automation Sensors
- Thermostats
- Consumer Electronics
- Remote Sensors
- White Goods
3 Description
The TPL5010 Nano Timer is an ultra-low power timer with a watchdog feature designed for system wake up in duty-cycled, battery-powered applications such as those in IoT. Many of these applications require the use of a microcontroller (µC), so it is desirable to keep the µC in a low power mode to maximize current savings, waking up only during certain time intervals to collect data or service an interrupt. Although the internal timer of the µC can be used for system wake-up, it can single-handedly consume microamps of total system current.
Consuming only 35 nA, the TPL5010 can replace the functionality of the integrated µC timer. This allows the µC to be placed in a much lower power mode, with the internal timer off, returning only to active mode upon an interrupt by the TPL5010. By offering power savings of almost two orders of magnitude, the TPL5010 enables the use of significantly smaller batteries for energy harvesting or wireless sensor applications. The TPL5010 provides selectable timing intervals from 100 ms to 7200 s and is designed for interrupt-driven applications. Some standards (such as EN50271) require implementation of a watchdog for safety, and the TPL5010 realizes this watchdog function at almost no additional power consumption. The TPL5010 is available in a 6-pin SOT23 package.
Device Information
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPL5010 | SOT23 (6) | 3.00 mm x 3.00 mm |
Simplified Application Schematic: A block diagram shows a battery connected to a POWER MANAGEMENT block, which then connects to the TPL5010. The TPL5010 has pins VDD, GND, DELAY/M_RST, RSTn, WAKE, and DONE. VDD is connected to a microcontroller's VDD, and GND to GND. DELAY/M_RST is connected to an external resistor (REXT) to GND. RSTn and WAKE are outputs to the microcontroller, and DONE is an input from the microcontroller. Rp is shown as a pull-up resistor on RSTn.
4 Revision History
Changes from Original (January 2015) to Revision A:
- Added TPL5x1x Family of Nano Timers table.
- Changed TADC and REXT equations in the Quantization Error section.
- Added Receiving Notification of Documentation Updates section.
5 Device Comparison Table
TPL5x1x Family of Nano Timers:
| PART NUMBER | Special Features | Output | Rating |
|---|---|---|---|
| TPL5010 | Low Power Timer, Watchdog Functionality | Active High | Catalog |
| TPL5010Q | Low Power Timer, Watchdog Functionality | Active High | Automotive |
| TPL5111 | Low Power Timer, Power Gating MOS-Driver | Active High | Catalog |
| TPL5110 | Low Power Timer, Power Gating MOS-Driver | Active Low | Catalog |
6 Pin Configuration and Functions
The TPL5010 is available in a 6-Lead SOT-23 package.
Pin Configuration: A top view diagram shows the SOT-23 package with pins numbered 1 through 6. Pin 1 is VDD, Pin 2 is GND, Pin 3 is DELAY/M_RST, Pin 4 is DONE, Pin 5 is WAKE, and Pin 6 is RSTn.
| PIN NO. | NAME | TYPE | DESCRIPTION | APPLICATION INFORMATION |
|---|---|---|---|---|
| 1 | VDD | P | Supply voltage | |
| 2 | GND | G | Ground | |
| 3 | DELAY/ M_RST | I | Time Interval set and Manual Reset | Resistance between this pin and GND is used to select the time interval. The reset switch is also connected to this pin. |
| 4 | DONE | I | Logic Input for watchdog functionality | Digital signal driven by the µC to indicate successful processing of the WAKE signal. |
| 5 | WAKE | O | Timer output signal generated every tIP period. | Digital pulsed signal to wake up the µC at the end of the programmed time interval. |
| 6 | RSTn | O | Reset Output (open drain output) | Digital signal to RESET the µC, pullup resistance is required. |
7 Specifications
7.1 Absolute Maximum Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | -0.3 | 6 | V |
| Input Voltage at any pin | -0.3 | VDD + 0.3 | V |
| Input Current on any pin | -5 | +5 | mA |
| Junction Temperature, TJ | 150 | °C | |
| Storage Temperature, Tstg | -65 | 150 | °C |
7.2 ESD Ratings
| VALUE | UNIT | |
|---|---|---|
| Electrostatic discharge (Human Body Model, per ANSI/ESDA/JEDEC JS-001) | ±1000 | V |
| Electrostatic discharge (Charged-device model (CDM), per JEDEC specification JESD22-101) | ±250 | V |
7.3 Recommended Operating Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | 1.8 | 5.5 | V |
| Temperature | -40 | 105 | °C |
7.4 Thermal Information
| THERMAL METRIC | TPL5010 DDC (SOT-23) 6 PINS | UNIT |
|---|---|---|
| Junction-to-ambient thermal resistance (RθJA) | 163 | °C/W |
| Junction-to-case (top) thermal resistance (RθJC(top)) | 26 | °C/W |
| Junction-to-board thermal resistance (RθJB) | 57 | °C/W |
| Junction-to-top characterization parameter (ΨJT) | 7.5 | °C/W |
| Junction-to-board characterization parameter (ΨJB) | 57 | °C/W |
| Junction-to-case (bottom) thermal resistance (RθJC(bot)) | N/A | °C/W |
7.5 Electrical Characteristics
Specifications are for TA = 25°C, VDD-GND = 2.5 V, unless otherwise stated.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| POWER SUPPLY | |||||
| Supply current (IDD)4 | Operation mode | 35 | 50 | nA | |
| Digital conversion of external resistance (Rext) | 200 | 400 | µA | ||
| TIMER | |||||
| Time Interval Period (tIP) | 1650 selectable Time Intervals | Minimum time interval: 100 | Maximum time interval: 7200 | ms / s | |
| Time Interval Setting Accuracy5 | Excluding the precision of Rext | ±0.6% | |||
| Timer Interval Setting Accuracy over supply voltage | 1.8 V ≤ VDD ≤ 5.5 V | ±25 ppm/V | |||
| Oscillator Accuracy (tOSC) | -0.5% | 0.5% | |||
| Oscillator Accuracy over temperature6 | -40°C ≤ TA ≤ 105°C | ±100 | ±400 | ppm/°C | |
| Oscillator Accuracy over supply voltage | 1.8 V ≤ VDD ≤ 5.5 V | ±0.4 %/V | |||
| Oscillator Accuracy over life time7 | 0.24% | ||||
| DONE Pulse width (tDONE)6 | 100 | ns | |||
| RSTn Pulse width (tRSTn) | 320 | ms | |||
| WAKE Pulse width (tWAKE) | 20 | ms | |||
| Time to convert Rext (t_Rext) | 100 | 120 | ms | ||
| DIGITAL LOGIC LEVELS | |||||
| Logic High Threshold DONE pin (VIH) | 0.7 × VDD | V | |||
| Logic Low Threshold DONE pin (VIL) | 0.3 x VDD | V | |||
| Logic output High Level WAKE pin (VOH) | Iout = 100 µA | VDD - 0.3 | V | ||
| Iout = 1 mA | VDD - 0.7 | V | |||
| Logic output Low Level WAKE pin (VOL) | Iout = -100 µA | 0.3 | V | ||
| Iout = -1 mA | 0.7 | V | |||
| RSTn Logic output Low Level (VOLRSTn) | IOL = -1 mA | 0.3 | V | ||
| RSTn High Level output current (IOHRSTn) | VOHRSTn = VDD | 1 | nA | ||
| Logic High Threshold DELAY/M_RST pin (VIHM_RST) | 1.5 | V | |||
7.6 Timing Requirements
| MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|
| Rise Time RSTn (tRSTn)3 | 11 | µs | ||
| Fall Time RSTn (tfRSTn)3 | 50 | ns | ||
| Rise Time WAKE (trWAKE)3 | 50 | ns | ||
| Fall Time WAKE (tfWAKE)3 | 50 | ns | ||
| DONE to RSTn or WAKE to DONE delay (tDDONE) | Minimum delay4: 100 | ns | ||
| Maximum delay4: tIP | 20 | ms | ||
| Valid Manual Reset (tM_RST) | Observation time: 30 | 20 | ms | |
| De-bounce Manual Reset (tDB) | 20 | ms |
Figure 1. TPL5010 Timing: This diagram illustrates the timing relationships between the WAKE, DONE, RSTn, and DELAY/M_RST signals. It shows the WAKE pulse, the expected DONE signal, the resulting RSTn signal when DONE is missed, and the effect of a manual reset pulse on DELAY/M_RST.
7.7 Typical Characteristics
Figure 2. IDD vs. VDD: A graph plotting Supply Current (nA) on the Y-axis against Supply Voltage (V) on the X-axis, showing curves for different temperatures (-40°C, 25°C, 70°C, 105°C).
Figure 3. IDD vs. Temperature: A graph plotting Supply Current (nA) on the Y-axis against Temperature (°C) on the X-axis, showing curves for different supply voltages (1.8V, 2.5V, 3.3V, 5.5V).
Figure 4. Oscillator Accuracy vs. VDD: A graph plotting Oscillator Accuracy (%) on the Y-axis against Supply Voltage (V) on the X-axis, showing curves for different temperatures (-40°C, 25°C, 70°C, 105°C).
Figure 5. Oscillator Accuracy vs. Temperature: A graph plotting Oscillator Accuracy (%) on the Y-axis against Temperature (°C) on the X-axis, showing curves for different supply voltages (1.8V, 2.5V, 3.3V, 5.5V).
Figure 6. IDD vs. Time: A graph plotting Supply Current (µA) on the Y-axis against Time (s) on the X-axis, showing the current consumption over time during timer operation.
Figure 7. Time Interval Setting Accuracy: A histogram showing the frequency of accuracy percentages for time intervals between 1s and 7200s.
8 Detailed Description
8.1 Overview
The TPL5010 is a system wake-up timer with a watchdog feature designed for low-power applications. The TPL5010 can be used in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.
8.2 Functional Block Diagram
Functional Block Diagram: A block diagram illustrates the internal components of the TPL5010. It shows a LOW FREQUENCY OSCILLATOR feeding a FREQUENCY DIVIDER, which is controlled by LOGIC CONTROL. A DECODER & MANUAL RESET DETECTOR receives input from DELAY/M_RST and outputs to the LOGIC CONTROL. The LOGIC CONTROL generates the RSTn and WAKE signals, and receives input from DONE. GND is also shown.
8.3 Feature Description
The DONE, WAKE, and RSTn signals are used to implement the watchdog function. The TPL5010 is programmed to issue a periodic WAKE pulse to a µC which is in sleep or standby mode. After receiving the WAKE pulse, the µC must issue a DONE signal to the TPL5010 at least 20 ms before the rising edge of the next WAKE pulse. If the DONE signal is not asserted, the TPL5010 asserts the RSTn signal to reset the µC. A manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD.
Figure 8. Watchdog: This timing diagram shows the sequence of WAKE, DONE, and RSTn signals. It illustrates a scenario where a WAKE pulse is issued, followed by a DONE signal. If the DONE signal is missed ('MISSED DONE'), the RSTn signal is asserted after a delay related to the time interval (tIP) and reset pulse width (tRSTn).
8.3.1 WAKE
The WAKE pulse is sent out from the TPL5010 when the programmed time interval starts (except at the beginning of the first cycle or if in the previous interval the DONE has not been received). This signal is normally low.
8.3.2 DONE
The DONE pin is driven by a µC to signal successful processing of the WAKE signal. The TPL5010 recognizes a valid DONE signal as a low to high transition. If two or more DONE signals are received within the time interval, only the first DONE signal is processed. The DONE signal resets the counter of the watchdog only. If the DONE signal is received when the WAKE is still high, the WAKE will go low as soon as the DONE is recognized.
8.3.3 RSTn
To implement the reset interface between the TPL5010 and the µC, a pullup resistance is required. 100 kΩ is recommended to minimize current. During the POR and the reading of the REXT, the RSTn signal is LOW. RSTn is asserted (LOW) for either of the following conditions: 1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately 20 ms). 2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising edge.
8.4 Device Functional Modes
8.4.1 Start-Up
During start-up after POR, the TPL5010 executes a one-time measurement of the resistance attached to the DELAY/M_RST pin to determine the desired time interval for WAKE. This measurement interval is tR_EXT. During this measurement, a constant current is temporarily flowing into REXT.
Figure 9. Start-Up: This timing diagram shows the start-up sequence. It depicts the POR event, followed by RESISTANCE READING (tR_EXT), then the assertion of the RSTn signal, and finally the first WAKE pulse after a time interval (tIP).
8.4.2 Normal Operating Mode
During normal operating mode, the TPL5010 asserts periodic WAKE pulses in response to valid DONE pulses from the µC. If either a manual reset is applied (logic HIGH on DELAY/M_RST pin), or the µC does not issue a DONE pulse within the required time, the TPL5010 asserts the RSTn signal to the µC and restarts its internal counters.
8.5 Programming
8.5.1 Configuring the WAKE Interval With the DELAY/M_RST Pin
The time interval between two adjacent WAKE pulses (rising edges) is selectable through an external resistance (REXT) between the DELAY/M_RST pin and ground. The value of the resistance REXT is converted one time after POR. The allowable range of REXT is 500 Ω to 170 kΩ. At least a 1% precision resistance is recommended. The time between two adjacent RESET signals (falling edges), or between a RESET (falling edge) and a WAKE (rising edge), is given by the sum of the programmed time interval and the tRSTn (reset pulse width).
8.5.2 Manual Reset
If VDD is connected to the DELAY/M_RST pin, the TPL5010 recognizes this as a manual reset condition. In this case, the time interval is not set. If the manual reset is asserted during the POR or during the reading procedure, the reading procedure is aborted and is restarted as soon as the manual reset switch is released. A pulse on the DELAY/M_RST pin is recognized as a valid manual reset only if it lasts at least 20 ms (observation time is 30 ms).
A valid manual reset resets all the counters inside the TPL5010. The counters restart only when the high digital voltage at DELAY/M_RST is removed and the next tRSTn is elapsed.
Figure 10. Manual Reset: This timing diagram illustrates the manual reset function. It shows a VALID M_RST pulse on DELAY/M_RST, which results in the RSTn signal being asserted LOW for a duration determined by tM_RST, tDB, and tRSTn. It also shows a NOT VALID M_RST condition.
8.5.2.1 DELAY/M_RST
A resistance in the range between 500 Ω and 170 kΩ needs to be connected to select a valid time interval. At the POR and during the reading of the resistance, the DELAY/M_RST is connected to an analog signal chain through a mux. After reading the resistance, the analog circuit is switched off, and the DELAY/RST is connected to a digital circuit. The manual reset detection is supported with a de-bounce feature, making the TPL5010 insensitive to glitches on the DELAY/M_RST pin. When a valid manual reset signal is asserted on the DELAY/M_RST pin, the RSTn signal is asserted LOW after a delay of tM_RST. It remains LOW after a valid manual reset is asserted + tDB + tRSTn. Due to the asynchronous nature of the manual reset signal and its arbitrary duration, the LOW status of the RSTn signal may be affected by an uncertainty of about ±5 ms.
A valid manual reset puts all the digital output signals at their default values: WAKE = LOW, RSTn = asserted LOW.
8.5.2.2 Circuitry
The manual reset may be implemented using a switch (momentary mechanical action). The TPL5010 offers two possible approaches according to the power consumption constraints of the application.
Figure 11. Manual Reset With SPST Switch: A schematic shows a single-pole single-throw (SPST) switch connected between the DELAY/M_RST pin and VDD, with REXT connected between DELAY/M_RST and GND. This configuration is suitable for use cases not requiring the lowest power consumption.
Figure 12. Manual Reset With SPDT Switch: A schematic shows a single-pole double-throw (SPDT) switch used to connect DELAY/M_RST from REXT to VDD. This provides a lower power solution for manual reset as no current flows when the switch is in the VDD position.
8.5.3 Timer Interval Selection Using External Resistance
To set the time interval, the external resistance REXT is selected according to Equation 1:
REXT = [ -b + √(b² - 4a(c - 100T)) ] / 2a
where:
- T is the desired time interval in seconds.
- REXT is the resistance value to use in Ω.
- a, b, and c are coefficients depending on the range of the time interval.
| SET | Time interval Range (s) | a | b | c |
|---|---|---|---|---|
| 1 | 1 < T ≤ 5 | 0.2253 | -20.7654 | 570.5679 |
| 2 | 5 < T ≤ 10 | -0.1284 | 46.9861 | -2651.8889 |
| 3 | 10 ≤ T ≤ 100 | 0.1972 | -19.3450 | 692.1201 |
| 4 | 100 < T ≤ 1000 | 0.2617 | -56.2407 | 5957.7934 |
| 5 | T > 1000 | 0.3177 | -136.2571 | 34522.4680 |
EXAMPLE: Required time interval: 8 s. The coefficient set to be selected is number 2. The formula becomes:
REXT = [ -46.9861 + √(46.9861² - 4*0.1284*(-2561.8889 – 100*8)) ] / (2*0.1284)
The resistance value is 10.18 kΩ.
Tables 2 and 3 contain example values of tIP and their corresponding value of REXT.
| tIP (ms) | Resistance (Ω) | Closest Real Value (Ω) | Parallel of Two 1% Tolerance Resistors, (kΩ) |
|---|---|---|---|
| 100 | 500 | 500 | 1.0 // 1.0 |
| 200 | 1000 | 1000 | 2.43 // 3.92 |
| 300 | 1500 | 1500 | 4.42 // 5.76 |
| 400 | 2000 | 2000 | 5.36 // 6.81 |
| 500 | 2500 | 2500 | 4.75 // 13.5 |
| 600 | 3000 | 3000 | 6.19 // 11.3 |
| 700 | 3500 | 3500 | 6.19 // 16.5 |
| 800 | 4000 | 4000 | |
| 900 | 4500 | 4501 |
| tIP | Calculated Resistance (kΩ) | Closest Real Value (kΩ) | Parallel of Two 1% Tolerance Resistors, (kΩ) |
|---|---|---|---|
| 1s | 5.20 | 5.202 | 7.15 // 19.1 |
| 2s | 6.79 | 6.788 | 12.4 // 15.0 |
| 3s | 7.64 | 7.628 | 12.7// 19.1 |
| 4s | 8.30 | 8.306 | 14.7 // 19.1 |
| 5s | 8.85 | 8.852 | 16.5 // 19.1 |
| 6s | 9.27 | 9.223 | 18.2 // 18.7 |
| 7s | 9.71 | 9.673 | 19.1 // 19.6 |
| 8s | 10.18 | 10.180 | 11.5 // 8.87 |
| 9s | 10.68 | 10.68 | 17.8 // 26.7 |
| 10s | 11.20 | 11.199 | 15.0 // 44.2 |
| 20s | 14.41 | 14.405 | 16.9 // 97.6 |
| 30s | 16.78 | 16.778 | 32.4 // 34.8 |
| 40s | 18.75 | 18.748 | 22.6 // 110.0 |
| 50s | 20.047 | 20.047 | 28.7 // 66.5 |
| 1min | 22.02 | 22.021 | 40.2 // 48.7 |
| 2min | 29.35 | 29.349 | 35.7 // 165.0 |
| 3min | 34.73 | 34.729 | 63.4 // 76.8 |
| 4min | 39.11 | 39.097 | 63.4 // 102.0 |
| 5min | 42.90 | 42.887 | 54.9 // 196.0 |
| 6min | 46.29 | 46.301 | 75.0 // 121.0 |
| 7min | 49.38 | 49.392 | 97.6 // 100.0 |
| 8min | 52.24 | 52.224 | 88.7 // 127.0 |
| 9min | 54.92 | 54.902 | 86.6 // 150.0 |
| 10min | 57.44 | 57.437 | 107.0 // 124.0 |
| 20min | 77.57 | 77.579 | 140.0 // 174.0 |
| 30min | 92.43 | 92.233 | 182.0 // 187.0 |
| 40min | 104.67 | 104.625 | 130.0 // 536.00 |
| 50min | 115.33 | 115.331 | 150.0 // 499.00 |
| 1h | 124.91 | 124.856 | 221.0 // 287.00 |
| 1h30min | 149.39 | 149.398 | 165.0 // 1580.0 |
| 2h | 170.00 | 170.00 | 340.0 // 340.0 |
8.5.4 Quantization Error
The TPL5010 can generate 1650 discrete timer intervals in the range of 100 ms to 7200 s. The first 9 intervals are multiples of 100 ms. The remaining 1641 intervals cover the range between 1 s to 7200 s. Because they are discrete intervals, there is a quantization error associated with each value.
The quantization error can be evaluated according to Equation 3:
Err = 100 × (TDESIRED - TADC) / TDESIRED
where:
TADC = INT [ 1 / (100 × (aRD² + bRD + c)) ]
RD = REXT / 100
REXT is the resistance calculated with Equation 1, and a, b, c are the coefficients listed in Table 1.
8.5.5 Error Due to Real External Resistance
REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to closely approach the theoretical REXT using two or more standard values in parallel. However, standard values are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.
The accuracy can be evaluated using the following procedure:
- Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial resistance values and their tolerances.
- Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with the TADC equation mentioned in Equation 3.
- Find the errors using Equation 3 with TADC_MIN, TADC_MAX. The results of the formula indicate the accuracy of the time interval.
The example below illustrates the procedure:
- Desired time interval, Tdesired = 600 s.
- Required REXT from Equation 1, REXT = 57.44 kΩ.
From Table 3, REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1 = 107 kΩ, R2 = 124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 4:
uR// = √( (uR1/R1)² + (uR2/R2)² ) × R//
where:
uRn (n=1,2) represents the uncertainty of a resistance (see Equation 5).
Equation 5: uRn = Tolerance / √3
The uncertainty of the parallel resistance is 0.82%, which means the value of REXT may range between REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ. Using these values of REXT, the digitized timer intervals calculated by the TADC equation mentioned in Equation 3 are respectively TADC_MIN = 586.85 s and TADC_MAX = 611.3 s, giving an error range of -1.88% / +2.19%. The asymmetry of the error range is due to the quadratic transfer function of the resistance digitizer.
9 Application and Implementation
NOTE: Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
In battery-powered applications, one design constraint is the need for low current consumption. The TPL5010 is designed for applications where there is a need to monitor environmental conditions at a fixed time interval. Often in these applications, a watchdog or other internal timer in a µC is used to implement a wake-up function. Using the TPL5010 to implement the watchdog function will consume only tens of nA, significantly improving the power consumption of the system.
9.2 Typical Application
The TPL5010 can be used in conjunction with environment sensors to build a low-power environment data logger, such as an air quality data-logger. In this application, due to the monitored phenomena, the µC and the front end of the sensor spend most of the time in the idle state, waiting for the next logging interval, usually a few hundred milliseconds. Figure 13 shows a data logging application based on a µC and a front end for a gas sensor based on the LMP91000.
Figure 13. Data-Logger: This block diagram shows a typical application setup for a data logger. It includes a Lithium-ion battery, a POWER MANAGEMENT block, the TPL5010 timer, a microcontroller (µC), and a gas sensor (LMP91000). The diagram illustrates the interconnections and signal paths, including VDD, GND, RSTn, WAKE, DONE, SCL, SDA, and connections to sensors and displays.
9.2.1 Design Requirements
The design is driven by the low-current consumption constraint. The data are usually acquired on a rate that ranges between 1 s and 10 s. The highest necessity is the maximization of the battery life. The TPL5010 helps achieve that goal because it allows putting the µC in its lowest power mode. The TPL5010 will take care of the watchdog and the timing.
Figure 14. Effect of TPL5010 on Current Consumption: This line graph compares current consumption over time. The 'Without TPL5010' line shows higher, continuous current usage. The 'With TPL5010' line shows significantly lower baseline current with periodic, short spikes, demonstrating power savings.
10 Power Supply Recommendations
The TPL5010 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of 0.1 µF between VDD and GND pin is recommended.
11 Layout
11.1 Layout Guidelines
The DELAY/M_RST pin is sensitive to parasitic capacitance. TI suggests that the traces connecting the resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This capacitance can affect the initial set up of the time interval. Signal integrity on the WAKE and RSTn pins is also improved by keeping the trace length between the TPL5010 and the µC short to reduce the parasitic capacitance.
Figure 15. Layout: This diagram illustrates recommended PCB layout practices. It shows the placement of the TPL5010, a manual reset switch, bypass capacitor (C1), pull-up resistor (RP), and external resistor (R_EXT), along with trace routing to minimize parasitic capacitance.
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
- TI E2E™ Online Community: Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
- Design Support: Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 - TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Packaging Information: Details various orderable part numbers, their status, material type, package (SOT-23 THIN), pin count, carrier type, RoHS compliance, lead finish, MSL rating, operating temperature, and part marking.
Tape and Reel Information: Describes reel dimensions, tape dimensions (A0, B0, K0, P1, W), and quadrant assignments for pin 1 orientation. It also details tape and reel box dimensions.
Package Outline (DDC0006A): Provides detailed mechanical drawings of the SOT-23 package, including dimensions, pin numbering, and features like seating plane and gage plane.
Example Board Layout and Stencil Design: Illustrates recommended PCB land patterns and solder paste stencil apertures for the SOT-23 package.
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