TPL5010 Nano-power System Timer with Watchdog Function
Texas Instruments
1 Features
- Supply Voltage from 1.8V to 5.5V
- Current Consumption at 2.5V: 35nA (typ)
- Selectable Time Intervals: 100ms to 7200s
- Timer Accuracy: 1% (typ)
- Resistor Selectable Time Interval
- Watchdog Functionality
- Manual Reset
2 Applications
- Battery Powered Systems
- Internet of Things (IoT)
- Intruder Detection
- Tamper Detection
- Home Automation Sensors
- Thermostats
- Consumer Electronics
- Remote Sensors
- White Goods
3 Description
The TPL5010 Nano Timer is a low-power timer with a watchdog feature, ideal for system wake-up in duty-cycled or battery-powered applications. In such systems, the µC timer can be used for system wake-up, but if the timer sleep current is high, up to 60-80% of the total system current can be consumed by the µC timer in this sleep mode. Consuming only 35nA, the TPL5010 can replace the functionality of the integrated µC timer and allow the µC to be placed in a much lower power mode. Such power savings enable the use of significantly smaller batteries, making it well-suited for energy harvesting or wireless sensor applications. The TPL5010 provides selectable timing intervals from 100ms to 7200s and is designed for interrupt-driven applications. Some standards (such as EN50271) require implementation of a watchdog for safety, and the TPL5010 realizes this watchdog function at almost no additional power consumption. The TPL5010 is available in a 6-pin SOT23 package.
Device Information
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPL5010 | SOT23 (6) | 3.00 mm x 3.00 mm |
(1) For all available packages, see the orderable addendum at the end of the datasheet.
4 Simplified Application Schematic
The schematic shows a typical setup for the TPL5010. A battery provides power through a POWER MANAGEMENT block to VOUT and VIN. The TPL5010 is connected to GND and VDD. Its DELAY/M_RST pin is connected to an external resistor (REXT) to GND, which sets the timing interval. The RSTn pin is connected to the µC's RST input, with a pull-up resistor (Rp). The WAKE pin is connected to the µC's input for wake-up signals, and the DONE pin is connected to a µC GPIO for watchdog acknowledgment.
5 Revision History
| DATE | REVISION | NOTES |
|---|---|---|
| January 2015 | * | Initial release. |
6 Pin Configuration and Functions
6-Lead SOT23 Top View
The TPL5010 is housed in a 6-lead SOT23 package. The pins are arranged as follows:
- Pin 1: VDD (Power Supply)
- Pin 2: GND (Ground)
- Pin 3: DELAY/M_RST (Time Interval set and Manual Reset)
- Pin 4: DONE (Logic Input for watchdog functionality)
- Pin 5: WAKE (Timer output signal)
- Pin 6: RSTn (Reset Output)
Pin Functions Table
| PIN NO. | NAME | TYPE(1) | DESCRIPTION | APPLICATION INFORMATION |
|---|---|---|---|---|
| 1 | VDD | P | Supply voltage | |
| 2 | GND | G | Ground | |
| 3 | DELAY/ M_RST | I | Time Interval set and Manual Reset | Resistance between this pin and GND is used to select the time interval. The reset switch is also connected to this pin. |
| 4 | DONE | I | Logic Input for watchdog functionality | Digital signal driven by the µC to indicate successful processing of the WAKE signal. |
| 5 | WAKE | O | Timer output signal generated every tIP period. | Digital pulsed signal to wake up the µC at the end of the programmed time interval. |
| 6 | RSTn | O | Reset Output (open drain output) | Digital signal to RESET the µC, pull-up resistance is required |
(1) G= Ground, P= Power, O= Output, I= Input.
7 Specifications
7.1 Absolute Maximum Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | -0.3 | 6.0 | V |
| Input Voltage at any pin(2) | -0.3 | VDD + 0.3 | V |
| Input Current on any pin | -5 | +5 | mA |
| Storage Temperature, Tstg | -65 | 150 | °C |
| Junction Temperature, TJ(3) | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage between any two pins should not exceed 6V.
(3) The maximum power dissipation is a function of TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC board.
7.2 ESD Ratings
| V(ESD) Electrostatic discharge | VALUE | UNIT |
|---|---|---|
| Human Body Model, per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-101(2) | ±250 | V |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | 1.8 | 5.5 | V |
| Temperature Range | -40 | 105 | °C |
7.4 Thermal Information
| THERMAL METRIC(1) | TPL5010 SOT23 6 PINS | UNIT |
|---|---|---|
| Junction-to-ambient thermal resistance | 163 | °C/W |
| Junction-to-case (top) thermal resistance | 26 | |
| Junction-to-board thermal resistance | 57 | |
| Junction-to-top characterization parameter | 7.5 | |
| Junction-to-board characterization parameter | 57 | |
| Junction-to-case (bottom) thermal resistance | N/A |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
Specifications are for TA= 25°C, VDD-GND=2.5 V, unless otherwise stated.
| PARAMETER | TEST CONDITIONS | MIN (2) | TYP (3) | MAX (2) | UNIT |
|---|---|---|---|---|---|
| POWER SUPPLY | |||||
| Supply current(4) | Operation mode Digital conversion of external resistance (Rext) | 35 200 | 50 400 | nA µA | |
| TIMER | |||||
| Time Interval Period | 1650 selectable Time Intervals | Min time interval Max time interval | 100 7200 | ms s | |
| Time Interval Setting Accuracy(5) | Excluding the precision of Rext | ±0.6% | % | ||
| Timer Interval Setting Accuracy over supply voltage | 1.8V ≤ VDD ≤ 5.5V | ±25 | ppm/V | ||
| Oscillator Accuracy | -0.5% | 0.5% | % | ||
| Oscillator Accuracy over temperature(6) | -40°C ≤TA≤105°C | ±100 | +400 | ppm/°C | |
| Oscillator Accuracy over supply voltage | 1.8V ≤ VDD ≤ 5.5V | ±0.4 | %/V | ||
| Oscillator Accuracy over life time(7) | 0.24% | % | |||
| DONE Pulse width(6) | 100 | ns | |||
| RSTn Pulse width | 320 | ms | |||
| WAKE Pulse width | 20 | ms | |||
| Time to convert Rext | 100 | 120 | ms | ||
| DIGITAL LOGIC LEVELS | |||||
| Logic High Threshold DONE pin | 0.7xVDD | V | |||
| Logic Low Threshold DONE pin | 0.3xVDD | V | |||
| Logic output High Level WAKE pin | lout = 100 µA | VDD-0.3 | V | ||
| lout = 1 mA | VDD-0.7 | V | |||
| Logic output Low Level WAKE pin | lout = -100 µA | 0.3 | V | ||
| lout = -1 mA | 0.7 | V | |||
| RSTn Logic output Low Level | IOL= -1 mA | 0.3 | V | ||
| RSTn High Level output current | VOHRSTn=VDD | 1 | nA | ||
| Logic High Threshold DELAY/M_RST pin | 1.5 | V | |||
(1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD.
(5) The accuracy for time interval settings below 1second is ±100ms.
(6) This parameter is specified by design and/or characterization and is not tested in production.
(7) Operational life time test procedure equivalent to 10 years.
7.6 Timing Requirements
| Capacitive load 50 pF, Rpull-up 100kΩ | MIN (1) | NOM (2) | MAX (1) | UNIT | |
|---|---|---|---|---|---|
| trRSTn Rise Time RSTn (3) | 11 | µs | |||
| tfRSTn Fall Time RSTn (3) | 50 | ns | |||
| trWAKE Rise Time WAKE (3) | Capacitive load 50 pF | 50 | ns | ||
| tfWAKE Fall Time WAKE (3) | Capacitive load 50 pF | 50 | ns | ||
| tDDONE DONE to RSTn or WAKE to DONE delay | Min delay(4) Max delay (4) | 100 | ns | ||
| tM_RST Valid Manual Reset | Observation time 30ms | 20 | ms | ||
| tDB De-bounce Manual Reset | 20 | ms |
(1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(3) This parameter is specified by design and/or characterization and is not tested in production.
(4) In case of RSTn from its falling edge, in case of WAKE, from its rising edge.
Figure 1. TPL5010 Timing Diagram: This diagram illustrates the timing relationships between the WAKE, DONE, RSTn, and DELAY/M_RST signals. It shows the WAKE pulse initiating a timer interval, the expected DONE signal from the µC, and the RSTn signal being asserted if the DONE signal is missed or if a manual reset occurs. It also depicts the delays associated with these signals, such as tD_DONE, tM_RST, and tDB.
7.7 Typical Characteristics
Figure 2. IDD vs. VDD: This graph shows the typical supply current (IDD) in nanoamperes (nA) as a function of supply voltage (VDD) in volts (V) for different ambient temperatures (-40°C, 25°C, 70°C, 105°C). The current generally increases with supply voltage.
Figure 3. IDD vs. Temperature: This graph illustrates the typical supply current (IDD) in nanoamperes (nA) as a function of ambient temperature (°C) for different supply voltages (1.8V, 2.5V, 3.3V, 5.5V). The current tends to increase with temperature.
Figure 4. Oscillator Accuracy vs. VDD: This graph displays the typical oscillator accuracy in percentage (%) versus supply voltage (VDD) in volts (V) for various temperatures. The accuracy varies with both voltage and temperature.
Figure 5. Oscillator Accuracy vs. Temperature: This graph shows the typical oscillator accuracy in percentage (%) versus ambient temperature (°C) for different supply voltages. The accuracy exhibits fluctuations across the temperature range.
Figure 6. IDD vs. Time: This graph plots the typical supply current (IDD) in microamperes (µA) over time (seconds). It shows a higher current during the Power-On Reset (POR) and REXT reading phase, which then drops to a much lower, stable current during the Timer Mode.
Figure 7. Time Interval Setting Accuracy: This histogram displays the distribution of time interval setting accuracy in percentage (%) for time intervals between 1s and 7200s. It shows that the accuracy is tightly clustered around 0%.
8 Detailed Description
8.1 Overview
The TPL5010 is a system wake-up timer with a watchdog feature, ideal for low-power applications. It is suitable for interrupt-driven applications and provides selectable timing from 100ms to 7200s.
8.2 Functional Block Diagram
The functional block diagram shows the main components of the TPL5010: a LOW FREQUENCY OSCILLATOR, a FREQUENCY DIVIDER, LOGIC CONTROL, a DECODER & MANUAL RESET DETECTOR. These blocks interact to produce the RSTn, WAKE, and DONE output signals based on the DELAY/M_RST input and internal timing.
8.3 Feature Description
The DONE, WAKE, and RSTn signals are used to implement the watchdog function. The TPL5010 issues a periodic WAKE pulse to a µC in sleep or standby mode. After receiving the WAKE pulse, the µC must issue a DONE signal to the TPL5010 at least 20ms before the rising edge of the next WAKE pulse. If the DONE signal is not asserted, the TPL5010 asserts the RSTn signal to reset the µC. A manual reset function is achieved by momentarily pulling the DELAY/M_RST pin to VDD.
Figure 8. Watchdog Diagram: This timing diagram illustrates the watchdog operation. It shows the WAKE pulse, the expected DONE signal from the µC, and the RSTn signal. If the DONE signal is missed (MISSED DONE), the RSTn signal is asserted after a delay (tRSTn + tIP).
8.3.1 WAKE
The WAKE pulse is sent out from the TPL5010 when the programmed time interval starts, except for the first cycle or if the DONE signal was not received in the previous interval. This signal is normally low.
8.3.2 DONE
The DONE pin is driven by a µC to signal successful processing of the WAKE signal. The TPL5010 recognizes a valid DONE signal as a low-to-high transition. If multiple DONE signals are received within the time interval, only the first one is processed. The DONE signal resets the watchdog counter. If DONE is received while WAKE is still high, WAKE will go low immediately after DONE is recognized.
8.3.3 RSTn
A pull-up resistance (100kΩ recommended) is required for the reset interface between the TPL5010 and the µC. During POR and REXT reading, the RSTn signal is LOW. RSTn is asserted (LOW) under two conditions: 1. If the DELAY/M_RST pin is high for at least two consecutive internal oscillator cycles (approx. 20ms). 2. At the start of a new time interval if DONE is not received at least 20ms before the next WAKE rising edge.
8.4 Device Functional Modes
8.4.1 Startup
During startup, after POR, the TPL5010 measures the resistance connected to the DELAY/M_RST pin to determine the desired WAKE time interval. This measurement takes tR_EXT, during which a constant current flows into REXT.
Figure 9. Startup Diagram: This diagram shows the startup sequence, including POR, the resistance reading phase (tR_EXT), and the subsequent RSTn and WAKE signals.
8.4.2 Normal Operating Mode
In normal operation, the TPL5010 asserts periodic WAKE pulses in response to valid DONE pulses from the µC. If a manual reset is applied (DELAY/M_RST pin HIGH) or if the µC fails to issue a DONE pulse within the required time, the TPL5010 asserts the RSTn signal to the µC and restarts its internal counters.
8.5 Programming
8.5.1 Configuring the WAKE Interval with the DELAY/M_RST Pin
The time interval between adjacent WAKE pulses is set by an external resistance (REXT) connected between the DELAY/M_RST pin and ground. REXT is converted once after POR. The allowable range for REXT is 500Ω to 170kΩ. A 1% precision resistor is recommended. The time between RESET signals or between a RESET and WAKE is the programmed time interval plus the tRSTn pulse width.
8.5.2 Manual Reset
Connecting VDD to the DELAY/M_RST pin triggers a manual reset. In this state, the time interval is not set. If manual reset occurs during POR or reading, the procedure aborts and restarts upon release. A valid manual reset pulse must last at least 20ms (observation time is 30ms). A valid manual reset clears all counters, and they restart only after the HIGH digital voltage on DELAY/M_RST is removed and tRSTn elapses.
Figure 10. Manual Reset Diagram: This timing diagram shows the effect of a VALID M_RST pulse on the DELAY/M_RST, RSTn, WAKE, and DONE signals, illustrating the reset sequence and its duration.
8.5.2.1 DELAY/M_RST
A resistance between 500Ω and 170kΩ is required to select a time interval. The DELAY/M_RST pin connects to an analog signal chain during POR and resistance reading, then switches to a digital circuit. Manual reset detection includes a de-bounce feature. When a valid manual reset is asserted, RSTn goes LOW after tM_RST and stays LOW for tM_RST + tDB + tRSTn. The LOW status of RSTn may have an uncertainty of about ±5ms. A valid manual reset sets WAKE to LOW and RSTn to asserted LOW.
8.5.2.2 Circuitry
Manual reset can be implemented with a momentary switch. Two approaches are offered based on power consumption constraints.
Figure 11. Manual Reset with SPST Switch Schematic: This circuit shows a single-pole single-throw (SPST) switch connecting DELAY/M_RST directly to VDD for manual reset. REXT is in series. Current drawn during reset is VDD/REXT.
Figure 12. Manual Reset with SPDT Switch Schematic: This circuit uses a single-pole double-throw (SPDT) switch to connect DELAY/M_RST between REXT and VDD. This provides a lower power manual reset solution as no current flows when switching to VDD.
8.5.3 Timer Interval Selection Using External Resistance
The time interval (T) is set using an external resistance (REXT) according to the following formula:
R_EXT = 100 * (-b + sqrt(b^2 - 4*a*(c - 100*T))) / (2*a) (Equation 1)
Where:
- T is the desired time interval in seconds.
- REXT is the resistance value in Ω.
- a, b, c are coefficients depending on the time interval range.
| SET | Time interval Range (s) | a | b | c |
|---|---|---|---|---|
| 1 | 1 <T≤ 5 | 0.2253 | -20.7654 | 570.5679 |
| 2 | 5 <T≤ 10 | -0.1284 | 46.9861 | -2651.8889 |
| 3 | 10 <T≤ 100 | 0.1972 | -19.3450 | 692.1201 |
| 4 | 100 <T≤ 1000 | 0.2617 | -56.2407 | 5957.7934 |
| 5 | T> 1000 | 0.3177 | -136.2571 | 34522.4680 |
Example: For a required time interval of 8s, SET 2 is selected. The formula becomes:
R_EXT = 100 * (-46.9861 + sqrt(46.9861^2 - 4*0.1284*(-2561.8889 - 100*8))) / (2*0.1284) (Equation 2)
The resistance value is 10.18 kΩ.
The following tables provide example values of tIP and their corresponding REXT values.
| tIP (ms) | Resistance (Ω) | Closest Real Value (Ω) | Parallel of Two 1% Tolerance Resistors, (kΩ) |
|---|---|---|---|
| 100 | 500 | 500 | 1.0 // 1.0 |
| 200 | 1000 | 1000 | |
| 300 | 1500 | 1500 | 2.43 // 3.92 |
| 400 | 2000 | 2000 | |
| 500 | 2500 | 2500 | 4.42 // 5.76 |
| 600 | 3000 | 3000 | 5.36 // 6.81 |
| 700 | 3500 | 3500 | 4.75 // 13.5 |
| 800 | 4000 | 4000 | 6.19 // 11.3 |
| 900 | 4500 | 4501 | 6.19 // 16.5 |
| tIP | Calculated Resistance (kΩ) | Closest Real Value (kΩ) | Parallel of Two 1% Tolerance Resistors, (kΩ) |
|---|---|---|---|
| 1s | 5.20 | 5.202 | 7.15 // 19.1 |
| 2s | 6.79 | 6.788 | 12.4 // 15.0 |
| 3s | 7.64 | 7.628 | 12.7// 19.1 |
| 4s | 8.30 | 8.306 | 14.7 // 19.1 |
| 5s | 8.85 | 8.852 | 16.5 // 19.1 |
| 6s | 9.27 | 9.223 | 18.2 // 18.7 |
| 7s | 9.71 | 9.673 | 19.1// 19.6 |
| 8s | 10.18 | 10.180 | 11.5 // 8.87 |
| 9s | 10.68 | 10.68 | 17.8 // 26.7 |
| 10s | 11.20 | 11.199 | 15.0 // 44.2 |
| 20s | 14.41 | 14.405 | 16.9 // 97.6 |
| 30s | 16.78 | 16.778 | 32.4 // 34.8 |
| 40s | 18.75 | 18.748 | 22.6 // 110.0 |
| 50s | 20.047 | 20.047 | 28.7 // 66.5 |
| tIP | Calculated Resistance (kΩ) | Closest Real Value (kΩ) | Parallel of Two 1% Tolerance Resistors, (kΩ) |
|---|---|---|---|
| 1min | 22.02 | 22.021 | 40.2 // 48.7 |
| 2min | 29.35 | 29.349 | 35.7 // 165.0 |
| 3min | 34.73 | 34.729 | 63.4 // 76.8 |
| 4min | 39.11 | 39.097 | 63.4 // 102.0 |
| 5min | 42.90 | 42.887 | 54.9 // 196.0 |
| 6min | 46.29 | 46.301 | 75.0 // 121.0 |
| 7min | 49.38 | 49.392 | 97.6 // 100.0 |
| 8min | 52.24 | 52.224 | 88.7 // 127.0 |
| 9min | 54.92 | 54.902 | 86.6 // 150.0 |
| 10min | 57.44 | 57.437 | 107.0 // 124.0 |
| 20min | 77.57 | 77.579 | 140.0 // 174.0 |
| 30min | 92.43 | 92.233 | 182.0 // 187.0 |
| 40min | 104.67 | 104.625 | 130.0 // 536.00 |
| 50min | 115.33 | 115.331 | 150.0 // 499.00 |
| 1h | 124.91 | 124.856 | 221.0 // 287.00 |
| 1h30min | 149.39 | 149.398 | 165.0 // 1580.0 |
| 2h | 170.00 | 170.00 | 340.0 // 340.0 |
8.5.4 Quantization Error
The TPL5010 generates 1650 discrete timer intervals from 100ms to 7200s. The first 9 intervals are multiples of 100ms, while the remaining 1641 cover 1s to 7200s. Discrete intervals introduce quantization error.
The quantization error is calculated as:
Err = 100 * (T_DESIRED - T_ADC) / T_DESIRED (Equation 3)
Where:
T_ADC = INT( (1/100) * (a * (R_D^2 / 100^2) + b * (R_D / 100) + c) ) (Equation 4)
R_D = INT( R_EXT / 100 ) (Equation 5)
REXT is calculated using Equation 1, and a,b,c are coefficients from Table 1.
8.5.5 Error Due to Real External Resistance
REXT is a theoretical value and may not match standard commercial resistor values. Approximating REXT with parallel standard values introduces tolerance errors. The accuracy can be evaluated by:
- Determining min/max REXT values (REXT_MIN, REXT_MAX) using Equation 1 and commercial resistor tolerances.
- Calculating time intervals (TADC_MIN, TADC_MAX) using Equation 4 with REXT_MIN and REXT_MAX.
- Finding errors using Equation 3 with TADC_MIN and TADC_MAX.
Example: Desired time interval T_desired = 600s. Required REXT = 57.44kΩ. Using parallel 1% tolerance resistors (R1=107kΩ, R2=124kΩ), the equivalent REXT uncertainty is 0.82%, leading to REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ. This results in TADC_MIN = 586.85s and TADC_MAX = 611.3s, yielding an error range of -1.88% / +2.19% due to the digitizer's quadratic transfer function.
9 Application and Implementation
NOTE: Information in this section is not part of the TI component specification and is provided for application guidance only. TI customers are responsible for validating suitability and design implementation.
9.1 Application Information
For battery-powered applications, low current consumption is critical. The TPL5010 is ideal for monitoring environmental conditions at fixed intervals. It replaces µC timers, consuming only tens of nA, significantly improving power efficiency.
9.2 Typical Application
The TPL5010 can be used in low-power environment data-loggers, such as air quality loggers. In these applications, the µC and sensor spend most time in an idle state, waiting for the next logging interval. Figure 13 shows a data logging application using a µC and a gas sensor (LMP91000).
Figure 13. Data-logger Schematic: This schematic depicts a system powered by a Lithium-ion battery. It includes the TPL5010, a microcontroller (µC), and a gas sensor (LMP91000). The TPL5010 manages timing and wake-up. The µC interfaces with the sensor, display, and keyboard. REXT sets the timing interval for the TPL5010.
9.2.1 Design Requirements
The primary design driver is low current consumption to maximize battery life. Data acquisition rates typically range from 1s to 10s. The TPL5010 enables the µC to operate in its lowest power mode, handling watchdog and timing functions.
Figure 14. Effect of TPL5010 on Current Consumption Graph: This graph compares current consumption over time for a system with and without the TPL5010. The line 'Without TPL5010' shows higher current peaks during wake-up cycles. The line 'With TPL5010' shows significantly reduced current consumption, demonstrating the power-saving benefit of using the TPL5010 for efficient wake-up and sleep management.
10 Power Supply Recommendations
The TPL5010 requires a voltage supply between 1.8V and 5.5V. A 0.1µF X7R multilayer ceramic bypass capacitor between VDD and GND is recommended.
11 Layout
11.1 Layout Guidelines
The DELAY/M_RST pin is sensitive to parasitic capacitance. Traces connecting REXT to GND should be kept short to minimize capacitance, which can affect time interval setup. Signal integrity on WAKE and RSTn is improved by keeping traces to the µC short.
Figure 15. Layout Example: This diagram shows an example PCB layout. It illustrates the placement of the TPL5010, a manual reset switch, R_EXT, RP (pull-up resistor), and their connections to the µC. Ground planes and short trace lengths are emphasized.
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. To prevent electrostatic damage, short the leads together or place the device in conductive foam during storage or handling.
12.3 Glossary
Refer to SLYZ022 -- TI Glossary for terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages provide mechanical, packaging, and orderable information. This data is subject to change. For browser-based versions, refer to the left-hand navigation.
Packaging Information: The TPL5010 is available in a 6-lead SOT23 package (DDC drawing). Orderable devices include TPL5010DDCR (3000 units/reel) and TPL5010DDCT (250 units/reel). These are Green (RoHS & no Sb/Br) compliant. Lead/Ball Finish is CU NIPDAU, with MSL Level-1 at 260°C peak temperature, and an operating temperature range of -40°C to 105°C. Device marking is ZAKX.
Tape and Reel Information: Details dimensions for tape reels and tape itself, including A0, B0, K0, P1, and W dimensions for the SOT23 DDC package. Pin 1 quadrant is Q3.
Tape and Reel Box Dimensions: Specifies the length, width, and height of the shipping boxes for the TPL5010DDCR and TPL5010DDCT.
Mechanical Data (DDC R-PDSO-G6): Provides detailed linear dimensions in millimeters for the 6-lead plastic small-outline package, including body dimensions, lead pitch, and seating plane specifications. Falls within JEDEC MO-193 variation AA.
Land Pattern Data (DDC R-PDSO-G6): Shows example board layout, stencil openings, and pad geometry for the DDC package, with dimensions in millimeters. Recommends IPC-7351 for alternate designs.
