1 Features
- Supply Voltage From 1.8 V to 5.5 V
- Current Consumption at 2.5 V and 35 nA (Typical)
- Selectable Time Intervals: 100 ms to 7200 s
- Timer Accuracy: 1% (Typical)
- Resistor Selectable Time Interval
- Watchdog Functionality
- Manual Reset
2 Applications
- Battery-Powered Systems
- Internet of Things (IoT)
- Intruder Detection
- Tamper Detection
- Home Automation Sensors
- Thermostats
- Consumer Electronics
- Remote Sensors
- White Goods
3 Description
The TPL5010 Nano Timer is an ultra-low power timer with a watchdog feature designed for system wake up in duty-cycled, battery-powered applications such as those in IoT. Many of these applications require the use of a µC, so it is desirable to keep the µC in a low power mode to maximize current savings, waking up only during certain time intervals to collect data or service an interrupt. Although the internal timer of the µC can be used for system wake-up, it can single-handedly consume microamps of total system current. Consuming only 35 nA, the TPL5010 can replace the functionality of the integrated µC timer. This allows the µC to be placed in a much lower power mode, with the internal timer off, returning only to active mode upon an interrupt by the TPL5010. By offering power savings of almost two orders of magnitude, the TPL5010 enables the use of significantly smaller batteries for energy harvesting or wireless sensor applications. The TPL5010 provides selectable timing intervals from 100 ms to 7200 s and is designed for interrupt-driven applications. Some standards (such as EN50271) require implementation of a watchdog for safety and the TPL5010 realizes this watchdog function at almost no additional power consumption. The TPL5010 is available in a 6-pin SOT23 package.
Device Information
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPL5010 | SOT23 (6) | 3.00 mm × 3.00 mm |
Simplified Application Schematic
A simplified schematic shows a battery connected to a POWER MANAGEMENT block. The TPL5010 is powered by VDD and GND from the POWER MANAGEMENT block. The TPL5010 has pins for DELAY/M_RST, DONE, WAKE, and RSTn. An external resistor REXT is connected between DELAY/M_RST and GND. The TPL5010's WAKE output is connected to a microcontroller's (µC) RSTn input. The TPL5010's RSTn output is connected to the µC's WAKE input. The TPL5010's DONE input is connected to a µC's GPIO. The µC also has VDD and GND connections, and an external resistor Rp is connected between the µC's RSTn and VDD.
4 Revision History
Changes from Original (January 2015) to Revision A
- Added TPL5x1x Family of Nano Timers table
- Changed TADC and RD equations in the Quantization Error section
- Added Receiving Notification of Documentation Updates section
5 Device Comparison Table
TPL5x1x Family of Nano Timers
| PART NUMBER | Special Features | Output | Rating |
|---|---|---|---|
| TPL5010 | Low Power Timer, Watchdog Functionality | Active High | Catalog |
| TPL5010Q | Low Power Timer, Watchdog Functionality | Active High | Automotive |
| TPL5111 | Low Power Timer, Power Gating MOS-Driver | Active High | Catalog |
| TPL5110 | Low Power Timer, Power Gating MOS-Driver | Active Low | Catalog |
6 Pin Configuration and Functions
Diagram of the DDC Package, 6-Lead SOT-23, Top View, showing pin numbers 1 through 6 and their names: 1-VDD, 2-GND, 3-DELAY/M_RST, 4-DONE, 5-WAKE, 6-RSTn.
Pin Functions
| PIN NO. | NAME | TYPE(1) | DESCRIPTION | APPLICATION INFORMATION |
|---|---|---|---|---|
| 1 | VDD | P | Supply voltage | |
| 2 | GND | G | Ground | |
| 3 | DELAY/ M_RST | I | Time Interval set and Manual Reset | Resistance between this pin and GND is used to select the time interval. The reset switch is also connected to this pin. |
| 4 | DONE | I | Logic Input for watchdog functionality | Digital signal driven by the µC to indicate successful processing of the WAKE signal. |
| 5 | WAKE | O | Timer output signal generated every tIP period. | Digital pulsed signal to wake up the µC at the end of the programmed time interval. |
| 6 | RSTn | O | Reset Output (open drain output) | Digital signal to RESET the µC, pullup resistance is required |
(1) G= Ground, P= Power, O= Output, I= Input.
7 Specifications
7.1 Absolute Maximum Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | -0.3 | 6 | V |
| Input Voltage at any pin(2) | -0.3 | VDD + 0.3 | V |
| Input Current on any pin | -5 | +5 | mA |
| Junction Temperature, TJ(3) | 150 | °C | |
| Storage Temperature, Tstg | -65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage between any two pins should not exceed 6V. (3) The maximum power dissipation is a function of TJ(MAX), JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a printed-circuit board (PCB).
7.2 ESD Ratings
| V(ESD) | VALUE | UNIT | |
|---|---|---|---|
| Electrostatic discharge | Human Body Model, per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-101(2) | ±250 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Ratings
| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply Voltage (VDD-GND) | 1.8 | 5.5 | V |
| Temperature | -40 | 105 | °C |
7.4 Thermal Information
| THERMAL METRIC(1) | TPL5010 DDC (SOT-23) 6 PINS | UNIT |
|---|---|---|
| RθJA Junction-to-ambient thermal resistance | 163 | °C/W |
| RθJC(top) Junction-to-case (top) thermal resistance | 26 | °C/W |
| RθJB Junction-to-board thermal resistance | 57 | °C/W |
| ΨJT Junction-to-top characterization parameter | 7.5 | °C/W |
| ΨJB Junction-to-board characterization parameter | 57 | °C/W |
| RθJC(bot) Junction-to-case (bottom) thermal resistance | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
Specifications are for TA= 25°C, VDD-GND = 2.5 V, unless otherwise stated.
| PARAMETER | TEST CONDITIONS | MIN(2) | TYP(3) | MAX(2) | UNIT |
|---|---|---|---|---|---|
| POWER SUPPLY | |||||
| IDD Supply current(4) | Operation mode Digital conversion of external resistance (Rext) | 35 | 50 | nA | |
| TIMER | |||||
| tIP Time Interval Period | 1650 selectable Time Intervals | Minimum time interval | 100 | ms | |
| Maximum time interval | 7200 | s | |||
| Time Interval Setting Accuracy(5) | Excluding the precision of Rext | ±0.6% | % | ||
| Timer Interval Setting Accuracy over supply voltage | 1.8 V ≤ VDD ≤ 5.5 V | ±25 | ppm/V | ||
| tOSC Oscillator Accuracy | -40°C ≤ TA ≤ 105°C | -0.5% | 0.5% | ||
| Oscillator Accuracy over temperature(6) | ±100 | ±400 | ppm/°C | ||
| Oscillator Accuracy over supply voltage | 1.8 V ≤ VDD ≤ 5.5 V | ±0.4 | %/V | ||
| Oscillator Accuracy over life time(7) | 0.24% | ||||
| tDONE DONE Pulse width (6) | 100 | ns | |||
| tRSTn RSTn Pulse width | 320 | ms | |||
| tWAKE WAKE Pulse width | 20 | ms | |||
| t_Rext Time to convert Rext | 100 | 120 | ms | ||
| DIGITAL LOGIC LEVELS | |||||
| VIH Logic High Threshold DONE pin | 0.7 × VDD | V | |||
| VIL Logic Low Threshold DONE pin | 0.3 x VDD | V | |||
| VOH Logic output High Level WAKE pin | Iout = 100 µA Iout = 1 mA | VDD - 0.3 VDD - 0.7 | V | ||
| VOL Logic output Low Level WAKE pin | Iout = -100 µA Iout = -1 mA | 0.3 | V | ||
| VOLRSTN RSTn Logic output Low Level | IOL = -1 mA | 0.3 | V | ||
| IOHRSTN RSTn High Level output current | VOHRSTN = VDD | 1 | nA | ||
| VIHM_RST Logic High Threshold DELAY/M_RST pin | 1.5 | V | |||
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current excludes load and pullup resistor current. Input pins are at GND or VDD. (5) The accuracy for time interval settings below 1 second is ±100 ms. (6) This parameter is specified by design and/or characterization and is not tested in production. (7) Operational life time test procedure equivalent to 10 years.
7.6 Timing Requirements
| MIN(1) | NOM(2) | MAX(1) | UNIT | ||
|---|---|---|---|---|---|
| trRSTn | Rise Time RSTn (3) | 11 | µs | ||
| tfRSTn | Fall Time RSTn (3) | Capacitive load 50 pF, Rpullup 100 kΩ | 50 | ns | |
| trWAKE | Rise Time WAKE (3) | Capacitive load 50 pF | 50 | ns | |
| tfWAKE | Fall Time WAKE (3) | Capacitive load 50 pF | 50 | ns | |
| tDDONE | DONE to RSTn or WAKE to DONE delay | Minimum delay(4) Maximum delay(4) | 100 | ns | |
| tIP | 20ms | ms | |||
| tM_RST | Valid Manual Reset | Observation time 30 ms | 20 | ms | |
| tDB | De-bounce Manual Reset | 20 | ms |
Timing diagram showing the relationship between VDD, WAKE, DONE, RSTn, and DELAY/M_RST signals over time. It illustrates rise and fall times, pulse widths, delays, and intervals like tIP, tDDONE, tM_RST, and tDB, as well as the watchdog timing where a missed DONE signal triggers RSTn.
7.7 Typical Characteristics
Graph titled 'IDD vs. VDD'. Shows supply current (nA) on the Y-axis and Supply Voltage (V) on the X-axis. Multiple curves represent different ambient temperatures (TA = -40°C, 25°C, 70°C, 105°C).
Graph titled 'IDD vs. Temperature'. Shows supply current (nA) on the Y-axis and Temperature (°C) on the X-axis. Multiple curves represent different supply voltages (VDD = 1.8V, 2.5V, 3.3V, 5.5V).
Graph titled 'Oscillator Accuracy vs. VDD'. Shows oscillator accuracy (%) on the Y-axis and Supply Voltage (V) on the X-axis. Multiple curves represent different ambient temperatures (TA = -40°C, 25°C, 70°C, 105°C).
Graph titled 'Oscillator Accuracy vs. Temperature'. Shows oscillator accuracy (%) on the Y-axis and Temperature (°C) on the X-axis. Multiple curves represent different supply voltages (VDD = 1.8V, 2.5V, 3.3V, 5.5V).
Graph titled 'IDD vs. Time'. Shows supply current (µA) on the Y-axis (logarithmic scale) and Time (s) on the X-axis. It shows a high current during POR/REXT READING phase, followed by a lower, stable current during TIMER MODE.
Histogram titled 'Time Interval Setting Accuracy'. Shows Frequency (%) on the Y-axis and Accuracy (%) on the X-axis. The distribution shows accuracy for time intervals between 1s and 7200s, with a mean around 0% and a spread of approximately ±0.6%.
8 Detailed Description
8.1 Overview
The TPL5010 is a system wake-up timer with a watchdog feature designed for low-power applications. The TPL5010 can be used in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.
8.2 Functional Block Diagram
Block diagram of the TPL5010. Inputs are VDD and DELAY/M_RST. Outputs are RSTn, WAKE, and DONE. Internal blocks include a LOW FREQUENCY OSCILLATOR, FREQUENCY DIVIDER, LOGIC CONTROL, and a DECODER & MANUAL RESET DETECTOR. GND is also an input.
8.3 Feature Description
The DONE, WAKE and RSTn signals are used to implement the watchdog function. The TPL5010 is programmed to issue a periodic WAKE pulse to a µC which is in sleep or standby mode. After receiving the WAKE pulse, the µC must issue a DONE signal to the TPL5010 at least 20 ms before the rising edge of the next WAKE pulse. If the DONE signal is not asserted, the TPL5010 asserts the RSTn signal to reset the µC. A manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD.
WAKE
The WAKE pulse is sent out from the TPL5010 when the programmed time interval starts (except at the beginning of the first cycle or if in the previous interval the DONE has not been received). This signal is normally low.
DONE
The DONE pin is driven by a µC to signal successful processing of the WAKE signal. The TPL5010 recognizes a valid DONE signal as a low to high transition. If two or more DONE signals are received within the time interval, only the first DONE signal is processed. The DONE signal resets the counter of the watchdog only. If the DONE signal is received when the WAKE is still high, the WAKE will go low as soon as the DONE is recognized.
RSTn
To implement the reset interface between the TPL5010 and the µC a pullup resistance is required. 100 KΩ is recommended to minimize current. During the POR and the reading of the REXT, the RSTn signal is LOW. RSTn is asserted (LOW) for either one of the following conditions: 1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately 20 ms). 2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising edge (see Figure 8).
8.4 Device Functional Modes
Start-Up
During start-up after POR, the TPL5010 executes a one-time measurement of the resistance attached to the DELAY/M_RST pin to determine the desired time interval for WAKE. This measurement interval is tR_EXT. During this measurement, a constant current is temporarily flowing into REXT. Timing diagram showing WAKE, DONE, RSTn, and DELAY/M_RST signals during the start-up phase. It illustrates the POR event, the RESISTANCE READING period (tR_EXT), and the subsequent WAKE pulse (tR_EXT + tRSTn + tIP).
Normal Operating Mode
During normal operating mode, the TPL5010 asserts periodic WAKE pulses in response to valid DONE pulses from the µC. If either a manual reset is applied (logic HIGH on DELAY/M_RST pin), or the µC does not issue a DONE pulse within the required time, the TPL5010 asserts the RSTn signal to the µC and restarts its internal counters. See Figure 8 and Figure 10.
8.5 Programming
Configuring the WAKE Interval With the DELAY/M_RST Pin
The time interval between two adjacent WAKE pulses (rising edges) is selectable through an external resistance (REXT) between the DELAY/M_RST pin and ground. The value of the resistance REXT is converted one time after POR. The allowable range of REXT is 500 Ω to 170 kΩ. At least a 1% precision resistance is recommended. See section Timer Interval Selection Using External Resistance on how to set the WAKE pulse interval using REXT. The time between two adjacent RESET signals (falling edges), or between a RESET (falling edge) and a WAKE (rising edge), is given by the sum of the programmed time interval and the tRSTn (reset pulse width).
Manual Reset
If VDD is connected to the DELAY/M_RST pin, the TPL5010 recognizes this as a manual reset condition. In this case, the time interval is not set. If the manual reset is asserted during the POR or during the reading procedure, the reading procedure is aborted and is restarted as soon as the manual reset switch is released. A pulse on the DELAY/M_RST pin is recognized as a valid manual reset only if it lasts at least 20 ms (observation time is 30 ms). A valid manual reset resets all the counters inside the TPL5010. The counters restart only when the high digital voltage at DELAY/M_RST is removed and the next tRSTn is elapsed. Timing diagram illustrating a manual reset. It shows WAKE, DONE, RSTn, and DELAY/M_RST signals. A VALID M_RST pulse (high on DELAY/M_RST for at least 20ms) triggers an ANY RESET condition, asserting RSTn LOW for a duration (tM_RST + tDB + tRSTn).
DELAY/M_RST
A resistance in the range between 500 Ω and 170 kΩ needs to be connected to select a valid time interval. At the POR and during the reading of the resistance the DELAY/M_RST is connected to an analog signal chain though a mux. After the reading of the resistance the analog circuit is switched off and the DELAY/RST is connected to a digital circuit. The manual reset detection is supported with a de-bounce feature which makes the TPL5010 insensitive to the glitches on the DELAY/M_RST pin. When a valid manual reset signal is asserted on the DELAY/M_RST pin, the RSTn signal is asserted LOW after a delay of tM_RST. It remains LOW after a valid manual reset is asserted + tDB + tRSTn. Due to the asynchronous nature of the manual reset signal and its arbitrary duration, the LOW status of the RSTn signal maybe affected by an uncertainty of about ±5 ms. A valid manual reset puts all the digital output signals at their default values: WAKE = LOW, RSTn = asserted LOW.
Circuitry
The manual reset may be implemented using a switch (momentary mechanical action). The TPL5010 offers two possible approaches according to the power consumption constraints of the application.
9 Application and Implementation
9.1 Application Information
In battery-powered applications, one design constraint is the need for low current consumption. The TPL5010 is designed for applications where there is a need to monitor environmental conditions at a fixed time interval. Often in these applications a watchdog or other internal timer in a µC is used to implement a wake-up function. Using the TPL5010 to implement the watchdog function will consume only tens of nA, significantly improving the power consumption of the system.
9.2 Typical Application
The TPL5010 can be used in conjunction with environment sensors to build a low-power environment data-logger, such as an air quality data-logger. In this application, due to the monitored phenomena, the µC and the front end of the sensor spend most of the time in the idle state, waiting for the next logging interval, usually a few hundred of milliseconds. Figure 13 shows a data logging application based on a µC and a front end for a gas sensor based on the LMP91000. A detailed schematic for a data-logger application. It shows a Lithium-ion battery, a POWER MANAGEMENT block, the TPL5010, a microcontroller (µC), and a gas sensor front-end (LMP91000). The TPL5010 manages wake-up and timing for the µC and sensor. Peripherals like a display and keyboard are also connected.
9.2.1 Design Requirements
The design is driven by the low-current consumption constraint. The data are usually acquired on a rate that ranges between 1 s and 10 s. The highest necessity is the maximization of the battery life. The TPL5010 helps achieve that goal because it allows putting the µC in its lowest power mode. The TPL5010 will take care of the watchdog and the timing.
9.2.2 Detailed Design Procedure
When the main constraint is the battery life, the selection of a low power voltage reference, the µC, and the display is mandatory. The first step in the design is the calculation of the power consumption of the devices in their different mode of operations. For instance, the LMP91000 burns most of the power when in gas measurement mode, then, according to the connected gas sensor, it has two idle states (standby and deep sleep). The same is true for the µC, such as one of the MSP430 family, which can be placed in one of its lower power modes, such as LMP3.5 or LMP4.5. In this case, the TPL5010 can be used to implement the watchdog and wake-up timing functions. After the power budget calculation, it is possible to select the appropriate time interval which satisfies the application constraints and maximize the life of the battery.
9.2.3 Application Curve
A line graph titled 'Effect of TPL5010 on Current Consumption'. The Y-axis represents 'Current consumption' and the X-axis represents 'Time'. Two lines are plotted: 'Without TPL5010' showing a higher, sustained current, and 'With TPL5010' showing significantly lower, intermittent current spikes.
10 Power Supply Recommendations
The TPL5010 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of 0.1 µF between VDD and GND pin is recommended.
11 Layout
11.1 Layout Guidelines
The DELAY/M_RST pin is sensitive to parasitic capacitance. TI suggests that the traces connecting the resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This capacitance can affect the initial set up of the time interval. Signal integrity on the WAKE and RSTn pins is also improved by keeping the trace length between the TPL5010 and the µC short to reduce the parasitic capacitance.
11.2 Layout Example
A top-down view of a PCB layout example for the TPL5010. It shows the placement of the TPL5010 IC, a MANUAL RESET SWITCH, a capacitor C1, a resistor RP, and the R_EXT resistor. Connections to VDD, GND, RSTn, WAKE, DELAY/M_RST, and DONE are indicated, along with a ground plane.
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community: TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support: TI's Design Support. Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 - TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Package Option Addendum
| Orderable Device | Status | Package Type | Package Drawing | Pins | Package Qty | Eco Plan(2) | Lead finish/ Ball material(6) | MSL Peak Temp(3) | Op Temp (°C) | Device Marking(4/5) | Samples |
|---|---|---|---|---|---|---|---|---|---|---|---|
| TPL5010DDCR | ACTIVE | SOT-23-THIN | DDC | 6 | 3000 | RoHS & Green | NIPDAU | Level-1-260C-UNLIM | -40 to 105 | ZAKX | |
| TPL5010DDCT | ACTIVE | SOT-23-THIN | DDC | 6 | 250 | RoHS & Green | NIPDAU | Level-1-260C-UNLIM | -40 to 105 | ZAKX | Samples |
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.
Other Qualified Versions
Automotive: TPL5010-Q1. NOTE: Qualified Version Definitions: Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects.
Tape and Reel Information
Diagrams illustrating Reel Dimensions and Tape Dimensions, including definitions for A0, B0, K0, W, and P1. Also shows Quadrant Assignments for Pin 1 Orientation in Tape.
| Device | Package Type | Package Drawing | Pins | SPQ | Reel Diameter (mm) | Reel Width W1 (mm) | A0 (mm) | B0 (mm) | K0 (mm) | P1 (mm) | W (mm) | Pin1 Quadrant |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| TPL5010DDCR | SOT-23-THIN | DDC | 6 | 3000 | 178.0 | 8.4 | 3.2 | 3.2 | 1.4 | 4.0 | 8.0 | Q3 |
| TPL5010DDCT | SOT-23-THIN | DDC | 6 | 250 | 178.0 | 8.4 | 3.2 | 3.2 | 1.4 | 4.0 | 8.0 | Q3 |
| TPL5010DDCT | SOT-23-THIN | DDC | 6 | 250 | 180.0 | 8.4 | 3.1 | 3.05 | 1.1 | 4.0 | 8.0 | Q3 |
Tape and Reel Box Dimensions
| Device | Package Type | Package Drawing | Pins | SPQ | Length (mm) | Width (mm) | Height (mm) |
|---|---|---|---|---|---|---|---|
| TPL5010DDCR | SOT-23-THIN | DDC | 6 | 3000 | 208.0 | 191.0 | 35.0 |
| TPL5010DDCT | SOT-23-THIN | DDC | 6 | 250 | 208.0 | 191.0 | 35.0 |
| TPL5010DDCT | SOT-23-THIN | DDC | 6 | 250 | 183.0 | 183.0 | 20.0 |
Package Outline
Drawings illustrating the SOT-23 - 1.1 max height package outline for a small outline transistor. Includes top view, side view, and end view with detailed dimensions and tolerances per ASME Y14.5M.
Example Board Layout
Diagram showing the recommended land pattern example for the SOT-23 package on a PCB. Includes details on solder mask openings, exposed metal, and solder mask definitions.
Example Stencil Design
Diagram showing the solder paste example for the SOT-23 package, based on a 0.125 thick stencil. Includes recommendations for stencil design.
Important Notice and Disclaimer
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