AD8041: 160 MHz Rail-to-Rail Amplifier with Disable

Features

Fully Specified for +3 V, +5 V, and ±5 V Supplies
Output Swings Rail to Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 1 V Beyond Supplies
Disable/Power-Down Capability
Low Power of 5.2 mA (26 mW on 5 V)
High Speed and Fast Settling on 5 V:

160 MHz -3 dB Bandwidth (G = +1)
160 V/µs Slew Rate
30 ns Settling Time to 0.1%

Good Video Specifications (R_L = 150 Ω, G = +2)

Gain Flatness of 0.1 dB to 30 MHz
0.03% Differential Gain Error
0.03° Differential Phase Error

Low Distortion

-69 dBc Worst Harmonic @ 10 MHz

Outstanding Load Drive Capability

Drives 50 mA 0.5 V from Supply Rails
Cap Load Drive of 45 pF

Product Description

The AD8041 is a low power voltage feedback, high-speed amplifier designed to operate on +3 V, +5 V, or ±5 V supplies. It offers true single-supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail. The output voltage swing extends to within 50 mV of each rail, providing maximum output dynamic range. It features gain flatness of 0.1 dB to 30 MHz and differential gain and phase error of 0.03% and 0.03°, respectively, on a single 5 V supply. This makes the AD8041 ideal for professional video electronics such as cameras and video switchers, as well as any high-speed portable equipment. Its low distortion and fast settling make it suitable for buffering high-speed A-to-D converters. The AD8041 includes a high-speed disable feature for multiplexing or power reduction (1.5 mA typical). The disable logic interface is compatible with CMOS or open-collector logic. With a low supply current of 5.8 mA maximum, it can operate on a single 3 V power supply, making it ideal for portable and battery-powered applications. The 160 MHz bandwidth and 160 V/µs slew rate on a single 5 V supply make the AD8041 versatile for general-purpose high-speed applications requiring dual supplies up to ±6 V or single supplies from 3 V to 12 V. The AD8041 is available in 8-lead plastic DIP and SOIC packages for the industrial temperature range of -40°C to +85°C.

Connection Diagram

The AD8041 is available in 8-lead DIP and SOIC packages. The pins are as follows: Pin 1: NC (No Connect), Pin 2: -INPUT, Pin 3: +INPUT, Pin 4: -Vs, Pin 5: NC (No Connect), Pin 6: OUTPUT, Pin 7: +Vs, Pin 8: DISABLE.

Key Performance Graphs

Figure 1. Output Swing: G = -1, V_S = 5 V: This graph illustrates the output voltage waveform over time, demonstrating the amplifier's ability to swing close to the supply rails.

Figure 2. Frequency Response: G = +2, V_S = 5 V: This graph shows the normalized gain in dB versus frequency in MHz for a gain of +2 and a 5 V supply, indicating the amplifier's bandwidth and gain flatness.

Specifications

Specifications are provided for various supply voltages and conditions. Key parameters include Dynamic Performance, Noise/Distortion Performance, DC Performance, Input Characteristics, Output Characteristics, Power Supply, and Disable Characteristics.

Specifications (@ T_A = 25°C, V_S = 5 V, R_L = 2 kΩ to 2.5 V)

Parameter	Conditions	Min	Typ	Max	Unit
DYNAMIC PERFORMANCE
-3 dB Small Signal Bandwidth, V_O < 0.5 V p-p	G = +1	130	160		MHz
Bandwidth for 0.1 dB Flatness	G = +2, R_L = 150 Ω		30		MHz
Slew Rate	G = -1, V_O = 2 V Step	130	160		V/µs
Full Power Response	V_O = 2 V p-p		24		MHz
Settling Time to 0.1%	G = -1, V_O = 2 V Step		35		ns
Settling Time to 0.01%			55		ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion	f_C = 5 MHz, V_O = 2 V p-p, G = +2, R_L = 1 kΩ		-72		dB
Input Voltage Noise	f = 10 kHz		16		nV/√Hz
Input Current Noise	f = 10 kHz		600		fA/√Hz
Differential Gain Error (NTSC)	G = +2, R_L = 150 Ω to 2.5 V		0.03		%
Differential Phase Error (NTSC)	G = +2, R_L = 75 Ω to 2.5 V		0.01		%
	G = +2, R_L = 150 Ω to 2.5 V		0.03		Degrees
	G = +2, R_L = 75 Ω to 2.5 V		0.19		Degrees
DC PERFORMANCE
Input Offset Voltage	T_MIN to T_MAX		2	7	mV
Offset Drift			8		mV
Input Bias Current		10			µV/°C
Input Offset Current		1.2	3.2		µA
Open-Loop Gain	R_L = 1 kΩ		3.5		µA
	T_MIN to T_MAX	86	95		dB
			90		dB
INPUT CHARACTERISTICS
Input Resistance		160			kΩ
Input Capacitance		1.8			pF
Input Common-Mode Voltage Range	V_CM = 0 V to 3.5 V	-0.2	+4	V
Common-Mode Rejection Ratio		74	80		dB
OUTPUT CHARACTERISTICS
Output Voltage Swing: R_L = 10 kΩ		0.05 to 4.95		V
Output Voltage Swing: R_L = 1 kΩ		0.1 to 4.9		V
Output Voltage Swing: R_L = 50 Ω	V_OUT = 0.5 V to 4.5 V	0.3 to 4.5		V
Output Current	Sourcing		50		mA
Short Circuit Current			90		mA
Capacitive Load Drive	G = +1		150		mA
			45		pF
POWER SUPPLY
Operating Range		3	12	V
Quiescent Current		5.2	5.8	mA
Quiescent Current (Disabled)		1.4	1.7	mA
Power Supply Rejection Ratio	V_S = 0, +5 V, ±1 V	72	80		dB
DISABLE CHARACTERISTICS
Turn-Off Time	V_O = 2 V p-p @ 10 MHz, G = +2	120		ns
Turn-On Time	R_F = R_L = 2 kΩ	230		ns
Off Isolation (Pin 8 Tied to -V_S)	R_F = R_L = 2 kΩ	70		dB
Off Voltage (Device Disabled)	R_L = 100 Ω, f = 5 MHz, G = +2, R_F = 1 kΩ	<V_S - 2.5		V
On Voltage (Device Enabled)		Open or +V_S		V

Specifications (@ T_A = 25°C, V_S = 3 V, R_L = 2 kΩ to 1.5 V)

Parameter	Conditions	Min	Typ	Max	Unit
DYNAMIC PERFORMANCE
-3 dB Small Signal Bandwidth, V_O < 0.5 V p-p	G = +1	120	150		MHz
Bandwidth for 0.1 dB Flatness	G = +2, R_L = 150 Ω		25		MHz
Slew Rate	G = -1, V_O = 2 V Step	120	150		V/µs
Full Power Response	V_O = 2 V p-p		20		MHz
Settling Time to 0.1%	G = -1, V_O = 2 V Step		40		ns
Settling Time to 0.01%			55		ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion	f_C = 5 MHz, V_O = 2 V p-p, G = -1, R_L = 100 Ω		-55		dB
Input Voltage Noise	f = 10 kHz		16		nV/√Hz
Input Current Noise	f = 10 kHz		600		fA/√Hz
Differential Gain Error (NTSC)	G = +2, R_L = 150 Ω to 1.5 V, Input V_CM = 1 V		0.07		%
Differential Phase Error (NTSC)	G = +2, R_L = 150 Ω to 1.5 V, Input V_CM = 1 V		0.05		Degrees
DC PERFORMANCE
Input Offset Voltage	T_MIN to T_MAX		2	7	mV
Offset Drift			8		mV
Input Bias Current		10			µV/°C
Input Offset Current		1.2	3.2		µA
Open-Loop Gain	R_L = 1 kΩ		3.5		µA
	T_MIN to T_MAX	85	94		dB
			89		dB
INPUT CHARACTERISTICS
Input Resistance		160			kΩ
Input Capacitance		1.8			pF
Input Common-Mode Voltage Range	V_CM = 0 V to 1.5 V	-0.2	+2	V
Common-Mode Rejection Ratio		72	80		dB
OUTPUT CHARACTERISTICS
Output Voltage Swing: R_L = 10 kΩ		0.05 to 2.95		V
Output Voltage Swing: R_L = 1 kΩ		0.45 to 2.7	0.1 to 2.9	V
Output Voltage Swing: R_L = 50 Ω	V_OUT = 0.5 V to 2.5 V	0.5 to 2.6	0.25 to 2.75	V
Output Current	Sourcing		50		mA
Short Circuit Current			70		mA
Capacitive Load Drive	G = +1		120		mA
			40		pF
POWER SUPPLY
Operating Range		3	12	V
Quiescent Current		5.0	5.6	mA
Quiescent Current (Disabled)		1.3	1.5	mA
Power Supply Rejection Ratio	V_S = 0, +3 V, ±0.5 V	68	80		dB
DISABLE CHARACTERISTICS
Turn-Off Time	V_O = 2 V p-p @ 10 MHz, G = +2	90		ns
Turn-On Time	R_F = R_L = 2 kΩ	170		ns
Off Isolation (Pin 8 Tied to -V_S)	R_F = R_L = 2 kΩ	70		dB
Off Voltage (Device Disabled)	R_L = 100 Ω, f = 5 MHz, G = +2, R_F = 1 kΩ	<V_S - 2.5		V
On Voltage (Device Enabled)		Open or +V_S		V

Specifications (@ T_A = 25°C, V_S = ±5 V, R_L = 2 kΩ to 0 V)

Parameter	Conditions	Min	Typ	Max	Unit
DYNAMIC PERFORMANCE
-3 dB Small Signal Bandwidth, V_O < 0.5 V p-p	G = +1	140	170		MHz
Bandwidth for 0.1 dB Flatness	G = +2, R_L = 150 Ω		32		MHz
Slew Rate	G = -1, V_O = 2 V Step	140	170		V/µs
Full Power Response	V_O = 2 V p-p		26		MHz
Settling Time to 0.1%	G = -1, V_O = 2 V Step		30		ns
Settling Time to 0.01%			50		ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion	f_C = 5 MHz, V_O = 2 V p-p, G = +2, R_L = 1 kΩ		-77		dB
Input Voltage Noise	f = 10 kHz		16		nV/√Hz
Input Current Noise	f = 10 kHz		600		fA/√Hz
Differential Gain Error (NTSC)	G = +2, R_L = 150 Ω		0.02		%
Differential Phase Error (NTSC)	G = +2, R_L = 75 Ω		0.02		%
	G = +2, R_L = 150 Ω		0.03		Degrees
	G = +2, R_L = 75 Ω		0.10		Degrees
DC PERFORMANCE
Input Offset Voltage	T_MIN to T_MAX		2	7	mV
Offset Drift			8		mV
Input Bias Current		10			µV/°C
Input Offset Current		1.2	3.2		µA
Open-Loop Gain	R_L = 1 kΩ		3.5		µA
	T_MIN to T_MAX	90	99		dB
			95		dB
INPUT CHARACTERISTICS
Input Resistance		160			kΩ
Input Capacitance		1.8			pF
Input Common-Mode Voltage Range	V_CM = -5 V to +3.5 V	-5.2	+4	V
Common-Mode Rejection Ratio		72	80		dB
OUTPUT CHARACTERISTICS
Output Voltage Swing: R_L = 10 kΩ		-4.95 to +4.95		V
Output Voltage Swing: R_L = 1 kΩ		-4.45 to +4.6	-4.8 to +4.8	V
Output Voltage Swing: R_L = 50 Ω	V_OUT = -4.5 V to +4.5 V	-4.3 to +3.2	-4.5 to +3.8	V
Output Current	Sourcing		50		mA
Short Circuit Current			100		mA
Capacitive Load Drive	G = +1		160		mA
			50		pF
POWER SUPPLY
Operating Range		3	12	V
Quiescent Current		5.8	6.5	mA
Quiescent Current (Disabled)		1.6	2.2	mA
Power Supply Rejection Ratio	V_S = -5 V, +5 V, ±1 V	68	80		dB
DISABLE CHARACTERISTICS
Turn-Off Time	V_O = 2 V p-p @ 10 MHz, G = +2	120		ns
Turn-On Time	R_F = 2 kΩ	320		ns
Off Isolation (Pin 8 Tied to -V_S)	R_F = 2 kΩ	70		dB
Off Voltage (Device Disabled)	R_L = 100 Ω, f = 5 MHz, G = +2, R_F = 1 kΩ	<V_S - 2.5		V
On Voltage (Device Enabled)		Open or +V_S		V

Absolute Maximum Ratings

Rating	Value
Supply Voltage	12.6 V
Internal Power Dissipation²
Plastic DIP Package (N)	1.3 Watts
Small Outline Package (R)	0.9 Watts
Input Voltage (Common Mode)	±V_S
Differential Input Voltage	±3.4 V
Output Short Circuit Duration	Observe Power Derating Curves
Storage Temperature Range (N, R)	-65°C to +125°C
Operating Temperature Range (A Grade)	-40°C to +85°C
Lead Temperature Range (Soldering 10 sec)	300°C

NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Specification is for the device in free air: 8-Lead Plastic DIP Package: θ_JA = 90°C/W. 8-Lead SOIC Package: θ_JA = 155°C/W.

Maximum Power Dissipation

The maximum power that can be safely dissipated by the AD8041 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8041 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.

Figure 3. Maximum Power Dissipation vs. Temperature: This graph shows the maximum power dissipation in Watts versus ambient temperature in °C for both 8-Lead Plastic DIP and 8-Lead SOIC packages, illustrating the power derating required to maintain a junction temperature of 150°C.

Ordering Guide

Model	Temperature Range	Package Description	Package Options
AD8041AN	-40°C to +85°C	8-Lead Plastic DIP	N-8
AD8041AR	-40°C to +85°C	8-Lead Plastic SOIC	SO-8
AD8041AR-REEL	-40°C to +85°C	13" Tape and Reel	SO-8
AD8041AR-REEL7	-40°C to +85°C	7" Tape and Reel	SO-8
AD8041-EB		Evaluation Board
5962-9683901MPA*	-55°C to +125°C	8-Lead Cerdip	Q-8

*Refer to official DSCC drawing for tested specifications.

Safety Information

CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8041 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING! ESD SENSITIVE DEVICE

Typical Performance Characteristics

The following graphs illustrate typical performance data for the AD8041:

TPC 1. Typical Distribution of V_OS: A histogram showing the distribution of input offset voltage (V_OS) in mV.

TPC 2. V_OS Drift Over –40°C to +85°C: A graph depicting input offset voltage drift in µV/°C versus temperature in °C.

TPC 3. I_B vs. Temperature: A graph showing input bias current (I_B) in µA versus temperature in °C.

TPC 4. Open-Loop Gain vs. R_L to 25°C: A graph illustrating open-loop gain in dB versus load resistance (R_L) in Ω at 25°C.

TPC 5. Open-Loop Gain vs. Temperature: A graph showing open-loop gain in dB versus temperature in °C for various supply voltages and load conditions.

TPC 6. Open-Loop Gain vs. Output Voltage: A graph depicting open-loop gain in dB versus output voltage in Volts for different load conditions.

TPC 7. Input Voltage Noise vs. Frequency: A graph showing input voltage noise in nV/√Hz versus frequency in Hz.

TPC 8. Total Harmonic Distortion: A graph illustrating total harmonic distortion in dBc versus fundamental frequency in MHz for various supply voltages, gains, and load conditions.

TPC 9. Worst Harmonic vs. Output Voltage: A graph showing worst harmonic distortion in dBc versus output voltage (V_PP).

TPC 10. Differential Gain and Phase Errors: Bar charts displaying differential gain (%) and differential phase (Degrees) versus DC output level (100 IRE MAX) for different supply voltages and load conditions.

TPC 11. 0.1 dB Gain Flatness: A graph showing closed-loop gain in dB versus frequency in MHz for specific supply voltage and feedback resistor conditions, indicating the frequency range for flat response.

TPC 12. Open-Loop Gain and Phase vs. Frequency: A graph depicting open-loop gain in dB and phase in Degrees versus frequency in MHz for a specific supply voltage and load condition.

TPC 13. Closed-Loop Frequency Response vs. Temperature: A graph showing closed-loop gain in dB versus frequency in MHz at different temperatures.

TPC 14. Closed-Loop Frequency Response vs. Supply: A graph illustrating closed-loop gain in dB versus frequency in MHz for different supply voltages.

TPC 15. Output Resistance vs. Frequency: A graph showing output resistance in Ω versus frequency in MHz for a specific gain and supply voltage.

TPC 16. Settling Time vs. Input Step: A graph depicting settling time in ns versus input step voltage in Volts p-p for different supply voltages and accuracy levels (0.1%, 1%).

TPC 17. CMRR vs. Frequency: A graph showing common-mode rejection ratio (CMRR) in dB versus frequency in MHz for specific supply voltages.

TPC 18. Output Saturation Voltage vs. Load Current: A graph illustrating output saturation voltage in mV versus load current in mA for different supply voltages and temperature conditions, indicating output voltage limits.

TPC 19. Supply Current vs. Temperature: A graph showing supply current in mA versus temperature in °C for different supply voltages.

TPC 20. PSRR vs. Frequency: A graph depicting power supply rejection ratio (PSRR) in dB versus frequency in MHz for positive and negative supply variations.

TPC 21. Output Voltage Swing vs. Frequency: A graph showing output voltage swing in V_PP versus frequency in MHz for a specific supply voltage and load.

TPC 22. Capacitive Load vs. Series Resistance: A graph illustrating capacitive load in pF versus series resistance in Ω for different phase margins, indicating stability with capacitive loads.

TPC 23. Frequency Response vs. Closed-Loop Gain: A graph showing normalized output in dB versus frequency in MHz for different closed-loop gains.

TPC 24. Pulse Response, V_S = 3 V: An oscilloscope trace showing output voltage versus time for a specific input pulse, supply voltage, and gain.

TPC 25a-b. Output Swing vs. Load Reference Voltage, V_S = 5 V, G = -1: Oscilloscope traces demonstrating output voltage versus time for different load conditions and supply voltages, illustrating output swing limits.

TPC 26. One Volt Step Response, V_S = 5 V, G = +2: An oscilloscope trace showing output voltage versus time for a 1V input step.

TPC 27. 100 mV Step Response, V_S = 5 V, G = +1: An oscilloscope trace showing output voltage versus time for a 100mV input step.

TPC 28. Output Swing, V_S = 3 V, V_IN = 3 V p-p: An oscilloscope trace showing output voltage versus time for specific input signal conditions and supply voltages.

TPC 29. Output Swing, V_S = 3 V, V_IN = 2.8 V p-p: An oscilloscope trace showing output voltage versus time for specific input signal conditions and supply voltages.

Circuit Description and Applications

The AD8041 is fabricated using Analog Devices' proprietary eXtra-Fast Complementary Bipolar (XFCB) process, enabling high-frequency performance. The device utilizes a differential output input stage for maximized bandwidth and headroom, and a complementary common-emitter output stage for excellent load drive.

Overdrive Recovery

Figure 4. Overdrive Recovery: This oscilloscope trace shows the amplifier recovering from overdrive conditions, illustrating recovery times of 50 ns from negative overdrive and 25 ns from positive overdrive.

Circuit Description

The internal design employs a "Nested Integrator" topology. The output stage is modeled as an ideal op amp with a single-pole response. The output impedance is low at low frequencies due to feedback, reducing to less than 0.1 Ω with 110 dB open-loop gain. At higher frequencies, the output impedance rises but remains manageable due to integrator capacitors, allowing for good capacitive load drive capability (e.g., 45° phase margin with a 20 pF load).

Figure 5. AD8041 Simplified Schematic: This diagram shows the internal simplified schematic of the AD8041, highlighting transistors, resistors, and capacitors that form the amplifier's architecture.

Figure 6. Small Signal Schematic: This schematic provides a small-signal model of the amplifier, detailing transconductances (gm), resistances (R), and capacitances (C) used in its analysis.

Disable Operation

The AD8041 features an active-low disable pin that can three-state the output and reduce supply current to less than 1.6 mA. This pin can be used to configure the AD8041 as a 2:1 multiplexer. The break-before-make switching time is approximately 50 ns for disabling and 300 ns for enabling.

Figure 7. 2:1 Multiplexer: This circuit diagram shows how the AD8041's disable pin can be used to create a 2:1 multiplexer.

Figure 8. 2:1 Multiplexer Performance: This oscilloscope trace demonstrates the performance of the 2:1 multiplexer circuit.

Applications

Single Supply A/D Conversion

Figure 9. 10-Bit, 40 MSPS A/D Conversion: This application circuit shows the AD8041 buffering an input signal for an AD9050 A/D converter, operating from a single 5 V supply. It provides 40 MSPS conversion with 10-bit performance.

Figure 10. FFT Output of Circuit in Figure 9: This plot displays the Fast Fourier Transform (FFT) output of the A/D conversion circuit, showing signal quality metrics like fundamental frequency, harmonics, and SNR.

RGB Buffer

The AD8041 can buffer RGB signals for driving monitors, operating from a single 3 V or 5 V supply. This eliminates the need for dual-supply op amps when buffering multiple monitors.

Figure 11. Single Supply RGB Buffer: This schematic illustrates a single-supply, gain-of-two buffer circuit for driving a second RGB monitor.

Figure 12. 3 V, RGB Buffer: This oscilloscope photo shows the output of the RGB buffer circuit operating from a 3 V supply.

Single Supply Composite Video Line Driver

The AD8041 can drive composite video signals. The input requires AC coupling and DC shifting to handle negative-going sync tips in a single-supply configuration.

Figure 13. Single Supply Composite Video Line Driver: This schematic shows a single-supply, gain-of-two composite video line driver circuit.

Sync Stripper

For RGB monitor systems that carry synchronizing signals with the Green (G) signal, the AD8041 can be used to strip the sync portion.

Figure 14. Single Supply Sync Stripper: This schematic shows a circuit using the AD8041 to perform sync stripping on a video signal.

Figure 15. Single Supply Sync Stripper: This diagram shows a sync stripper circuit referencing an external DAC.

Evaluation Board

An evaluation board for the AD8041 is available, designed to demonstrate the specified high-speed performance. The board layout can be used as a guide for custom board designs.

Figure 16. Noninverting Configurations for Evaluation Boards: This schematic shows typical configurations for the AD8041 evaluation board.

Figure 17. Evaluation Board Silkscreen (Top): This diagram displays the silkscreen layout of the evaluation board's top side.

Figure 18. Board Layout (Component Side): This image shows the component placement on the evaluation board's top side.

Figure 19. Board Layout (Back Side): This image shows the routing on the evaluation board's back side.

Layout Considerations

Proper RF design techniques and low-pass parasitic component selection are crucial for achieving the AD8041's high-speed performance. Key considerations include using a ground plane, minimizing stray capacitance near input pins, using chip capacitors for supply bypassing, placing feedback resistors close to the inverting input, and employing stripline design for long signal traces.

Outline Dimensions

The AD8041 is available in several package types:

8-Lead Plastic DIP (N-8)

Standard dual in-line package with 8 pins.

8-Lead Plastic SOIC (SO-8)

Small outline surface-mount package with 8 pins.

8-Lead Ceramic DIP (Q-8)

Ceramic dual in-line package with 8 pins, often used for higher reliability or specific environmental requirements.

Revision History

Data Sheet changed from REV. 0 to REV. A. Specifications changed in DISABLE CHARACTERISTICS, Off Voltage (Device Disabled).

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