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Intel® Arria® 10 Hard Processor System Technical Reference Manual Comprehensive technical reference manual detailing the Intel® Arria® 10 Hard Processor System (HPS), including its Arm® Cortex®-A9 MPCore™ processors, peripherals, system interconnect, and integration with FPGA fabric. Covers clock management, reset, security, memory interfaces, and various communication protocols. |
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Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide This user guide provides a comprehensive overview of the Intel® SoC FPGA Embedded Development Suite (SoC EDS), a tool suite for embedded software development on Intel FPGA SoC devices. It covers installation, toolchains, development roles, bootloader management, hardware libraries, flash programming, compilers, and device tree generation, updated for Intel Quartus Prime Design Suite 20.1. |
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Intel® Agilex™ Hard Processor System Technical Reference Manual A comprehensive technical reference manual for the Intel® Agilex™ Hard Processor System (HPS), detailing its architecture, components, and functionalities. This manual is essential for developers working with Intel Agilex FPGAs. |
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Intel AN 932: Flash Access Migration Guidelines for SDM-Based Devices This Intel application note (AN 932) provides comprehensive guidelines for migrating flash access and Remote System Update (RSU) operations from control block-based FPGA devices to SDM-based architectures, covering Intel Arria 10, Stratix 10, and Agilex devices. |
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Intel Stratix 10 Hard Processor System Technical Reference Manual A comprehensive technical reference manual detailing the Intel Stratix 10 Hard Processor System (HPS), including its architecture, components, and functionality. This manual is updated for the Intel Quartus Prime Design Suite version 21.1. |
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Intel® FPGA SDK for OpenCL™ Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide This comprehensive guide details the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide. It covers essential procedures, design considerations, and integration steps for customizing the platform with the Intel FPGA SDK for OpenCL, targeting experienced FPGA developers. |
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DSP Builder for Intel® FPGAs Release Notes Comprehensive release notes for Intel® DSP Builder for FPGAs, detailing version updates, new features, bug fixes, and system requirements for software versions 22.4 and earlier, including revision history and MATLAB dependencies. |
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Intel Stratix 10 E-tile Hard IP Design Examples: Ethernet, CPRI PHY, and Dynamic Reconfiguration User Guide This user guide provides detailed information and examples for implementing Ethernet, CPRI PHY, and Dynamic Reconfiguration using the E-tile Hard IP on Intel Stratix 10 devices. It covers design generation, simulation, compilation, and hardware testing for various configurations. |