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Intel Stratix 10 E-tile Hard IP Design Examples

User Guide for Ethernet, CPRI PHY, and Dynamic Reconfiguration

Introduction

This document serves as a comprehensive user guide for the E-tile Hard IP design examples on Intel Stratix 10 devices. It details the implementation of Ethernet, CPRI PHY, and Dynamic Reconfiguration functionalities.

The guide covers various design examples, including:

  • E-tile Hard IP for Ethernet Intel FPGA IP design example
  • E-tile CPRI PHY Intel FPGA IP design example
  • E-tile Dynamic Reconfiguration design example

It provides step-by-step instructions for generating, simulating, compiling, and testing these designs in hardware. The document is updated for Intel® Quartus® Prime Design Suite version 19.3.

Key Features and Examples

Explore detailed examples for:

  • Ethernet IP: Covers 10GE, 25GE, and 100GE variants with optional RS-FEC and PTP support. Includes directory structures, simulation, and hardware design procedures.
  • CPRI PHY IP: Offers guidance on the E-tile CPRI PHY Intel FPGA IP design example, including quick start guides, hardware/software requirements, and simulation/hardware testing.
  • Dynamic Reconfiguration: Details the E-tile Dynamic Reconfiguration design example, covering functional descriptions, simulation, and hardware implementation for various Ethernet and CPRI configurations.

Resources

For more information, refer to the following resources:

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