Hardware Design Guideline for TPS65987 and TPS65988 USB Power Delivery Controllers

1.1 Power Supply Scheme

The power supply scheme involves LDOs to provide stable voltage rails. The VIN_3V3 rail is the main supply for the chip, requiring a clean 3.3V input with a 10-µF capacitor placed close to the pin. The LDO_3V3 rail powers the chip's core and can supply external SPI flash and I2C pull-ups, with a current limit of 25 mA. The LDO_1V8 rail is internally generated from LDO_3V3 for digital circuitry, requiring a 4.7 µF capacitor nearby.

The ADCIN1 pin is used for boot strap initialization. In dead battery conditions, the VBUS pin voltage determines power usage. This pin, along with SPI_MISO, helps select the device configuration from ROM. A potential divider between LDO_3V3 and GND is recommended for configuration selection, with a 1% tolerance for resistors. Avoid connecting ADCIN1 directly to ground or LDO_3V3; use a resistor divider as specified in the datasheet.

External SPI Flash should be powered by LDO_3V3 and operate at 12 MHz or higher. A 0.1-µF capacitor should be placed near the SPI flash supply pin for noise filtering. Pull-up resistors are recommended for CS, MISO, WP, and HOLD lines. Texas Instruments suggests the "W25X05CL" or similar SPI flash for system use.

1.3 I2C Interface

The device features three I2C ports, supporting Master and Slave modes with Fast (400 KHz) and Standard (100 KHz) I2C modes, including burst writing. All I2C lines require pull-up resistors, preferably from the LDO_3V3 rail. Unused I2C ports also need a 10-kΩ pull-up resistor.

The ADCIN2 pin sets the I2C address. A potential divider between LDO_3V3 and GND is used to achieve the desired I2C address. Table 1-2 details the I2C addresses for Port 1 based on the divider ratio.

1.4 HRESET

HRESET is an active-high hardware reset signal that reinitializes all device settings. If not used, the pin should be grounded. If used, pull down to ground with a 100-KΩ resistor and add a 0.01-µF capacitor for noise filtering.

1.5 Configuration Channel / VCONN Lines

Configuration Channel (CC) lines are critical for Type-C and PD communication, handling negotiations between devices. A Type-C/PD port has two CC lines (CC1 and CC2). One CC line is used for communication, while the other can be converted to VCONN to supply 5-V power to cable electronics, supporting up to 600 mA. In captive cable scenarios, the CC line and VCONN are fixed. High-speed signal multiplexing is not required in such cases. Ensure CC lines are directly connected to the Type-C receptacle, avoiding passive components between the PD chip and receptacle. Capacitors on CC lines are used to tune eye-diagram requirements and should be placed close to the PD controller to prevent voltage drop in long traces.

1.6 Battery Charger Detection and Advertisement (BC1.2)

The device has two USB lines that can be used for BC1.2 detection or as standard GPIOs. These pins can be connected to USB 2.0 lines for BC1.2 detection. If not used, they can be assigned to events for BC1.2 detection.

1.7 GPIOs

Multiple GPIOs can be assigned PD events via the configuration tool, supporting various event options and system inputs. Unused GPIOs should be left floating. Some GPIOs have specific features and should be used as per the TPS65987DDH schematic checklist in the Appendix.

1.8 Hot Plug Detect or HPD Line

The HPD line is used for Display Port (DP) communication. The PD controller monitors the Type-C communication for HPD messages from DP devices and adjusts its line state accordingly.

1.9 PP_EXT Power Path Control

Signals GPIO16 and GPIO17 control external power FETs and require a driver FET. These pins are not high-voltage tolerant. PP_EXT pins can function as GPIOs if external FETs are not used.

1.10 Power Path Considerations

Protect the power path from voltage transients exceeding absolute maximum ratings. For external power paths, use components with voltage ratings similar to or better than the PD controller. Reverse current protection (RCP) is highly recommended. A Schottky diode or a Transient Voltage Suppressor (TVS) device (like TVS2200) on the VBUS can absorb GND currents during shorts or disconnects, protecting connected devices. The forward voltage of these components should be as low as possible (e.g., 500 mV or lower for Schottky diodes). When connecting external power supplies, protect against hot-plug transient voltages, which can be double the supply voltage. System design should minimize these transients using input filters, soft-start circuits, or TVS devices. Adequate bulk capacitance is also necessary for PPHV1 and PPHV2 paths. Regulated supplies are best for PPHV1 and PPHV2. For 5V-only systems, a controlled 5V supply can be used. For higher power systems (up to 100W), a variable DC/DC converter with a controlled ramp rate is recommended. Ensure power supplies do not violate the PD controller's absolute maximum voltage ratings. Failure to use power path protection can lead to reliability issues and irreversible system damage.

2.1 Power Domain

The device supports PD power up to 60 W internally and up to 100 W with external FETs. Key guidelines include:

• Use external FETs with larger packages for better heat dissipation, especially during rapid temperature changes.
• Employ wide traces for high-current paths (VBUS, PP_HV, PP_EXT) or power planes for VBUS to ensure low resistance.
• Ensure sufficient space and copper around power devices for heat dissipation.
• Minimize vias in high-current paths; if necessary, use at least one via per 500 mA.
• Use at least 8-mil traces for CC lines to support VCONN supply currents.
• Place decoupling capacitors close to the power supply pins.
• Provide at least eight ground vias beneath the chip, running from the top to the bottom layer for optimal electrical and thermal conductivity.
• For split FET pads, provide at least 6 thermal vias underneath each pad, ensuring they are electrically isolated (NC) and run from top to bottom layer, preferably tented.

2.2 Hi Speed Lines

In USB PD systems, high-speed signals can reach 10 Gbit/s, and up to 40 Gbit/s in Thunderbolt 3 systems. Maintaining signal integrity is crucial at these data rates.

• Place SuperSpeed or Alternate Mode multiplexers close to the Type-C receptacle for direct routing of high-speed lines.
• Avoid placing switching circuits near multiplexers and high-speed signal traces to prevent noise coupling.
• Maintain 90-Ω differential impedance for high-speed signals.
• Separate differential pairs by at least three times their width and ensure uniform layout.
• Match intra-pair trace lengths within 5 mils.
• Avoid sharp bends on high-speed signals; use curved or 45° bends instead of 90° bends.
• When high-speed signal pairs cross on different planes, ensure a ground plane is present between them.
• Maintain continuous grounding when changing layers for high-speed signals to ensure uniform impedance. Place GND vias adjacent to signal vias on high-speed traces.

2.3 Other Considerations

This section covers additional design considerations and best practices:

• Minimize the distance between the Type-C receptacle and the PD Controller's CC pins. Place 220-pF capacitors close to the PD Controller to tune CC signal eye diagrams.
• Place ESD diodes as close as possible to the Type-C receptacle.
• Ensure ESD components are placed without stubs, using a pass-through method on differential paths.
• Position power regulators away from high-speed signals and associated components.

A.1 Dead Battery Considerations

In a dead battery state, system power is unavailable, and the system must operate using VBUS from the source. The TPS65987DDH has a built-in LDO for power-up. Laptops typically require an embedded controller (EC) to manage PD ports according to system requirements. When system power is unavailable, an additional regulator is needed from VBUS or PP_HV/PP_EXT to supply 3.3 V to the EC and other critical components. Two methods are described:

1. Using an LDO from VBUS: This device powers up upon VBUS availability, negotiates an implicit contract, and then powers the LDO, which in turn powers the EC and other components. This method is suitable even when system power is activated by an SRDY command or BUZPOWERZ configuration, ensuring the power path is active only when instructed by the EC.
2. Using an LDO from PP_HV/PP_EXT: This device powers up via its internal LDO, negotiates a contract, and activates power FETs. Once the FETs are active, they power the LDO, which then powers other necessary components.

A.2 TPS65987DDH Schematic Checklist

Table A-1 provides a checklist for TPS65987DDH components and pins, detailing pin names, numbers, descriptions, and recommended values for capacitors and resistors.

A.3 TPS65987DDH System Checklist

Table A-2 presents a system checklist for verifying the design against the TPS65987DDH components and pins checklist.

Revision History

Details changes made across different revisions of the document, including updates to numbering formats, content structure, figures, and tables.