Texas Instruments TPS27081A: 1.2-V to 8-V, 3-A PFET High-Side Load Switch with Level Shift and Adjustable Slew Rate Control

1 Features

Low ON-Resistance, High-Current PFET with RDS(on) values ranging from 32 mΩ at VGS = −4.5 V to 155 mΩ at VGS = −1.2 V.
Adjustable Turnon and Turnoff Slew Rate Control via external R1, R2, and C1 components.
Supports a wide range of 1.2-V to 8-V supply inputs.
Integrated NMOS for PFET control, supporting 1-V to 8-V control logic.
Full ESD Protection on all pins (HBM 2 kV, CDM 500 V).
Ultra-Low Leakage Current in Standby (Typical 100 nA).
Available in a compact 6-pin SOT (DDC) package (2.9 mm × 2.8 mm × 0.75 mm).

2 Applications

High-Side Load Switches
Inrush Current Control
Power Sequencing and Control
Standby Power Isolation
Portable Power Switches

3 Description

The TPS27081A is a high-side load switch integrating a Power PFET and a Control NFET in a small package. It offers industry-standard ESD protection on all pins for enhanced compatibility. The device supports low-voltage (1-V) CPU or MCU logic to control higher voltage power supplies by level-shifting the ON/OFF signal to VIN levels, eliminating the need for an external level-shifter. To manage inrush current when switching large capacitive loads, external resistor R2 and capacitor C1 can be used to control the slew rate. For standby applications, a single pullup resistor R1 is sufficient; R2 can be connected to ground if inrush current control is not required.

Device Information

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS27081A	SOT (6)	2.90 mm × 1.60 mm

Simplified Schematic

The simplified schematic illustrates the TPS27081A's internal structure. It shows VIN (Pin 4) connected to the drain of the PFET (Q1). The source of Q1 is connected to VOUT (Pins 2 and 3). The gate of Q1 (Pin 6) is connected to R1/C1. Pin 1 (R2) is connected to the source of the NFET (Q2). The gate of Q2 (Pin 5) is connected to the ON/OFF control signal. The drain of Q2 is connected to the gate of Q1 (Pin 6). A load (LOAD) is connected to VOUT, with a load capacitor (CL) and slew rate control capacitor (C1) potentially connected between VOUT and the R1/C1 pin.

5 Pin Configuration and Functions

The TPS27081A is available in a 6-pin SOT (DDC) package. The pin functions are:

ON/OFF (Pin 5): Active high enable input. A pulldown resistor to GND is recommended for high-impedance drivers.
R1/C1 (Pin 6): Gate terminal of the power PFET (Q1).
R2 (Pin 1): Source terminal of the NMOS (Q2). Connect to system ground directly or via a slew rate control resistor.
VIN (Pin 4): Source terminal of the power PFET (Q1). A pull-up resistor between VIN and R1/C1 is recommended.
VOUT (Pins 2, 3): Drain terminal of the power PFET (Q1). A slew control capacitor can be connected between VOUT and R1/C1.

6 Specifications

6.1 Absolute Maximum Ratings

Parameter	Condition	Min	Max	Unit
VIN(max)	VIN pin max voltage with reference to pin R2	-0.1	8	V
VOUT(max)	VOUT pin max voltage with reference to pin R2	-0.1	8	V
VON/OFF	ON/OFF in maximum voltage with respect to pin R2	-0.3	8	V
IQ1(on)	Maximum continuous drain current of Q1 at TJ = 105°C		3	A
	Maximum pulsed drain current of Q1 at TJ = 105°C		9.5
PD	Maximum power dissipation at TA = 25°C, TJ = 150°C, R̃JA = 105 °C/W		1190	mW
TA	Operating free-air ambient temperature	-40	85	°C
TJ(max)	Operating virtual junction temperature		150	°C
Tstg	Storage temperature	-65	150	°C

6.2 ESD Ratings

Parameter	Condition	Value	Unit
V(ESD)	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins	±2000	V
	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins	±500	V

6.3 Recommended Operating Conditions

Parameter	Condition	Min	Max	Unit
VIN	Input voltage	1	8	V
TA	Operating free-air ambient temperature	-40	85	°C
TJ	Junction temperature	-40	105	°C

6.4 Thermal Information

Thermal Metric	TPS27081A DDC (SOT) 6 PINS	Unit
R̃JA (Junction-to-ambient thermal resistance)	105	°C/W
R̃JC(top) (Junction-to-case (top) thermal resistance)	43	°C/W
R̃JB (Junction-to-board thermal resistance)	17.8	°C/W
ΨJT (Junction-to-top characterization parameter)	6.5	°C/W
ΨJB (Junction-to-board characterization parameter)	16.2	°C/W
R̃JC(bot) (Junction-to-case (bottom) thermal resistance)	n/a	°C/W

6.5 Electrical Characteristics

Electrical characteristics are specified over the recommended junction temperature range of −40°C to 105°C unless otherwise noted. Typical values are specified at TA = TJ = 25°C.

Parameter	Test Conditions	Min	Typ	Max	Unit
OFF-TIME CHARACTERISTICS
BVIN1 (Q1 drain-to-source breakdown voltage)	VON/OFF = 0 V, VGS(Q1) = 0 V, ID(Q1) = 250 µA	-8			V
ILOAD (VIN pin total leakage current)	VIN = 8 V, VON/OFF = 0 V, RR1 = 10 kΩ		0.15	0.75	µA
ILOAD (VIN pin total leakage current)	VIN = 5 V, VON/OFF = 0 V, RR1 = 10 kΩ		5	20	µA
IFQ2 (Q2 drain-to-source leakage current)	VIN = 8 V, VON/OFF = 0 V		0.05	0.05	µA
IFQ2 (Q2 drain-to-source leakage current)	VIN = 5 V, VON/OFF = 0 V		0.35	0.6	µA
ON-TIME CHARACTERISTICS
VIL (ON/OFF pin low-level input voltage)	VIN = 5 V, ID(Q1) < 2 µA, RR1 = 10 kΩ, RR2 = RL = 0 Ω		0.3		V
VIL (ON/OFF pin low-level input voltage)	VIN = 5 V, ID(Q1) < 20 µA, RR1 = 10 kΩ, RR2 = RL = 0 Ω		0.2		V
VIH (ON/OFF pin high-level input voltage)	VIN = 5 V, RR1 = 10 kΩ		1		V
RQ1(on) (Q1 Channel ON-resistance)	VGS = −4.5 V, ID(Q1) = 3 A		32	55	mΩ
	VGS = −3 V, ID(Q1) = 2.5 A		44	77	mΩ
	VGS = −2.5 V, ID(Q1) = 2.5 A		50	85	mΩ
	VGS = −1.8 V, ID(Q1) = 2 A		82	147	mΩ
	VGS = −1.5 V, ID(Q1) = 1 A		93	166	mΩ
	VGS = −1.2 V, ID(Q1) = 0.5 A		155	260	mΩ
RQ2(on) (Q2 Channel ON-resistance)	VGS = 4.5 V, ID(Q2) = 0.4 A		1.8	3	Ω
	VGS = 3.0 V, ID(Q2) = 0.3 A		2.3	6.2	Ω
	VGS = 2.5 V, ID(Q2) = 0.2 A		2.6	6.1	Ω
	VGS = 1.8 V, ID(Q2) = 0.1 A		3.8	10	Ω
	VGS = 1.5 V, ID(Q2) = 0.05 A		4.4	8.5	Ω
	VGS = 1.2 V, ID(Q2) = 0.03 A		6.25	13.5	Ω
Q1 DRAIN-SOURCE DIODE PARAMETERS
IFSD (Source-drain diode peak forward current)	VFSD = 0.8 V, VON/OFF = 0 V		1		A
VFSD (Source-drain diode forward voltage)	VON/OFF = 0 V, IFSD = -0.6 A		1		V

6.6 Typical Characteristics

Figures 1 through 7 illustrate typical characteristics, showing voltage drop versus load current for various VGS(Q1) conditions (−1.2 V to −7 V) at 25°C and 85°C. Figures 8 through 12 depict the PFET Q1 Minimum Safe Operating Area (SOA) curves, plotting load current versus ambient temperature for different VGS(Q1) values (−4.5 V, −3 V, −2.5 V, −1.8 V, and −1.2 V).

7 Detailed Description

7.1 Overview

The TPS27081A is a load switch designed for up to 8 V and 3 A. It features an ultra-low resistance P-channel MOSFET to minimize voltage drop across low voltage and high current rails. The device offers programmable slew rate control to mitigate power supply droop caused by inrush currents and maintains very low leakage during shutdown.

7.2 Functional Block Diagram

The functional block diagram shows the TPS27081A with its key internal components: VIN (Pin 4), R1/C1 (Pin 6), ON/OFF (Pin 5), VOUT (Pins 2, 3), and R2 (Pin 1), connected to a PFET (Q1) and an NFET (Q2).

7.3 Feature Description

The TPS27081A utilizes a low-voltage PMOS transistor as the main switch. An integrated NMOS transistor controls the PMOS gate, allowing interface with a wide range of GPIO voltages. An input voltage above 1 V (VIH) turns on the PMOS by driving its gate towards ground via the NMOS. External components R1 and R2 are used for slew rate control and turnoff, respectively. R1 acts as a pull-up resistor to ensure proper turnoff, and its value should be chosen to avoid significantly affecting the PMOS gate voltage. Additional pins allow for external passive components to fine-tune the output rise time.

7.4 Device Functional Modes

ON/OFF: The switch turns ON when VIN > 1 V and V(ON/OFF) > 1 V, resulting in VOUT ≈ VIN. The switch turns OFF when VIN > 1 V and V(ON/OFF) < 1 V, resulting in VOUT ≠ VIN.
Fastest Output Rise Time: Achieved by connecting R2 to ground and omitting a capacitor between VOUT and R1/C1.
Controlled Output Rise Time: Achieved by connecting R2 to a resistor (R2) and adding a capacitor (C1) between VOUT and R1/C1. Specific values can be determined using provided equations.

8 Application and Implementation

8.1 Application Information

This section provides design considerations for implementing the TPS27081A in various applications. It is important to note that this information is not part of the TI component specification and customers are responsible for validating their designs.

8.2 Typical Application

8.2.1 Standard Load Switching Application

The TPS27081A serves as a high-side load switch, integrating a PFET and NMOS for up to 8-V supply and 3-A load current. Figure 13 illustrates a typical application for controlling load inrush current.

Figure 13. Standard Application Diagram: Shows VIN connected to Q1's drain, Q1's source to VOUT. R1/C1 is connected to Q1's gate. ON/OFF controls Q2's gate, whose source is connected to R2, and R2 is connected to ground. LOAD is connected to VOUT. CL is shown across the load.

COMPONENT	DESCRIPTION
R1	Level shift and pullup resistor
R2	Optional (for slew rate control)
C1	Optional (for slew rate control)

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Configuring Q1 ON Resistance

The ON-resistance (RQ1(on)) of the PFET (Q1) is set by the gate-to-source voltage (VGS(Q1)). Connecting R2 directly to ground maximizes VGS(Q1), minimizing voltage dropout. The equation VGS(Q1) = -VIN × (RR1 / (RR1 + RR2)) describes VGS(Q1) when R2 controls the turnon slew rate. For example, with RR1 = 10 × RR2 and VIN = 5 V, VGS(Q1) = −4.5 V.

8.2.1.2.2 Configuring Turnon Slew Rate

Switching large capacitive loads (CLOAD) can cause high inrush current. To control this, R2 and C1 are used. The rise time (tRISE) to charge CLOAD from 10% to 90% of VIN is approximated by the formula: tRISE = (3.9 × RR2 × CC1) / (VIN)²⁷⁵. Table 2 provides component values for achieving specific rise times with different VIN values and resistor configurations. It is recommended that R1 > 10 × R2.

8.2.1.2.3 Configuring Turnoff Delay

The PMOS turnoff delay is influenced by R1 and C1. Lower R1 values result in quicker turnoff, with the delay approximated by t_off > 2 × R1 × C1.

8.2.1.2.4 Low Voltage ON/OFF Interface

The ON/OFF pin requires VGS(Q2) > 1.0 V (typical) to turn ON. For reliable operation, the ON/OFF logic should adhere to the VIH(on) > 1.0 V + IQ2 × R2 and VIL(off) < 0.2 V limits. Minimizing the IQ2 × R2 drop allows direct interfacing with low-voltage logic. A high R1/R2 ratio helps reduce this drop. If an ON/OFF signal is unavailable, connecting the ON/OFF pin to VIN enables the device to sync with the input supply. A pulldown resistor is advised for high-impedance (tri-state) drivers.

8.2.1.2.5 ON-Chip Power Dissipation

On-chip power dissipation (PD) can be calculated using PD = IDQ1² × RQ1(on) + IDQ2² × RQ2(on), where IDQ1 and IDQ2 are the DC currents through Q1 and Q2, respectively. Estimating RQ1(on) and RQ2(on) can be done using the Electrical Characteristics or Figures 1-7.

8.2.1.3 Application Curves

Figures 14, 15, and 16 show output rise time and inrush current for different C1 values (330 pF, 3300 pF, and 33 nF) under specific VIN and load conditions.

8.3 System Examples

8.3.1 Standby Power Isolation

The TPS27081A facilitates standby power generation for always-ON modules. A single pull-up resistor is sufficient. Figure 17 shows a configuration where VOUT rise time is approximately 250 ns at VIN = 5 V.

Figure 17. Standby Power Generation Using TPS27081A: Depicts VIN, CIN, R1, R1/C1, ON/OFF, Q1, Q2, R2, VOUT, COUT, and a Standby Module. VDD is shown for the module.

8.3.2 Boost Regulator With True Shutdown

The TPS27081A can prevent leakage current in boost regulator topologies by being placed in the input path, ensuring a true shutdown. This is particularly useful for LCD panels requiring inrush current control.

Figure 18. True Shutdown Using TPS27081A: Shows an input supply connected to VIN, then through Q1, R1, R1/C1, ON/OFF, Q2, R2 to a Boost Regulator's SHDN pin. VOUT is from the Boost Regulator's output.

8.3.3 Single Module Multiple Power Supply Sequencing

For modern SOCs and CPUs requiring sequential power-up, the TPS27081A can adjust VOUT1 rise time using R2 and C1 to synchronize with other supplies like DC-DC converters, enabling proper power sequencing.

Figure 19. Power Sequencing Using TPS27081A: Illustrates a SW Supply (DC-DC) connected to VIN, then through Q1, R1, R1/C1, ON/OFF, Q2, R2 to VOUT1. CVDD, VDDIO, DVDD, VDD are shown for a CPU/MCU/SOC.

8.3.4 Multiple Modules Interdependent Power Supply Sequencing

This configuration enables Module 2 to power up only after Module 1 is active and its GPIO output enables Module 2. The TPS27081A controls Module 2's power and manages inrush current for both modules.

Figure 20. Power Sequencing Using TPS27081A: Shows two cascaded TPS27081A circuits. Module 1 has VIN, R1, R1/C1, ON/OFF, Q1, Q2, R2, VOUT1. Module 2 has VIN, R3, R1/C1, ON/OFF, Q1, Q2, R2, R4, VOUT2.

8.3.5 TFT LCD Module Inrush Current Control

The TPS27081A is used to control inrush current for TFT LCD modules, preventing damage during power transitions.

Figure 21. Inrush Current Control Using TPS27081A: Depicts a 3-5V Input connected to VIN, then through Q1, R1, R1/C1, ON/OFF, Q2, R2 to VOUT, which is connected to a TFT LCD Module. COUT is shown across the module.

8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input

When a GPIO signal is not available, the ON/OFF pin can be connected to VIN. This setup allows Module 2 to power up after Module 1, with R4 and C1 values determining the sequence and controlling inrush current.

Figure 22. Power Sequencing Using TPS27081A: Shows two cascaded TPS27081A circuits. Module 1 has VIN, R1, R1/C1, ON/OFF, Q1, Q2, R2, VOUT1. Module 2 has VIN, R3, R1/C1, ON/OFF, Q1, Q2, R2, R4, VOUT2.

9 Power Supply Recommendations

The TPS27081A operates from a VIN range of 1 V to 8 V. The supply should be well-regulated and placed close to the device, with a recommended 1-µF bypass capacitor. For supplies located further away, additional bulk capacitance (e.g., 1-µF electrolytic, tantalum, or ceramic) may be necessary.

10 Layout

10.1 Layout Guidelines

Use good PCB layout practices for optimal performance.
Keep VIN and VOUT traces short and wide to handle high currents.
Bypass the VIN pin to ground with low ESR ceramic capacitors (e.g., 1-µF ceramic with X5R or X7R dielectric), placed close to the pin.
Bypass the VOUT pin to ground with low ESR ceramic capacitors (e.g., 0.1-µF ceramic), placed close to the pin.

10.2 Layout Example

Figure 23. Layout Example: Illustrates the recommended PCB layout, showing placement of VIN, VOUT, ON/OFF pins, R1, R2, C1, and bypass capacitors, along with connections to a ground plane.

10.3 Thermal Reliability

For enhanced reliability, TI recommends keeping the junction temperature below 105°C. The maximum ON-chip power dissipation (PDMAX) can be calculated using the formula: PDMAX = (TJ(max) - TA) / R̃JA, where TJ(max) is the target junction temperature, TA is the ambient temperature, and R̃JA is the junction-to-ambient thermal resistance.

10.4 Improving Package Thermal Performance

The R̃JA value depends on PCB layout. Using an external heat sink or cooling mechanism can reduce R̃JA and improve thermal performance. Refer to TI's design support for guidance.

11 Device and Documentation Support

11.1 Community Resources

TI provides community resources via the TI E2E™ Online Community (e2e.ti.com) for technical support, questions, and knowledge sharing. Design Support links offer access to forums, tools, and contact information.

11.2 Trademarks

E2E is a trademark of Texas Instruments. Other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

Devices have limited built-in ESD protection. Handle with care, shorting leads or using conductive foam during storage to prevent damage.

11.4 Glossary

Refer to the TI Glossary (SLYZ022) for definitions of terms, acronyms, and abbreviations.

12 Mechanical, Packaging, and Orderable Information

This section provides details on mechanical dimensions, packaging options, and orderable parts. Information is subject to change without notice.

Packaging Information: The TPS27081ADDCR is available in the SOT-23-THIN DDC package, is RoHS & Green compliant, and operates from -40°C to 85°C. It has a Moisture Sensitivity Level (MSL) of Level 1.

Tape and Reel Information: Details dimensions for tape and reel packaging, including reel diameter, width, and component placement within the tape.

Package Outline: Provides detailed mechanical drawings of the SOT-23-THIN DDC package, including pinout and dimensions.

Example Board Layout & Stencil Design: Offers guidance on PCB land pattern and stencil design for the DDC0006A package.

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