Texas Instruments bq24133EVM User's Guide

1 Introduction

1.1 EVM Features

• Evaluation module for bq24133
• Stand-alone synchronous switch-mode, battery-charge controller
• Integrated N-MOSFETs and power path selector
• CELL pin setting up to 12.6-V battery voltage; 1, 2, or 3 cells with 4.2 V/cell
• Input operating range: 4.5 V–16 V
• LED indication for charge status
• Test points for key signals available for testing purposes; easy probe hook-up.
• Jumpers available; easy-to-change setting

1.2 General Description

The bq24133 is a highly integrated stand-alone Li-ion and Li-polymer switch-mode battery charge controller with two integrated N-channel power MOSFETs and a power path selector gate driver. It offers a constant-frequency synchronous PWM controller with high accuracy regulation of input current, charge current, and voltage. It also provides battery detection, pre-conditioning, charge termination, and charge status monitoring.

The bq24133 automatically enters a low-quiescent current sleep mode when the input voltage falls below the battery voltage. The bq24133 charges one, two, or three cells (selected by CELL pin), supporting up to a 2.5-A charge current. The bq24133 is available in a 24-pin, 3.5 x 5.5 mm², thin QFN package.

For details, see the bq24133 data sheet (SLUSAF7).

1.3 I/O Description

1.4 Control and Key Parameters Settings

1.5 Recommended Operating Conditions

The bq2410 EVM board requires a regulated supply approximately 1 V minimum above the regulated voltage of the battery pack to a maximum input voltage of 16 Vdc. The bq24133 uses the CELL pin to select the number of cells with a fixed 4.2 V/cell. Connecting CELL to AGND gives a 1-cell configuration, a floating CELL pin gives a 2-cell configuration, and connecting to VREF gives a 3-cell configuration. The CELL pin adjusts the internal resistor voltage divider from the BAT pin to AGND pin for voltage feedback and regulate to internal 2.1-V voltage reference.

For Note 001, the BAT voltage is set to 4.2 V and for Note 002, the BAT voltage is set to 12.6 V.

The ISET input sets the maximum charging current. Battery current is sensed by current sensing resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 40 mV maximum. The equation for charge current is:

ICHARGE = VISET / (20 × R15) (1)

For bq24133, the precharge current is set as 1/10 of the fast-charge rate set by ISET voltage, according to the formula:

IPRECHARGE = VISET / (200 × R15) (2)

The default setting is 2 Adc for fast-charge current and 0.2 Adc for precharge current.

In the bq24133, once the voltage on OVPSET is above the 1.6-V ACOV threshold or below the 0.5-V ACUV threshold, the charge is disabled, and the battery is switched to the system instead of the adapter.

VACUV = 0.5 V × (1 + R6 / R9) (3)

For Note 001, ACUV = 2.51 V; for Note 002, ACUV = 5.87 V.

VACOV = 1.6 V × (1 + R6 / R9) (4)

For Note 001, ACOV = 8.03 V; for Note 002, ACOV = 18.80 V.

Similar to setting battery regulation current, the adapter current is set by the voltage on ACSET pin using the following equation:

IDPM = VACSET / (20 × R2) (5)

The default setting on the EVM is 3 Adc for adapter current regulation.

2 Test Summary

2.1 Definitions

This procedure details how to configure the HPA715A evaluation board. The following naming conventions are followed in the test procedure:

• VXXX: External voltage supply name (VIN, VBAT, VTS)
• LOADW: External load name (LOADR, LOADI)
• V(TPyyy): Voltage at internal test point TPyyy. For example, V(TP1) means the voltage at TP1.
• V(Jxx): Voltage at jack terminal Jxx.
• V(TP(XXX)): Voltage at test point XXX. For example, V(ACSET) means the voltage at the test point which is marked as ACSET.
• V(XXX, YYY): Voltage across point XXX and YYY.
• I(JXX(YYY)): Current going out from the YYY terminal of jack XX.
• Jxx(BBB): Terminal or pin BBB of jack xx
• Jxx ON: Internal jumper Jxx terminals are shorted
• Jxx OFF: Internal jumper Jxx terminals are open
• Jxx (-YY-) ON: Internal jumper Jxx adjacent terminals marked as YY are shorted
• Measure:A,B Check specified parameters A, B. If measured values are not within specified limits, the unit under test has failed.
• Observe: →A,B Observe if A, B occur. If they do not occur, the unit under test has failed.

Assembly drawings have locations for jumpers, test points, and individual components.

2.2 Safety

1. Safety Glasses are to be worn.
2. This test must be performed by qualified personnel who are trained in electronics theory and understand the risks and hazards of the assembly to be tested.
3. ESD precautions must be followed while handling electronic assemblies and performing this test.
4. Precautions must be observed to avoid touching areas of the assembly that may get hot or present a shock hazard during testing.

2.3 Quality

1. Test data can be made available on request from Texas Instruments.

2.4 Safety Apparel

1. Electrostatic smock
2. Electrostatic gloves or finger cots
3. Safety glasses
4. Ground ESD wrist strap.

2.5 Equipment

2.5.1 Power Supplies

Power Supply #1 (PS#1): a power supply capable of supplying 30 V at 5 A is required.

2.5.2 Loads

• LOAD#1: A 30-V (or greater), 5-A (or greater) electronic load that can operate at constant current and constant voltage mode.
• LOAD#2: An HP 6060B 3-V to 60-V/0-A to 60-A, 300-W system dc electronic load or equivalent.

2.5.3 Meters

Seven Fluke 75 multimeters (equivalent or better) or four equivalent voltage meters and three equivalent current meters. The current meters must be capable of measuring 5-A+ current.

2.6 Equipment Setup

1. Set the Power Supply #1 (PS#1) for 6-V ±200-mVdc (001), or 16-V ±0.200-mV (002), 4.5-A ±0.1-A current limit, and then turn off supply.
2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VIN, PGND).
3. Connect a voltage meter across J1 (VIN, PGND).
4. Connect Load#1 in series with a current meter to J2 (VBAT, PGND). Turn off Load#1.
5. Connect Load#2 in series with a current meter to J2 (VSYS, PGND). Turn off Load#2.
6. Connect a voltage meter across J2 (VBAT, PGND).
7. Connect a voltage meter across J2 (VSYS, PGND).
8. Check all jumper shunts. JP1: connect 2-3 (External TS); JP2: ON; JP3: OPEN; JP4: OPEN. JP5: connect 1-2 for 001 and connect 2-3 for 002.

2.7 Procedure

Disconnect the load and power supply. Use diode-function of multimeter to check the resistance between J1-VIN and J2-VSYS. Pass only if both OPEN for bi-direction (positive J1-VIN and negative on J2-VSYS; negative J1-VIN and positive on J2-VSYS).

2.7.1 Power Supply and VREF

Make sure that Section 2.6 steps are followed. Disconnect LOAD#1#2. Turn on PS#1 (6 V for 001 and 16 V for 002).

• Measure → V(J2(VSYS)) = 6 V ±500 mV (001)
• Measure → V(J2(VSYS)) = 16 V ±500 mV (002)
• Measure → V(J2(VBAT)) = 0.5 V ±500 mV
• Measure → V(TP(VREF)) = 3.3 V ±200 mV
• Measure → V(TP(REGN)) = 0.5 V ±500 mV

2.7.2 Charger Enable and Battery Detection

Connect 2-3 of JP1 (Internal TS); short JP4 (Charger Enable)

• Measure → V(TP(VREF)) = 3.3 V ±200 mV
• Measure → V(TP(REGN)) = 6 V ±200 mV
• Observe → V(J2(VBAT)) = 4.2 V ±200 mV (001)
• Observe → V(J2(VBAT)) = 12.6 V ±200 mV (002)
• Observe → D1 (/STAT) BLINK

2.7.3 Charge Current/Voltage Regulation and Battery Temperature Qualification

Reconnect LOAD#2, and turn on. Use the constant voltage mode. Set the output voltage to 2.5 V for 001 and 8 V for 002.

• Measure → I(J2(VBAT)) = 0.2 A ±100 mA
• Observe → D1 (/STAT) ON

Increase the voltage of LOAD#2 to 3.5 V for 001 and 10.5 V for 002.

• Measure → I(J2(VBAT)) = 2 A ±200 mA
• Observe → D1 (/STAT) ON

Open 2-3 of JP1 (External TS)

• Measure → I(J2(VBAT)) = 0 A ±100 mA
• Observe → D1 (/STAT) BLINK

Connect 2-3 of JP1 (Internal TS)

• Measure → I(J2(VBAT)) = 2 A ±200 mA
• Observe → D1 (/STAT) ON

2.7.4 Charger Termination and Recharge

Increase the voltage of LOAD#2 slowly to approximately 4.2 V for Note 001 and 12.6 V for Note 002.

• Observe → I(J2(VBAT)) decreases from 2 A while V(J2(VBAT)) becomes constant.
• Observe → I(J2(VBAT)) drops to zero when LOAD#2 current is less than 0.2 A.

Decrease the voltage of LOAD#2 slowly to approximately 3.5 V for Note 001 and 10.5 V for Note 002.

• Measure → I(J2(VBAT)) = 2 A ±200 mA.
• Observe → D1 (/STAT) ON.

2.7.5 OVP - Input Overvoltage Protection

Increase the voltage of PS#1 to 9 V for Note 001 or 20 V for Note 002.

• Measure → I(J1(VIN)) = 0 A ±200 mA.
• Observe → D1 (/STAT) BLINK.

2.7.6 DPM - Input Current Regulation

Connect the output of the Load#1 in series with a current meter (multimeter) to J2 (SYS, PGND). Ensure that a voltage meter is connected across J2 (SYS, PGND). Resume other status as in Section 2.7.3. Turn on the power of Load#1. Set the load current to 0.5 A. Increase the load current until I(J1(VIN)) = 3 A.

• Observe → I(J2(VBAT)) decreases from 3 A to 0 A and I(J1(VIN)) keeps 3 A unchanged.

2.7.7 Test Complete

Turn off the power supply, and remove all connections from the unit under test (UUT).

3 PCB Layout Guideline

1. It is critical that the exposed thermal pad on the backside of the bq24133 package be soldered to the PCB ground. Ensure that sufficient thermal vias are right underneath the IC, connecting to the ground plane on the other layers.
2. The control stage and the power stage must be routed separately. At each layer, the signal ground and the power ground are connected only at the thermal pad.
3. Charge current sense resistor must be connected to SRP and SRN with a Kelvin contact. The area of this loop must be minimized. The decoupling capacitors for these pins must be placed as close to the IC as possible.
4. Input current sense resistor must be connected to ACP, ACN with a Kelvin contact. The area of this loop must be minimized. The decoupling capacitors for these pins should be placed as close to the IC as possible.
5. Decoupling capacitors for VREF, AVCC, and REGN must make the interconnections to the IC as short as possible.
6. Decoupling capacitors for BAT must be placed close to the corresponding IC pins, and make the interconnections to the IC as short as possible.
7. Decoupling capacitor(s) for the charger input must be placed close to SW and PGND.
8. Take the EVM layout for design reference.

4 Bill of Materials, Board Layout, and Schematic

4.1 Bill of Materials

Notes:

1. These assemblies are ESD sensitive, ESD precautions shall be observed.
2. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Install label after final wash. Text shall be 8 pt font. Text shall be per Table 1.

4.2 Board Layout

4.3 Schematic

Important Notices

Evaluation Board/Kit Important Notice

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.

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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.

EVM Warnings and Restrictions

It is important to operate this EVM within the input voltage range of 0 V to 20 V and the output voltage range of 0 V to 12.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than 85° C. The EVM is designed to operate properly with certain components above 85° C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch.

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