Features
- Equalizes up to 24 dB loss at 10 Gbps
- Equalizes up to 22 dB loss at 6.4 Gbps
- 8 levels of programmable equalization
- Operates up to 10 Gbps with 30" FR4 traces
- Operates up to 6.4 Gbps with 40" FR4 traces
- 0.175 UI residual deterministic jitter at 6.4 Gbps with 40" FR4 traces
- Single 2.5V or 3.3V power supply
- Supports AC or DC-Coupling with wide input common-mode
- Low power consumption: 100 mW Typ at 2.5V
- Small 3 mm x 4 mm 14-pin WSON package
- > 8 kV HBM ESD Rating
- -40 to 85°C operating temperature range
Description
The DS64EV100 programmable equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter for NRZ data channels. The DS64EV100 is optimized for operation up to 10 Gbps for both cables and FR4 traces. The equalizer channel has eight levels of input equalization that can be programmed by three control pins.
The equalizer supports both AC and DC-coupled data paths for long run length data patterns such as PRBS-31, and balanced codes such as 8b/10b. The device uses differential current-mode logic (CML) inputs and outputs. The DS64EV100 is available in a 3 mm x 4 mm 14-pin leadless WSON package. Power is supplied from either a 2.5V or 3.3V supply.
Simplified Application Diagram
A diagram showing a typical application. A transmit (Tx) signal from an ASIC/FPGA High Speed I/O connects to the input of the DS64EV100. The output of the DS64EV100 connects to a Switch Fabric Card Line Card, which then connects to a Backplane/Cable Sub-system. A similar path is shown for another Tx/Rx pair.
Pin Configuration
Pin Diagram
A top view diagram of the 14-pin WSON package, illustrating the pin numbering from 1 to 14. Pin 1 is marked with an index area. The exposed pad (DAP) is connected to GND.
Pin Descriptions
| Pin Name | Pin # | I/O, Type | Description |
|---|---|---|---|
| HIGH SPEED DIFFERENTIAL I/O | |||
| IN+ | 3 | I, CML | Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating resistor is connected between IN+ and IN-. Refer to Figure 4. |
| IN- | 4 | I, CML | |
| OUT+ | 12 | O, CML | Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω terminating resistor connects OUT+ to VDD and OUT- to VDD. |
| OUT- | 11 | O, CML | |
| EQUALIZATION CONTROL | |||
| BST_2 | 14 | I, CMOS | BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1 and BST_0 are internally pulled low. |
| BST_1 | 7 | I, CMOS | |
| BST_0 | 8 | I, CMOS | |
| POWER | |||
| VDD | 5 | I, Power | VDD = 2.5V ±5% or 3.3V ±10%. VDD pins should be tied to VDD plane through low inductance path. A 0.01µF bypass capacitor should be connected between each VDD pin to GND planes. |
| GND | 2, 6, 9, 10, 13 | I, Power | Ground reference. GND should be tied to a solid ground plane through a low impedance path. |
| DAP | PAD | I, Power | Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board. |
| OTHER | |||
| NC | 1 | Reserved. Do not connect. | |
ESD Protection Note: These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Electrical Specifications
Absolute Maximum Ratings
| Parameter | Value |
|---|---|
| Supply Voltage (VDD) | -0.5V to +4V |
| CMOS Input Voltage | -0.5V to +4.0V |
| CMOS Output Voltage | -0.5V to +4.0V |
| CML Input/Output Voltage | -0.5V to +4.0V |
| Junction Temperature | +150°C |
| Storage Temperature | -65°C to +150°C |
| Lead Temperature Soldering, 4 sec | +260°C |
| ESD Rating HBM, 1.5 kΩ, 100 pF | > 8 kV |
| EIAJ, 0Ω, 200 pF | > 250 V |
| Thermal Resistance, θJA, No Airflow | 40 °C/W |
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.
Note 2: If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications.
Recommended Operating Conditions
| Parameter | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| Supply Voltage(1) | ||||
| VDD2.5 to GND | 2.375 | 2.5 | 2.625 | V |
| VDD3.3 to GND | 3.0 | 3.3 | 3.6 | V |
| Ambient Temperature | -40 | 25 | +85 | °C |
(1) The VDD2.5 is VDD = 2.5V ± 5% and VDD3.3 is VDD = 3.3V ± 10%.
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified. (1) (2)
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT |
|---|---|---|---|---|---|
| POWER | |||||
| P Power Supply Consumption | VDD3.3 VDD2.5 | 140 100 | 200 150 | mW mW | |
| N Supply Noise Tolerance(3) | 50 Hz – 100 Hz 100 Hz – 10 MHz 10 MHz – 1.6 GHz | 100 40 10 | mVp-p mVp-p mVp-p | ||
| LVTTL DC SPECIFICATIONS | |||||
| VIH High Level Input Voltage | VDD2.5 | 1.6 | V | ||
| VIL Low Level Input Voltage | VIL | 2.0 | V | ||
| VOH High Level Input Voltage | IOH = -3 mA, VDD3.3 | 3 | V | ||
| VOL Low Level Input Voltage | IOL = 3 mA | 0.8 | V | ||
(1) Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed.
(2) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
(3) Allowed supply noise (mVp-p sine wave) under typical conditions.
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER | ||||||
| IIN Input Current | VIN = VDD VIN = GND | +1.8 0 | +15 | µA µA | ||
| IIN-P Input Leakage Current with Internal Pull-Down/Up Resistors | VIN = GND, with internal pull-down resistors | +95 | µA | |||
| VIN = GND, with internal pull-up resistors | -15 | µA | ||||
| CML RECEIVER INPUTS (IN+, IN-) | ||||||
| VTX Source Transmit Launch Signal Level (IN diff) | AC-Coupled or DC-Coupled Requirement, Differential measurement at point A. Figure 1 | 400 | 1600 | mVp-p | ||
| VINTRE Input Threshold Voltage | Differential measurement at point B . Figure 1 | 120 | mVp-p | |||
| VDDTX Supply Voltage of Transmitter to EQ | DC-Coupled Requirement | 1.6 | VDD | V | ||
| VICMDC Input Common-Mode Voltage | DC-Coupled Requirement Differential measurement at point A. Figure 1 (4) | VDDx-0.8 | VDDx-0.2 | V | ||
| RLI Differential Input Return Loss | 100 MHz – 3.2 GHz, with fixture's effect de-embedded | 10 | dB | |||
| RIN Input Resistance | Differential Across IN+ and IN-. Figure 4 | 85 | 100 | 115 | Ω | |
| CML OUTPUTS (OUT+, OUT-) | ||||||
| VOD Output Differential Voltage Level (OUT diff) | Differential measurement with OUT+ and OUT- terminated by 50Ω to GND, AC-Coupled Figure 2 | 550 | 620 | 725 mVp-p | ||
| VOCM Output Common-Mode Voltage | Single-ended measurement DC-Coupled with 50Ω terminations (5) | VDD-0.2 | VDD-0.1 | V | ||
| tR, tF Transition Time | 20% to 80% of differential output voltage, measured within 1" from output pins. Figure 2 (5) | 20 | 60 | ps | ||
| RO Output Resistance | Single-ended to VDD | 42 | 50 | 58 | Ω | |
| RLO Differential Output Return Loss | 100 MHz – 1.6 GHz, with fixture's effect de-embedded. IN+ = static high. | 10 | dB | |||
| tPLHD Differential Low to High Propagation Delay | Propagation delay measurement at 50% VOD between input to output, 100 Mbps Figure 3 (5) | 240 | ps | |||
| tPHLD Differential High to Low Propagation Delay | 240 | ps | ||||
| EQUALIZATION | ||||||
| DJ1 Residual Deterministic Jitter at 10 Gbps | 30" of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7 (27-1) pattern (6) (7) | 0.20 | Ulp-p | |||
| DJ2 Residual Deterministic Jitter at 6.4 Gbps | 40" of 6 mil microstrip FR4, EQ Setting 0x06, PRBS-7 (27-1) pattern (6) (7) | 0.17 | 0.26 | Ulp-p | ||
| DJ3 Residual Deterministic Jitter at 5 Gbps | 40" of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7 (27-1) pattern (6) (7) | 0.12 | 0.20 | Ulp-p | ||
| DJ4 Residual Deterministic Jitter at 2.5 Gbps | 40" of 6 mil microstrip FR4, EQ Setting 0x07, PRBS-7 (27-1) pattern (6) (7) | 0.10 | 0.16 | Ulp-p | ||
(4) Measured with clock-like {11111 00000} pattern.
(5) Measured with clock-like {1111100000} pattern.
(6) Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
(7) Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Random jitter is removed through the use of averaging or similar means.
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT |
|---|---|---|---|---|---|
| POWER | |||||
| RJ Random Jitter (5) (8) | 0.5 | psrms | |||
(8) Random jitter contributed by the equalizer is defined as sqrt (JOUT² – JIN²). JOUT is the random jitter at equalizer outputs in psrms, see point C of Figure 1; JIN is the random jitter at the input of the equalizer in psrms, see Figure 1.
Timing Diagrams
Test Setup Diagram
A block diagram illustrating the test setup. It shows a Signal Source connected via an SMA Connector to a 6-mil trace width FR4 Microstrip Test Channel, which then connects via another SMA Connector to the INPUT of the DS64EV100. The OUTPUT of the DS64EV100 is also shown.
CML Output Transition Times
A timing diagram showing the differential output voltage (OUT diff) transitioning between high and low states, illustrating rise time (tR) and fall time (tF).
Propagation Delay Timing Diagram
A timing diagram showing the input differential signal (IN diff) and the output differential signal (OUT diff), illustrating the propagation delay from low to high (tPLHD) and high to low (tPHLD).
Applications Information
Simplified Receiver Input Termination Circuit
A schematic showing the input termination circuit for the DS64EV100, with IN+ and IN- differential inputs connected through resistors to VDD and ground, leading to the equalizer (EQ).
Simplified Block Diagram
A block diagram of the DS64EV100 internal structure. It shows Input Termination, Equalizer, DC Offset Correction, and Limiting Amplifier blocks. Boost control pins (BST_0: BST_2) are shown controlling the Equalizer. The output is CML OUT+ and OUT-.
Equalizer Boost Control
The equalizer channel supports eight programmable levels of equalization boost, and is controlled by the Boost Set pins (BST_[2:0]) in accordance with Table 2. The eight levels of boost settings enables the DS64EV100 to address a wide range of media loss and data rates.
EQ Boost Control Table
| 6 mil Microstrip FR4 Trace Length (in) | 24 AWG Twin-AX Cable Length (m) | Channel Loss at 3.2 GHz (db) | Channel Loss at 5 GHz (dB) | BST_N [2, 1, 0] |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 000 |
| 5 | 2 | 5 | 6 | 001 |
| 10 | 3 | 7.5 | 10 | 010 |
| 15 | 4 | 10 | 14 | 011 |
| 20 | 5 | 12.5 | 18 | 100 (Default) |
| 25 | 6 | 15 | 21 | 101 |
| 30 | 7 | 17 | 24 | 110 |
| 40 | 10 | 22 | 30 | 111 |
Design Considerations
General Recommendations
The DS64EV100 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the LVDS Owner's Manual for more detailed information on high-speed design tips to address signal integrity design issues.
PCB Layout Considerations for Differential Pairs
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit board. See AN-1187 for additional information on WSON packages.
Power Supply Bypassing
Two approaches are recommended to ensure that the DS64EV100 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.01µF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the DS64EV100. Smaller body size capacitors can help facilitate proper component placement. Additionally, three capacitors with capacitance in the range of 2.2 µF to 10 µF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as possible to the DS64EV100.
DC Coupling
The DS64EV100 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream driver, or downstream receiver. With DC coupling, users must ensure the input signal common mode is within the range of the electrical specification VICMDC and the device output is terminated with 50 Ω to VDD.
Typical Performance Eye Diagrams and Curves
Eye Diagrams
These figures display eye diagrams illustrating the performance of the DS64EV100 under various conditions, including different trace lengths (FR4, Twin-AX Cable, Backplane), data rates (2.5 Gbps, 5 Gbps, 6.4 Gbps, 10 Gbps), and equalization settings (e.g., PRBS7, 0x07 Setting).
- Figure 7: Equalized Signal (40 in FR4, 2.5 Gbps, PRBS7, 0x07 Setting)
- Figure 8: Equalized Signal (40 in FR4, 5 Gbps, PRBS7, 0x07 Setting)
- Figure 9: Equalized Signal (40 in FR4, 6.4 Gbps, PRBS7, 0x06 Setting)
- Figure 10: Equalized Signal (40 in FR4, 6.4 Gbps, PRBS31, 0x06 Setting)
- Figure 11: Equalized Signal (30 in FR4, 10 Gbps, PRBS7, 0x06 Setting)
- Figure 12: Equalized Signal (10m 24 AWG Twin-AX Cable, 6.4 Gbps, PRBS7, 0x06 Setting)
- Figure 13: Equalized Signal (32 in Tyco XAUI Backplane, 6.25 Gbps, PRBS7, 0x06 Setting)
DJ vs. EQ Setting Graphs
These graphs plot Deterministic Jitter (DJ) in Unit Intervals (UI) against the Equalization Setting (BST_2, BST_1, BST_0) for different trace lengths (6 in, 10 in, 20 in, 30 in, 40 in) at 6.4 Gbps (Figure 14) and 10 Gbps (Figure 15).
- Figure 14: DJ vs. EQ Setting (6.4 Gbps)
- Figure 15: DJ vs. EQ Setting (10 Gbps)
Revision History
Changes from Revision D (February 2013) to Revision E:
- Changed layout of National Data Sheet to TI format (Page 9).
Packaging Information
Package Option Addendum
Orderable Device: DS64EV100SD/NOPB
| Status | Package Type | Package Drawing | Pins | Package Qty | Eco Plan | Lead/Ball Finish | MSL Peak Temp | Op Temp (°C) | Device Marking | Samples |
|---|---|---|---|---|---|---|---|---|---|---|
| LIFEBUY | WSON | NHK | 14 | 1000 | Green (RoHS & no Sb/Br) | CU SN | Level-1-260C-UNLIM | -40 to 85 | D64E1SD |
Marketing Status Definitions: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. PREVIEW: Device has been announced but is not in production. OBSOLETE: TI has discontinued the production of the device.
RoHS Definition: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. "Green" means content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold.
MSL, Peak Temp: The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Device Marking: May include logo, lot trace code, or environmental category.
Lead/Ball Finish: Orderable Devices may have multiple material finish options.
Tape and Reel Information
Tape Dimensions
All dimensions are nominal.
| Device | Package Type | Package Drawing | Pins | SPQ | Reel Diameter (mm) | Reel Width W1 (mm) | A0 (mm) | B0 (mm) | K0 (mm) | P1 (mm) | W (mm) | Pin1 Quadrant |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DS64EV100SD/NOPB | WSON | NHK | 14 | 1000 | 178.0 | 12.4 | 3.3 | 4.3 | 1.0 | 8.0 | 12.0 | Q1 |
Tape and Reel Box Dimensions
All dimensions are nominal.
| Device | Package Type | Package Drawing | Pins | SPQ | Length (mm) | Width (mm) | Height (mm) |
|---|---|---|---|---|---|---|---|
| DS64EV100SD/NOPB | WSON | NHK | 14 | 1000 | 210.0 | 185.0 | 35.0 |
Mechanical Data
NHK0014A Package
Dimensions are in millimeters. Dimensions in ( ) are for reference only.
Recommended Land Pattern: A diagram showing the recommended land pattern for the WSON package, with pin 1 index area indicated.
Package Outline: A side view and top view of the WSON package, showing dimensions and pin layout. Pin 1 ID is marked.
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