onsemi MM74HC00 Quad 2-Input NAND Gate
Document Number: MM74HC00/D
Website: www.onsemi.com
General Description
The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
- Typical Propagation Delay: 8 ns
- Wide Power Supply Range: 2 V–6 V
- Low Quiescent Current: 20 μΑ Maximum (74HC Series)
- Low Input Current: 1 μΑ Maximum
- Fanout of 10 LS-TTL Loads
- This Device is Pb-Free and Halide Free
Absolute Maximum Ratings
| Symbol | Parameter | Rating | Unit |
|---|---|---|---|
| VCC | Supply Voltage | -0.5 to +6.5 | V |
| VIN | DC Input Voltage | -0.5 to VCC +0.5 | V |
| VOUT | DC Output Voltage | -0.5 to VCC +0.5 | V |
| IIK, IOK | Clamp Diode Current | +20 | mA |
| IOUT | DC Output Current, per pin | +25 | mA |
| ICC | DC VCC or GND Current, per pin | +50 | mA |
| TSTG | Storage Temperature Range | -65 to +150 | °C |
| PD | Power Dissipation SOIC TSSOP | 1077 833 | mW |
| TL | Lead Temperature (Soldering 10 seconds) | 260 | °C |
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
Recommended Operating Conditions
| Symbol | Parameter | Min | Max | Unit |
|---|---|---|---|---|
| VCC | Supply Voltage | 2 | 6 | V |
| VIN, VOUT | DC Input or Output Voltage | 0 | VCC | V |
| TA | Operating Temperature Range | -40 | +85 | °C |
| tr, tf | Input Rise or Fall Times | VCC = 2.0 V | 1000 | ns |
| VCC = 4.5 V | 500 | |||
| VCC = 6.0 V | 400 |
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.
DC Electrical Characteristics
(Note 2)
| Symbol | Parameter | VCC (V) | Conditions | Guaranteed Limits | Unit | |||
|---|---|---|---|---|---|---|---|---|
| TA = 25°C Typ. | TA = -40°C to 85°C | TA = -55°C to 125°C | ||||||
| VIH | Minimum HIGH Level Input Voltage | 2.0 | 1.5 | 1.5 | 1.5 | V | ||
| 4.5 | 3.15 | 3.15 | 3.15 | |||||
| 6.0 | 4.2 | 4.2 | 4.2 | |||||
| VIL | Maximum LOW Level Input Voltage | 2.0 | 0.5 | 0.5 | 0.5 | V | ||
| 4.5 | 1.35 | 1.35 | 1.35 | |||||
| 6.0 | 1.8 | 1.8 | 1.8 | |||||
| VOH | Minimum HIGH Level Output Voltage | 2.0 | VIN = VIH or VIL, IOUT ≤ 20 μΑ |
2.0 | 1.9 | 1.9 | 1.9 | V |
| 4.5 | 4.5 | 4.4 | 4.4 | 4.4 | ||||
| 6.0 | 6.0 | 5.9 | 5.9 | 5.9 | ||||
| VOL | Maximum LOW Level Output Voltage | 4.5 | VIN = VIH or VIL, IOUT ≤ 4.0 mA |
4.2 | 3.98 | 3.84 | 3.7 | V |
| 6.0 | 5.7 | 5.48 | 5.34 | 5.2 | ||||
| 2.0 | VIN = VIH or VIL, IOUT ≤ 20 μΑ |
0 | 0.1 | 0.1 | 0.1 | V | ||
| 4.5 | 0 | 0.1 | 0.1 | 0.1 | ||||
| 6.0 | 0 | 0.1 | 0.1 | 0.1 | ||||
| 4.5 | VIN = VIH or VIL, IOUT ≤ 4.0 mA |
0.2 | 0.26 | 0.33 | 0.4 | |||
| 6.0 | VIN = VIH or VIL, IOUT ≤ 5.2 mA |
0.2 | 0.26 | 0.33 | 0.4 | |||
| IIN | Maximum Input Current | 6.0 | VIN = VCC or GND | - | ±0.1 | ±1.0 | ±1.0 | μΑ |
| ICC | Maximum Quiescent Supply Current | 6.0 | VIN = VCC or GND, IOUT = 0 μΑ |
- | 20 | - | 40 | μΑ |
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. For a power supply of 5 V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5 V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5 V and 4.5 V respectively. (The VIH value at 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
AC Electrical Characteristics
(VCC = 5 V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns)
| Symbol | Parameter | Conditions | Typ. | Guaranteed Limit | Unit |
|---|---|---|---|---|---|
| tPHL, tPLH | Maximum Propagation Delay | 8 | 15 | ns |
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC Electrical Characteristics
(VCC = 2.0 V to 6.0 V, CL = 50 pF, tr = tf = 6 ns, unless otherwise specified)
| Symbol | Parameter | VCC (V) | Conditions | Guaranteed Limits | Unit | |||
|---|---|---|---|---|---|---|---|---|
| TA = 25°C Typ. | TA = -40°C to 85°C | TA = -55°C to 125°C | ||||||
| tPHL, tPLH | Maximum Propagation Delay | 2.0 | 45 | 90 | 113 | 134 | ns | |
| 4.5 | 9 | 18 | 23 | 27 | ||||
| 6.0 | 8 | 15 | 19 | 23 | ||||
| tTLH, tTHL | Maximum Output Rise and Fall Time | 2.0 | 30 | 75 | 95 | 110 | ns | |
| 4.5 | 8 | 15 | 19 | 22 | ||||
| 6.0 | 7 | 13 | 16 | 19 | ||||
| CPD | Power Dissipation Capacitance (Note 3) (per gate) | 20 | - | - | - | pF | ||
| CIN | Maximum Input Capacitance | 5 | 10 | 10 | 10 | pF | ||
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
Ordering Information
| Device | Marking | Package | Shipping |
|---|---|---|---|
| MM74HC00M | HC00A | SOIC-14 NB (Pb-Free and Halide Free) | 55 Units / Tube |
| MM74HC00MX | HC00A | TSSOP-14 (Pb-Free and Halide Free) | 2500 / Tape & Reel |
| MM74HC00MTCX | HC00A | TSSOP-14 (Pb-Free and Halide Free) | 2500 / Tape & Reel |
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
NOTE: All packages are lead free per JEDEC: J-STD-020B standard.
Package Outline: SOIC-14 NB
CASE 751A-03, ISSUE L
Date: 03 FEB 2016
Scale: 1:1
Diagram:
[Diagram showing SOIC-14 package dimensions with labels for D, E, A, A1, A3, b, c, e, H, h, L, M, and angle indicators]
Dimensions (Millimeters/Inches):
| DIM | MIN | MAX | MIN | MAX |
|---|---|---|---|---|
| A | 1.35 | 1.75 | 0.054 | 0.068 |
| A1 | 0.10 | 0.25 | 0.004 | 0.010 |
| A3 | 0.19 | 0.25 | 0.008 | 0.010 |
| b | 0.35 | 0.49 | 0.014 | 0.019 |
| c | 0.15 | 0.25 | 0.006 | 0.010 |
| D | 8.55 | 8.75 | 0.337 | 0.344 |
| E | 3.80 | 4.00 | 0.150 | 0.157 |
| e | 1.27 BSC | 0.050 BSC | ||
| H | 5.80 | 6.20 | 0.228 | 0.244 |
| h | 0.25 | 0.50 | 0.010 | 0.019 |
| L | 0.40 | 1.25 | 0.016 | 0.049 |
| M | 0° 7° | 0° 7° | ||
Soldering Footprint:
[Diagram showing soldering footprint for SOIC-14 package with dimensions]
Generic Marking Diagram:
[Diagram showing generic marking for SOIC-14 package with placeholders for device code, assembly location, wafer lot, year, work week, and Pb-Free indicator]
*This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "•", may or may not be present. Some products may not follow the Generic Marking.
Package Outline: TSSOP-14 WB
CASE 948G, ISSUE C
Date: 17 FEB 2016
Scale: 2:1
Diagram:
[Diagram showing TSSOP-14 package dimensions with labels for A, B, C, D, F, G, H, J, J1, K, K1, L, M, N, U, V, W, and angle indicators]
Dimensions (Millimeters/Inches):
| DIM | MIN | MAX | MIN | MAX |
|---|---|---|---|---|
| A | 4.90 | 5.10 | 0.193 | 0.200 |
| B | 4.30 | 4.50 | 0.169 | 0.177 |
| C | 1.20 | 0.047 | ||
| D | 0.05 | 0.15 | 0.002 | 0.006 |
| F | 0.50 | 0.60 | 0.020 | 0.024 |
| G | 0.50 | 0.75 | 0.020 | 0.030 |
| H | 0.65 BSC | 0.026 BSC | ||
| J | 0.09 | 0.20 | 0.004 | 0.008 |
| J1 | 0.09 | 0.16 | 0.004 | 0.006 |
| K | 0.19 | 0.30 | 0.007 | 0.012 |
| K1 | 0.19 | 0.25 | 0.007 | 0.010 |
| L | 6.40 BSC | 0.252 BSC | ||
| M | 0° 8° | 0° 8° | ||
Soldering Footprint:
[Diagram showing soldering footprint for TSSOP-14 WB package with dimensions]
Generic Marking Diagram:
[Diagram showing generic marking for TSSOP-14 WB package with placeholders for device code, assembly location, wafer lot, year, work week, and Pb-Free indicator]
*This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "•", may or may not be present. Some products may not follow the Generic Marking.
Additional Information
Technical Publications:
Technical Library: www.onsemi.com/design/resources/technical-documentation
onsemi Website: www.onsemi.com
Online Support: www.onsemi.com/support
For additional information, please contact your local Sales Representative at www.onsemi.com/support/sales
